2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA_COMMON_H_
9 #define _TEGRA_COMMON_H_
10 #include <linux/sizes.h>
11 #include <linux/stringify.h>
14 * High Level Configuration Options
16 #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
17 #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
19 #include <asm/arch/tegra.h> /* get chip and board defs */
21 /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */
23 #define CONFIG_SYS_TIMER_RATE 1000000
24 #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
27 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
30 #define CONFIG_ENV_VARS_UBOOT_CONFIG
31 #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
34 * NS16550 Configuration
36 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
39 * Common HW configuration.
40 * If this varies between SoCs later, move to tegraNN-common.h
41 * Note: This is number of devices, not max device ID.
43 #define CONFIG_SYS_MMC_MAX_DEVICE 4
46 * select serial console configuration
48 #define CONFIG_CONS_INDEX 1
50 /* allow to overwrite serial and ethaddr */
51 #define CONFIG_ENV_OVERWRITE
52 #define CONFIG_BAUDRATE 115200
54 /* turn on command-line edit/hist/auto */
55 #define CONFIG_COMMAND_HISTORY
57 #define CONFIG_SYS_NO_FLASH
60 * Increasing the size of the IO buffer as default nfsargs size is more
61 * than 256 and so it is not possible to edit it
63 #define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */
64 /* Print Buffer Size */
65 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
66 sizeof(CONFIG_SYS_PROMPT) + 16)
67 #define CONFIG_SYS_MAXARGS 64 /* max number of command args */
69 /* Boot Argument Buffer Size */
70 #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
72 #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
73 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
75 /*-----------------------------------------------------------------------
78 #define CONFIG_NR_DRAM_BANKS 2
79 #define PHYS_SDRAM_1 NV_PA_SDRC_CS0
80 #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
82 #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
83 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
85 #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
87 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
88 #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
89 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
90 CONFIG_SYS_INIT_RAM_SIZE - \
91 GENERATED_GBL_DATA_SIZE)
93 #define CONFIG_CMD_ENTERRCM
96 #define CONFIG_SPL_FRAMEWORK
97 #define CONFIG_SPL_BOARD_INIT
98 #define CONFIG_SPL_NAND_SIMPLE
99 #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \
100 CONFIG_SPL_TEXT_BASE)
101 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
103 /* Misc utility code */
104 #define CONFIG_BOUNCE_BUFFER
105 #define CONFIG_CRC32_VERIFY
107 #ifndef CONFIG_SPL_BUILD
108 #include <config_distro_defaults.h>
109 #define CONFIG_FAT_WRITE
112 #endif /* _TEGRA_COMMON_H_ */