2 * (C) Copyright 2010-2012
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA30_COMMON_H_
9 #define _TEGRA30_COMMON_H_
10 #include "tegra-common.h"
13 * Errata configuration
15 #define CONFIG_ARM_ERRATA_743622
16 #define CONFIG_ARM_ERRATA_751472
19 * NS16550 Configuration
21 #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
24 * High Level Configuration Options
26 #define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
28 /* Environment information, boards can override if required */
29 #define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
32 * Miscellaneous configurable options
34 #define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
35 #define CONFIG_STACKBASE 0x82800000 /* 40MB */
37 /*-----------------------------------------------------------------------
40 #define CONFIG_SYS_TEXT_BASE 0x8010E000
43 * Memory layout for where various images get loaded by boot scripts:
45 * scriptaddr can be pretty much anywhere that doesn't conflict with something
46 * else. Put it above BOOTMAPSZ to eliminate conflicts.
48 * kernel_addr_r must be within the first 128M of RAM in order for the
49 * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
50 * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
51 * should not overlap that area, or the kernel will have to copy itself
52 * somewhere else before decompression. Similarly, the address of any other
53 * data passed to the kernel shouldn't overlap the start of RAM. Pushing
54 * this up to 16M allows for a sizable kernel to be decompressed below the
55 * compressed load address.
57 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
58 * the compressed kernel to be up to 16M too.
60 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
61 * for the FDT/DTB to be up to 1M, which is hopefully plenty.
63 #define MEM_LAYOUT_ENV_SETTINGS \
64 "scriptaddr=0x90000000\0" \
65 "kernel_addr_r=0x81000000\0" \
66 "fdt_addr_r=0x82000000\0" \
67 "ramdisk_addr_r=0x82100000\0"
70 #define CONFIG_SPL_TEXT_BASE 0x80108000
71 #define CONFIG_SYS_SPL_MALLOC_START 0x80090000
72 #define CONFIG_SPL_STACK 0x800ffffc
74 /* Total I2C ports on Tegra30 */
75 #define TEGRA_I2C_NUM_CONTROLLERS 5
77 /* For USB EHCI controller */
78 #define CONFIG_EHCI_IS_TDI
80 #endif /* _TEGRA30_COMMON_H_ */