2 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_THEADORABLE_H
8 #define _CONFIG_THEADORABLE_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_DISPLAY_BOARDINFO_LATE
16 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
17 * for DDR ECC byte filling in the SPL before loading the main
20 #define CONFIG_SYS_TEXT_BASE 0x00800000
21 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
24 * Commands configuration
26 #define CONFIG_CMD_ENV
27 #define CONFIG_CMD_SATA
30 * The debugging version enables USB support via defconfig.
31 * This version should also enable all other non-production
32 * interfaces / features.
35 #define CONFIG_CMD_PCI
39 #define CONFIG_SYS_I2C
40 #define CONFIG_SYS_I2C_MVTWSI
41 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
42 #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
43 #define CONFIG_SYS_I2C_SLAVE 0x0
44 #define CONFIG_SYS_I2C_SPEED 100000
46 /* USB/EHCI configuration */
47 #define CONFIG_EHCI_IS_TDI
48 #define CONFIG_USB_MAX_CONTROLLER_COUNT 3
50 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
52 /* SPI NOR flash default params, used by sf commands */
53 #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */
54 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
56 /* Environment in SPI NOR flash */
57 #define CONFIG_ENV_IS_IN_SPI_FLASH
58 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
59 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
60 #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */
61 #define CONFIG_ENV_OVERWRITE
63 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
64 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
66 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
67 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
68 #define CONFIG_SYS_ALT_MEMTEST
69 #define CONFIG_PREBOOT
71 /* Keep device tree and initrd in lower memory so the kernel can access them */
72 #define CONFIG_EXTRA_ENV_SETTINGS \
73 "fdt_high=0x10000000\0" \
74 "initrd_high=0x10000000\0"
77 #define CONFIG_SYS_SATA_MAX_DEVICE 1
78 #define CONFIG_SATA_MV
81 #define CONFIG_EFI_PARTITION
82 #define CONFIG_DOS_PARTITION
84 /* Additional FS support/configuration */
85 #define CONFIG_SUPPORT_VFAT
89 #ifndef CONFIG_SPL_BUILD
91 #define CONFIG_PCI_MVEBU
92 #define CONFIG_PCI_PNP
93 #define CONFIG_BOARD_LATE_INIT /* for PEX switch test */
97 /* Enable LCD and reserve 512KB from top of memory*/
98 #define CONFIG_SYS_MEM_TOP_HIDE 0x80000
101 #define CONFIG_CFB_CONSOLE
102 #define CONFIG_VGA_AS_SINGLE_DEVICE
103 #define CONFIG_CMD_BMP
105 /* FPGA programming support */
107 #define CONFIG_FPGA_ALTERA
108 #define CONFIG_FPGA_STRATIX_V
113 #define CONFIG_BOOTCOUNT_LIMIT
114 #define CONFIG_BOOTCOUNT_RAM
115 /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
116 #define BOOTCOUNT_ADDR 0x1000
119 * mv-common.h should be defined after CMD configs since it used them
120 * to enable certain macros
122 #include "mv-common.h"
125 * Memory layout while starting into the bin_hdr via the
128 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
129 * 0x4000.4030 bin_hdr start address
130 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
131 * 0x4007.fffc BootROM stack top
133 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
134 * L2 cache thus cannot be used.
138 /* Defines for SPL */
139 #define CONFIG_SPL_FRAMEWORK
140 #define CONFIG_SPL_TEXT_BASE 0x40004030
141 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
143 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
144 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
146 #ifdef CONFIG_SPL_BUILD
147 #define CONFIG_SYS_MALLOC_SIMPLE
150 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
151 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
153 #define CONFIG_SPL_LIBCOMMON_SUPPORT
154 #define CONFIG_SPL_LIBGENERIC_SUPPORT
155 #define CONFIG_SPL_SERIAL_SUPPORT
156 #define CONFIG_SPL_I2C_SUPPORT
158 /* SPL related SPI defines */
159 #define CONFIG_SPL_SPI_SUPPORT
160 #define CONFIG_SPL_SPI_FLASH_SUPPORT
161 #define CONFIG_SPL_SPI_LOAD
162 #define CONFIG_SPL_SPI_BUS 0
163 #define CONFIG_SPL_SPI_CS 0
164 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000
165 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS
167 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
168 #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */
170 #endif /* _CONFIG_THEADORABLE_H */