git.sur5r.net Git - u-boot/blob - include/configs/trizepsiv.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefano Babic, DENX Gmbh, sbabic@denx.de
   4  *
   5  * (C) Copyright 2004
   6  * Robert Whaley, Applied Data Systems, Inc. rwhaley@applieddata.net
   7  *
   8  * (C) Copyright 2002
   9  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  10  *
  11  * (C) Copyright 2002
  12  * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  13  * Marius Groeger <mgroeger@sysgo.de>
  14  *
  15  * Configuation settings for the LUBBOCK board.
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43 #define CONFIG_PXA27X           1       /* This is an PXA27x CPU    */
  44
  45 #define CONFIG_MMC              1
  46 #define BOARD_LATE_INIT         1
  47
  48 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
  49
  50 /* we will never enable dcache, because we have to setup MMU first */
  51 #define CONFIG_SYS_NO_DCACHE
  52
  53 #define RTC
  54
  55 /*
  56  * Size of malloc() pool
  57  */
  58 #define CONFIG_SYS_MALLOC_LEN       (CONFIG_ENV_SIZE + 128*1024)
  59 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
  60
  61 /*
  62  * Hardware drivers
  63  */
  64
  65 /*
  66  * select serial console configuration
  67  */
  68 #define CONFIG_PXA_SERIAL
  69 #define CONFIG_SERIAL_MULTI
  70 #define CONFIG_FFUART          1       /* we use FFUART on Conxs */
  71 #define CONFIG_BTUART          1       /* we use BTUART on Conxs */
  72 #define CONFIG_STUART          1       /* we use STUART on Conxs */
  73
  74 /* allow to overwrite serial and ethaddr */
  75 #define CONFIG_ENV_OVERWRITE
  76
  77 #define CONFIG_BAUDRATE        38400
  78
  79 #define CONFIG_DOS_PARTITION   1
  80
  81 /*
  82  * Command line configuration.
  83  */
  84 #include <config_cmd_default.h>
  85
  86 #define CONFIG_CMD_FAT
  87 #define CONFIG_CMD_IMLS
  88 #define CONFIG_CMD_PING
  89 #define CONFIG_CMD_USB
  90
  91 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  92
  93 #undef CONFIG_SHOW_BOOT_PROGRESS
  94
  95 #define CONFIG_BOOTDELAY        3
  96 #define CONFIG_SERVERIP         192.168.1.99
  97 #define CONFIG_BOOTCOMMAND      "run boot_flash"
  98 #define CONFIG_BOOTARGS         "console=ttyS0,38400 ramdisk_size=12288"\
  99                                 " rw root=/dev/ram initrd=0xa0800000,5m"
 100
 101 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 102         "program_boot_mmc="                                             \
 103                         "mw.b 0xa0010000 0xff 0x20000; "                \
 104                         "if      mmcinit && "                           \
 105                                 "fatload mmc 0 0xa0010000 u-boot.bin; " \
 106                         "then "                                         \
 107                                 "protect off 0x0 0x1ffff; "             \
 108                                 "erase 0x0 0x1ffff; "                   \
 109                                 "cp.b 0xa0010000 0x0 0x20000; "         \
 110                         "fi\0"                                          \
 111         "program_uzImage_mmc="                                          \
 112                         "mw.b 0xa0010000 0xff 0x180000; "               \
 113                         "if      mmcinit && "                           \
 114                                 "fatload mmc 0 0xa0010000 uzImage; "    \
 115                         "then "                                         \
 116                                 "protect off 0x40000 0x1bffff; "        \
 117                                 "erase 0x40000 0x1bffff; "              \
 118                                 "cp.b 0xa0010000 0x40000 0x180000; "    \
 119                         "fi\0"                                          \
 120         "program_ramdisk_mmc="                                          \
 121                         "mw.b 0xa0010000 0xff 0x500000; "               \
 122                         "if      mmcinit && "                           \
 123                                 "fatload mmc 0 0xa0010000 ramdisk.gz; " \
 124                         "then "                                         \
 125                                 "protect off 0x1c0000 0x6bffff; "       \
 126                                 "erase 0x1c0000 0x6bffff; "             \
 127                                 "cp.b 0xa0010000 0x1c0000 0x500000; "   \
 128                         "fi\0"                                          \
 129         "boot_mmc="                                                     \
 130                         "if      mmcinit && "                           \
 131                                 "fatload mmc 0 0xa0030000 uzImage && "  \
 132                                 "fatload mmc 0 0xa0800000 ramdisk.gz; " \
 133                         "then "                                         \
 134                                 "bootm 0xa0030000; "                    \
 135                         "fi\0"                                          \
 136         "boot_flash="                                                   \
 137                         "cp.b 0x1c0000 0xa0800000 0x500000; "           \
 138                         "bootm 0x40000\0"                               \
 139
 140 #define CONFIG_SETUP_MEMORY_TAGS 1
 141 #define CONFIG_CMDLINE_TAG       1      /* enable passing of ATAGs      */
 142 /* #define CONFIG_INITRD_TAG     1 */
 143
 144 #if defined(CONFIG_CMD_KGDB)
 145 #define CONFIG_KGDB_BAUDRATE    230400          /* speed to run kgdb serial port */
 146 #define CONFIG_KGDB_SER_INDEX   2               /* which serial port to use */
 147 #endif
 148
 149 /*
 150  * Miscellaneous configurable options
 151  */
 152 #define CONFIG_SYS_HUSH_PARSER          1
 153 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 154
 155 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 156 #ifdef CONFIG_SYS_HUSH_PARSER
 157 #define CONFIG_SYS_PROMPT               "$ "            /* Monitor Command Prompt */
 158 #else
 159 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt */
 160 #endif
 161 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 162 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 163 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 164 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 165 #define CONFIG_SYS_DEVICE_NULLDEV       1
 166
 167 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on     */
 168 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM   */
 169
 170 #define CONFIG_SYS_LOAD_ADDR            0xa1000000      /* default load address */
 171
 172 #define CONFIG_SYS_HZ                   1000
 173 #define CONFIG_SYS_CPUSPEED             0x207           /* need to look more closely, I think this is Turbo = 2x, L=91Mhz */
 174
 175                                                 /* valid baudrates */
 176 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 177
 178 #ifdef CONFIG_MMC
 179 #define CONFIG_PXA_MMC
 180 #define CONFIG_CMD_MMC
 181 #define CONFIG_SYS_MMC_BASE             0xF0000000
 182 #endif
 183
 184 /*
 185  * Stack sizes
 186  *
 187  * The stack sizes are set up in start.S using the settings below
 188  */
 189 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 190 #ifdef CONFIG_USE_IRQ
 191 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 192 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 193 #endif
 194
 195 /*
 196  * Physical Memory Map
 197  */
 198 #define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
 199 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 200 #define PHYS_SDRAM_1_SIZE       0x04000000 /* 64 MB */
 201 #define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
 202 #define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
 203 #define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
 204 #define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
 205 #define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
 206 #define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 207
 208 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 209
 210 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 211 #define CONFIG_SYS_DRAM_SIZE            0x04000000
 212
 213 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 214
 215 /*
 216  * GPIO settings
 217  */
 218 #define CONFIG_SYS_GPSR0_VAL            0x00018000
 219 #define CONFIG_SYS_GPSR1_VAL            0x00000000
 220 #define CONFIG_SYS_GPSR2_VAL            0x400dc000
 221 #define CONFIG_SYS_GPSR3_VAL            0x00000000
 222 #define CONFIG_SYS_GPCR0_VAL            0x00000000
 223 #define CONFIG_SYS_GPCR1_VAL            0x00000000
 224 #define CONFIG_SYS_GPCR2_VAL            0x00000000
 225 #define CONFIG_SYS_GPCR3_VAL            0x00000000
 226 #define CONFIG_SYS_GPDR0_VAL            0x00018000
 227 #define CONFIG_SYS_GPDR1_VAL            0x00028801
 228 #define CONFIG_SYS_GPDR2_VAL            0x520dc000
 229 #define CONFIG_SYS_GPDR3_VAL            0x0001E000
 230 #define CONFIG_SYS_GAFR0_L_VAL          0x801c0000
 231 #define CONFIG_SYS_GAFR0_U_VAL          0x00000013
 232 #define CONFIG_SYS_GAFR1_L_VAL          0x6990100A
 233 #define CONFIG_SYS_GAFR1_U_VAL          0x00000008
 234 #define CONFIG_SYS_GAFR2_L_VAL          0xA0000000
 235 #define CONFIG_SYS_GAFR2_U_VAL          0x010900F2
 236 #define CONFIG_SYS_GAFR3_L_VAL          0x54000003
 237 #define CONFIG_SYS_GAFR3_U_VAL          0x00002401
 238 #define CONFIG_SYS_GRER0_VAL            0x00000000
 239 #define CONFIG_SYS_GRER1_VAL            0x00000000
 240 #define CONFIG_SYS_GRER2_VAL            0x00000000
 241 #define CONFIG_SYS_GRER3_VAL            0x00000000
 242
 243 #define CONFIG_SYS_GFER1_VAL            0x00000000
 244 #define CONFIG_SYS_GFER3_VAL            0x00000020
 245
 246 #if CONFIG_POLARIS
 247 #define CONFIG_SYS_GFER0_VAL            0x00000001
 248 #define CONFIG_SYS_GFER2_VAL            0x00200000
 249 #else
 250 #define CONFIG_SYS_GFER0_VAL            0x00000000
 251 #define CONFIG_SYS_GFER2_VAL            0x00000000
 252 #endif
 253
 254 #define CONFIG_SYS_PSSR_VAL             0x20    /* CHECK */
 255
 256 /*
 257  * Clock settings
 258  */
 259 #define CONFIG_SYS_CKEN         0x01FFFFFF      /* CHECK */
 260 #define CONFIG_SYS_CCCR         0x02000290 /*   520Mhz */
 261
 262 /*
 263  * Memory settings
 264  */
 265
 266 #define CONFIG_SYS_MSC0_VAL             0x4df84df0
 267 #define CONFIG_SYS_MSC1_VAL             0x7ff87ff4
 268 #if CONFIG_POLARIS
 269 #define CONFIG_SYS_MSC2_VAL             0xa2697ff8
 270 #else
 271 #define CONFIG_SYS_MSC2_VAL             0xa26936d4
 272 #endif
 273 #define CONFIG_SYS_MDCNFG_VAL           0x880009C9
 274 #define CONFIG_SYS_MDREFR_VAL           0x20ca201e
 275 #define CONFIG_SYS_MDMRS_VAL            0x00220022
 276
 277 #define CONFIG_SYS_FLYCNFG_VAL          0x00000000
 278 #define CONFIG_SYS_SXCNFG_VAL           0x40044004
 279
 280 /*
 281  * PCMCIA and CF Interfaces
 282  */
 283 #define CONFIG_SYS_MECR_VAL             0x00000001
 284 #define CONFIG_SYS_MCMEM0_VAL           0x00004204
 285 #define CONFIG_SYS_MCMEM1_VAL           0x00010204
 286 #define CONFIG_SYS_MCATT0_VAL           0x00010504
 287 #define CONFIG_SYS_MCATT1_VAL           0x00010504
 288 #define CONFIG_SYS_MCIO0_VAL            0x00008407
 289 #define CONFIG_SYS_MCIO1_VAL            0x0000c108
 290
 291 #define CONFIG_NET_MULTI                1
 292 #define CONFIG_DRIVER_DM9000            1
 293
 294 #if CONFIG_POLARIS
 295 #define CONFIG_DM9000_BASE              0x0C800000
 296 #else
 297 #define CONFIG_DM9000_BASE              0x08000000
 298 #endif
 299
 300 #define DM9000_IO                       CONFIG_DM9000_BASE
 301 #define DM9000_DATA                     (CONFIG_DM9000_BASE+0x8004)
 302
 303 #define CONFIG_USB_OHCI_NEW     1
 304 #define CONFIG_SYS_USB_OHCI_BOARD_INIT  1
 305 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      3
 306 #define CONFIG_SYS_USB_OHCI_REGS_BASE   0x4C000000
 307 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "trizepsiv"
 308 #define CONFIG_USB_STORAGE      1
 309 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 310
 311 /*
 312  * FLASH and environment organization
 313  */
 314
 315 #define CONFIG_SYS_FLASH_CFI
 316 #define CONFIG_FLASH_CFI_DRIVER 1
 317
 318 #define CONFIG_SYS_MONITOR_BASE 0
 319 #define CONFIG_SYS_MONITOR_LEN          0x40000
 320
 321 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 322 #define CONFIG_SYS_MAX_FLASH_SECT       4 + 255  /* max number of sectors on one chip   */
 323
 324 /* timeout values are in ticks */
 325 #define CONFIG_SYS_FLASH_ERASE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 326 #define CONFIG_SYS_FLASH_WRITE_TOUT     (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 327
 328 /* write flash less slowly */
 329 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
 330
 331 /* Unlock to be used with Intel chips */
 332 #define CONFIG_SYS_FLASH_PROTECTION     1
 333
 334 /* Flash environment locations */
 335 #define CONFIG_ENV_IS_IN_FLASH  1
 336 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + CONFIG_SYS_MONITOR_LEN) /* Addr of Environment Sector   */
 337 #define CONFIG_ENV_SIZE         0x40000 /* Total Size of Environment            */
 338 #define CONFIG_ENV_SECT_SIZE    0x40000 /* Total Size of Environment Sector     */
 339
 340 /* Address and size of Redundant Environment Sector     */
 341 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE)
 342 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 343
 344 #endif  /* __CONFIG_H */