2 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
5 * See file CREDITS for list of people who contributed to this project.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 * High Level Configuration Options
29 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
30 #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
31 #define CONFIG_V38B 1 /* ...on V38B board */
32 #define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
34 #define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
35 #define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
37 #undef CONFIG_HW_WATCHDOG /* don't use watchdog */
39 #define CONFIG_NETCONSOLE 1
41 #define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
42 #define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
44 #define CFG_XLB_PIPELINING 1 /* gives better performance */
46 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
47 #define BOOTFLAG_WARM 0x02 /* Software reboot */
50 * Serial console configuration
52 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
53 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
54 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
59 #define SDRAM_DDR 1 /* is DDR */
60 /* Settings for XLB = 132 MHz */
61 #define SDRAM_MODE 0x018D0000
62 #define SDRAM_EMODE 0x40090000
63 #define SDRAM_CONTROL 0x704f0f00
64 #define SDRAM_CONFIG1 0x73722930
65 #define SDRAM_CONFIG2 0x47770000
66 #define SDRAM_TAPDELAY 0x10000000
76 #define CONFIG_MAC_PARTITION 1
77 #define CONFIG_DOS_PARTITION 1
82 #define CONFIG_USB_OHCI
83 #define CONFIG_USB_STORAGE
84 #define CONFIG_USB_CLOCK 0x0001BBBB
85 #define CONFIG_USB_CONFIG 0x00001000
89 * Command line configuration.
91 #include <config_cmd_default.h>
93 #define CONFIG_CMD_FAT
94 #define CONFIG_CMD_I2C
95 #define CONFIG_CMD_IDE
96 #define CONFIG_CMD_PING
97 #define CONFIG_CMD_DHCP
98 #define CONFIG_CMD_DIAG
99 #define CONFIG_CMD_IRQ
100 #define CONFIG_CMD_JFFS2
101 #define CONFIG_CMD_MII
102 #define CONFIG_CMD_SDRAM
103 #define CONFIG_CMD_DATE
104 #define CONFIG_CMD_USB
105 #define CONFIG_CMD_FAT
108 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
111 * Boot low with 16 MB Flash
113 #define CFG_LOWBOOT 1
114 #define CFG_LOWBOOT16 1
119 #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
121 #define CONFIG_PREBOOT "echo;" \
122 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
125 #undef CONFIG_BOOTARGS
127 #define CONFIG_EXTRA_ENV_SETTINGS \
128 "bootcmd=run net_nfs\0" \
130 "baudrate=115200\0" \
131 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
132 "filesystem over NFS; echo\0" \
134 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
135 "addip=setenv bootargs $(bootargs) " \
136 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
137 "$(netmask):$(hostname):$(netdev):off panic=1\0" \
138 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
139 "flash_self=run ramargs addip;bootm $(kernel_addr) " \
140 "$(ramdisk_addr)\0" \
141 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
142 "nfsargs=setenv bootargs root=/dev/nfs rw " \
143 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \
145 "ethact=FEC ETHERNET\0" \
146 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
147 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
148 "cp.b 200000 ff000000 $(filesize);" \
149 "prot on ff000000 ff03ffff\0" \
150 "load=tftp 200000 $(u-boot)\0" \
151 "netmask=255.255.0.0\0" \
152 "ipaddr=192.168.160.18\0" \
153 "serverip=192.168.1.1\0" \
154 "ethaddr=00:e0:ee:00:05:2e\0" \
155 "bootfile=/tftpboot/v38b/uImage\0" \
156 "u-boot=/tftpboot/v38b/u-boot.bin\0" \
159 #define CONFIG_BOOTCOMMAND "run net_nfs"
161 #if defined(CONFIG_MPC5200)
163 * IPB Bus clocking configuration.
165 #undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
171 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
172 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
173 #define CFG_I2C_SPEED 100000 /* 100 kHz */
174 #define CFG_I2C_SLAVE 0x7F
177 * EEPROM configuration
179 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
180 #define CFG_I2C_EEPROM_ADDR_LEN 1
181 #define CFG_EEPROM_PAGE_WRITE_BITS 3
182 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
187 #define CFG_I2C_RTC_ADDR 0x51
190 * Flash configuration - use CFI driver
192 #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
193 #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
194 #define CFG_FLASH_CFI_AMD_RESET 1
195 #define CFG_FLASH_BASE 0xFF000000
196 #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
197 #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
198 #define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */
199 #define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
200 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
203 * Environment settings
205 #define CFG_ENV_IS_IN_FLASH 1
206 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
207 #define CFG_ENV_SIZE 0x10000
208 #define CFG_ENV_SECT_SIZE 0x10000
209 #define CONFIG_ENV_OVERWRITE 1
214 #define CFG_MBAR 0xF0000000
215 #define CFG_SDRAM_BASE 0x00000000
216 #define CFG_DEFAULT_MBAR 0x80000000
218 /* Use SRAM until RAM will be available */
219 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
220 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
222 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
223 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
224 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
226 #define CFG_MONITOR_BASE TEXT_BASE
227 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
228 # define CFG_RAMBOOT 1
231 #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
232 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
233 #define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
236 * Ethernet configuration
238 #define CONFIG_MPC5xxx_FEC 1
239 #define CONFIG_PHY_ADDR 0x00
245 #define CFG_GPS_PORT_CONFIG 0x90001404
248 * Miscellaneous configurable options
250 #define CFG_LONGHELP /* undef to save memory */
251 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
252 #if defined(CONFIG_CMD_KGDB)
253 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
255 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
257 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
258 #define CFG_MAXARGS 16 /* max number of command args */
259 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
261 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
262 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
264 #define CFG_LOAD_ADDR 0x100000 /* default load address */
266 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
268 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
269 #if defined(CONFIG_CMD_KGDB)
270 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
274 * Various low-level settings
276 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
277 #define CFG_HID0_FINAL HID0_ICE
279 #define CFG_BOOTCS_START CFG_FLASH_BASE
280 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
281 #define CFG_BOOTCS_CFG 0x00047801
282 #define CFG_CS0_START CFG_FLASH_BASE
283 #define CFG_CS0_SIZE CFG_FLASH_SIZE
285 #define CFG_CS_BURST 0x00000000
286 #define CFG_CS_DEADCYCLE 0x33333333
288 #define CFG_RESET_ADDRESS 0xff000000
291 * IDE/ATA (supports IDE harddisk)
293 #undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
294 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
295 #undef CONFIG_IDE_LED /* LED for ide not supported */
297 #define CONFIG_IDE_RESET /* reset for ide supported */
298 #define CONFIG_IDE_PREINIT
300 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
301 #define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
303 #define CFG_ATA_IDE0_OFFSET 0x0000
305 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
307 #define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
309 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */
311 #define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
313 #define CFG_ATA_STRIDE 4 /* Interval between registers */
318 #define CONFIG_STATUS_LED /* Status LED enabled */
319 #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
321 #define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
323 typedef unsigned int led_id_t;
325 #define __led_toggle(_msk) \
327 *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
330 #define __led_set(_msk, _st) \
333 *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
335 *((volatile long *) (CFG_LED_BASE)) |= (_msk); \
338 #define __led_init(_msk, st) \
340 *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
342 #endif /* __ASSEMBLY__ */
344 #endif /* __CONFIG_H */