git.sur5r.net Git - u-boot/blob - include/configs/vexpress_aemv8a.h

   1 /*
   2  * Configuration for Versatile Express. Parts were derived from other ARM
   3  *   configurations.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __VEXPRESS_AEMV8A_H
   9 #define __VEXPRESS_AEMV8A_H
  10
  11 /* We use generic board for v8 Versatile Express */
  12 #define CONFIG_SYS_GENERIC_BOARD
  13
  14 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  15 #ifndef CONFIG_SEMIHOSTING
  16 #error CONFIG_TARGET_VEXPRESS64_BASE_FVP requires CONFIG_SEMIHOSTING
  17 #endif
  18 #define CONFIG_ARMV8_SWITCH_TO_EL1
  19 #endif
  20
  21 #define CONFIG_REMAKE_ELF
  22
  23 #if !defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && \
  24     !defined(CONFIG_TARGET_VEXPRESS64_JUNO)
  25 /* Base FVP and Juno not using GICv3 yet */
  26 #define CONFIG_GICV3
  27 #endif
  28
  29 /*#define CONFIG_ARMV8_SWITCH_TO_EL1*/
  30
  31 #define CONFIG_SUPPORT_RAW_INITRD
  32
  33 /* Cache Definitions */
  34 #define CONFIG_SYS_DCACHE_OFF
  35 #define CONFIG_SYS_ICACHE_OFF
  36
  37 #define CONFIG_IDENT_STRING             " vexpress_aemv8a"
  38 #define CONFIG_BOOTP_VCI_STRING         "U-boot.armv8.vexpress_aemv8a"
  39
  40 /* Link Definitions */
  41 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
  42 /* ATF loads u-boot here for BASE_FVP model */
  43 #define CONFIG_SYS_TEXT_BASE            0x88000000
  44 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
  45 #elif CONFIG_TARGET_VEXPRESS64_JUNO
  46 #define CONFIG_SYS_TEXT_BASE            0xe0000000
  47 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  48 #else
  49 #define CONFIG_SYS_TEXT_BASE            0x80000000
  50 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
  51 #endif
  52
  53 /* Flat Device Tree Definitions */
  54 #define CONFIG_OF_LIBFDT
  55
  56 /* CS register bases for the original memory map. */
  57 #define V2M_PA_CS0                      0x00000000
  58 #define V2M_PA_CS1                      0x14000000
  59 #define V2M_PA_CS2                      0x18000000
  60 #define V2M_PA_CS3                      0x1c000000
  61 #define V2M_PA_CS4                      0x0c000000
  62 #define V2M_PA_CS5                      0x10000000
  63
  64 #define V2M_PERIPH_OFFSET(x)            (x << 16)
  65 #define V2M_SYSREGS                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
  66 #define V2M_SYSCTL                      (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
  67 #define V2M_SERIAL_BUS_PCI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
  68
  69 #define V2M_BASE                        0x80000000
  70
  71 /* Common peripherals relative to CS7. */
  72 #define V2M_AACI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
  73 #define V2M_MMCI                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
  74 #define V2M_KMI0                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
  75 #define V2M_KMI1                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
  76
  77 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
  78 #define V2M_UART0                       0x7ff80000
  79 #define V2M_UART1                       0x7ff70000
  80 #else /* Not Juno */
  81 #define V2M_UART0                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
  82 #define V2M_UART1                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
  83 #define V2M_UART2                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
  84 #define V2M_UART3                       (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
  85 #endif
  86
  87 #define V2M_WDT                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
  88
  89 #define V2M_TIMER01                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
  90 #define V2M_TIMER23                     (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
  91
  92 #define V2M_SERIAL_BUS_DVI              (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
  93 #define V2M_RTC                         (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
  94
  95 #define V2M_CF                          (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
  96
  97 #define V2M_CLCD                        (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
  98
  99 /* System register offsets. */
 100 #define V2M_SYS_CFGDATA                 (V2M_SYSREGS + 0x0a0)
 101 #define V2M_SYS_CFGCTRL                 (V2M_SYSREGS + 0x0a4)
 102 #define V2M_SYS_CFGSTAT                 (V2M_SYSREGS + 0x0a8)
 103
 104 /* Generic Timer Definitions */
 105 #define COUNTER_FREQUENCY               (0x1800000)     /* 24MHz */
 106
 107 /* Generic Interrupt Controller Definitions */
 108 #ifdef CONFIG_GICV3
 109 #define GICD_BASE                       (0x2f000000)
 110 #define GICR_BASE                       (0x2f100000)
 111 #else
 112
 113 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
 114 #define GICD_BASE                       (0x2f000000)
 115 #define GICC_BASE                       (0x2c000000)
 116 #elif CONFIG_TARGET_VEXPRESS64_JUNO
 117 #define GICD_BASE                       (0x2C010000)
 118 #define GICC_BASE                       (0x2C02f000)
 119 #else
 120 #define GICD_BASE                       (0x2C001000)
 121 #define GICC_BASE                       (0x2C002000)
 122 #endif
 123 #endif
 124
 125 #define CONFIG_SYS_MEMTEST_START        V2M_BASE
 126 #define CONFIG_SYS_MEMTEST_END          (V2M_BASE + 0x80000000)
 127
 128 /* Size of malloc() pool */
 129 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (8 << 20))
 130
 131 /* Ethernet Configuration */
 132 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 133 /* The real hardware Versatile express uses SMSC9118 */
 134 #define CONFIG_SMC911X                  1
 135 #define CONFIG_SMC911X_32_BIT           1
 136 #define CONFIG_SMC911X_BASE             (0x018000000)
 137 #else
 138 /* The Vexpress64 simulators use SMSC91C111 */
 139 #define CONFIG_SMC91111                 1
 140 #define CONFIG_SMC91111_BASE            (0x01A000000)
 141 #endif
 142
 143 /* PL011 Serial Configuration */
 144 #define CONFIG_PL011_SERIAL
 145 #ifdef CONFIG_TARGET_VEXPRESS64_JUNO
 146 #define CONFIG_PL011_CLOCK              7273800
 147 #else
 148 #define CONFIG_PL011_CLOCK              24000000
 149 #endif
 150 #define CONFIG_PL01x_PORTS              {(void *)CONFIG_SYS_SERIAL0, \
 151                                          (void *)CONFIG_SYS_SERIAL1}
 152 #define CONFIG_CONS_INDEX               0
 153
 154 #define CONFIG_BAUDRATE                 115200
 155 #define CONFIG_SYS_SERIAL0              V2M_UART0
 156 #define CONFIG_SYS_SERIAL1              V2M_UART1
 157
 158 /* Command line configuration */
 159 #define CONFIG_MENU
 160 /*#define CONFIG_MENU_SHOW*/
 161 #define CONFIG_CMD_CACHE
 162 #define CONFIG_CMD_BDI
 163 #define CONFIG_CMD_BOOTI
 164 #define CONFIG_CMD_UNZIP
 165 #define CONFIG_CMD_DHCP
 166 #define CONFIG_CMD_PXE
 167 #define CONFIG_CMD_ENV
 168 #define CONFIG_CMD_IMI
 169 #define CONFIG_CMD_LOADB
 170 #define CONFIG_CMD_MEMORY
 171 #define CONFIG_CMD_MII
 172 #define CONFIG_CMD_NET
 173 #define CONFIG_CMD_PING
 174 #define CONFIG_CMD_SAVEENV
 175 #define CONFIG_CMD_RUN
 176 #define CONFIG_CMD_BOOTD
 177 #define CONFIG_CMD_ECHO
 178 #define CONFIG_CMD_SOURCE
 179 #define CONFIG_CMD_FAT
 180 #define CONFIG_DOS_PARTITION
 181
 182 /* BOOTP options */
 183 #define CONFIG_BOOTP_BOOTFILESIZE
 184 #define CONFIG_BOOTP_BOOTPATH
 185 #define CONFIG_BOOTP_GATEWAY
 186 #define CONFIG_BOOTP_HOSTNAME
 187 #define CONFIG_BOOTP_PXE
 188 #define CONFIG_BOOTP_PXE_CLIENTARCH     0x100
 189
 190 /* Miscellaneous configurable options */
 191 #define CONFIG_SYS_LOAD_ADDR            (V2M_BASE + 0x10000000)
 192
 193 /* Physical Memory Map */
 194 #define CONFIG_NR_DRAM_BANKS            1
 195 #define PHYS_SDRAM_1                    (V2M_BASE)      /* SDRAM Bank #1 */
 196 #define PHYS_SDRAM_1_SIZE               0x80000000      /* 2048 MB */
 197 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 198
 199 /* Initial environment variables */
 200 #ifdef CONFIG_TARGET_VEXPRESS64_BASE_FVP
 201 #define CONFIG_EXTRA_ENV_SETTINGS       \
 202                                 "kernel_name=uImage\0"          \
 203                                 "kernel_addr=0x80000000\0"      \
 204                                 "initrd_name=ramdisk.img\0"     \
 205                                 "initrd_addr=0x88000000\0"      \
 206                                 "fdt_name=devtree.dtb\0"        \
 207                                 "fdt_addr=0x83000000\0"         \
 208                                 "fdt_high=0xffffffffffffffff\0" \
 209                                 "initrd_high=0xffffffffffffffff\0"
 210
 211 #define CONFIG_BOOTARGS         "console=ttyAMA0 earlyprintk=pl011,"\
 212                                 "0x1c090000 debug user_debug=31 "\
 213                                 "loglevel=9"
 214
 215 #define CONFIG_BOOTCOMMAND      "smhload ${kernel_name} ${kernel_addr}; " \
 216                                 "smhload ${fdt_name} $fdt_addr; " \
 217                                 "smhload ${initrd_name} $initrd_addr initrd_end; " \
 218                                 "fdt addr $fdt_addr; fdt resize; " \
 219                                 "fdt chosen $initrd_addr $initrd_end; " \
 220                                 "bootm $kernel_addr - $fdt_addr"
 221
 222 #define CONFIG_BOOTDELAY                1
 223
 224 #else
 225
 226 #define CONFIG_EXTRA_ENV_SETTINGS       \
 227                                         "kernel_addr_r=0x80000000\0"    \
 228                                         "initrd_addr_r=0x88000000\0"    \
 229                                         "fdt_addr_r=0x83000000\0"               \
 230                                         "fdt_high=0xa0000000\0"
 231
 232 #define CONFIG_BOOTARGS                 "console=ttyAMA0,115200n8 root=/dev/ram0"
 233 #define CONFIG_BOOTCOMMAND              "bootm $kernel_addr_r " \
 234                                         "$initrd_addr_r:$initrd_size $fdt_addr_r"
 235 #define CONFIG_BOOTDELAY                -1
 236 #endif
 237
 238 /* Do not preserve environment */
 239 #define CONFIG_ENV_IS_NOWHERE           1
 240 #define CONFIG_ENV_SIZE                 0x1000
 241
 242 /* Monitor Command Prompt */
 243 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 244 #define CONFIG_SYS_PROMPT               "VExpress64# "
 245 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 246                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 247 #define CONFIG_SYS_HUSH_PARSER
 248 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 249 #define CONFIG_SYS_LONGHELP
 250 #define CONFIG_CMDLINE_EDITING
 251 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 252
 253 /* Flash memory is available on the Juno board only */
 254 #ifndef CONFIG_TARGET_VEXPRESS64_JUNO
 255 #define CONFIG_SYS_NO_FLASH
 256 #else
 257 #define CONFIG_CMD_FLASH
 258 #define CONFIG_SYS_FLASH_CFI            1
 259 #define CONFIG_FLASH_CFI_DRIVER         1
 260 #define CONFIG_SYS_FLASH_BASE           0x08000000
 261 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MiB */
 262 #define CONFIG_SYS_MAX_FLASH_BANKS      2
 263
 264 /* Timeout values in ticks */
 265 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2 * CONFIG_SYS_HZ) /* Erase Timeout */
 266 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2 * CONFIG_SYS_HZ) /* Write Timeout */
 267
 268 /* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
 269 #define CONFIG_SYS_MAX_FLASH_SECT       259             /* Max sectors */
 270 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
 271 #define CONFIG_SYS_FLASH_PROTECTION     /* The devices have real protection */
 272 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* flinfo indicates empty blocks */
 273
 274 #endif
 275
 276 #endif /* __VEXPRESS_AEMV8A_H */