2 * (C) Copyright 2009-2012
3 * Jens Scharsig <esw@bus-elekronik.de>
4 * BuS Elektronik GmbH & Co. KG
6 * Configuation settings for the VL_MA2SC board.
8 * SPDX-License-Identifier: GPL-2.0+
14 /*--------------------------------------------------------------------------*/
16 #define CONFIG_ARM926EJS /* This is an ARM926EJS Core */
17 #define CONFIG_AT91SAM9263 /* It's an Atmel AT91SAM9263 SoC*/
18 #define CONFIG_VL_MA2SC /* on an VL_MA2SC Board */
19 #define CONFIG_ARCH_CPU_INIT
20 #define CONFIG_MISC_INIT_R
22 #include <asm/hardware.h>
24 #define MACH_TYPE_VL_MA2SC 2412
25 #define CONFIG_MACH_TYPE MACH_TYPE_VL_MA2SC
27 #define CONFIG_SYS_DCACHE_OFF
30 #define CONFIG_SYS_TEXT_BASE 0x21000000
32 #define CONFIG_SYS_TEXT_BASE 0x00000000
34 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
36 #define CONFIG_IDENT_STRING " on MiS Activ 2"
37 #define CONFIG_VERSION_VARIABLE
38 #define CONFIG_AT91_GPIO
40 #if !defined(CONFIG_SYS_USE_NANDFLASH) && !defined(CONFIG_RAMLOAD)
41 #define CONFIG_SYS_USE_NORFLASH
42 #define CONFIG_SYS_USE_BOOT_NORFLASH
45 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
46 #define CONFIG_SETUP_MEMORY_TAGS
47 #define CONFIG_INITRD_TAG
49 #ifndef CONFIG_SYS_USE_BOOT_NORFLASH
50 #define CONFIG_SKIP_LOWLEVEL_INIT
57 #define CONFIG_BOARD_EARLY_INIT_F
59 #define CONFIG_WATCHDOG
61 #define CONFIG_ATMEL_USART
62 #define CONFIG_USART_BASE ATMEL_BASE_DBGU
63 #define CONFIG_USART_ID ATMEL_ID_SYS
67 #define CONFIG_ATMEL_LCD
68 #define CONFIG_SPLASH_SCREEN
69 #define CONFIG_SYS_BLACK_ON_WHITE
70 #define LCD_BPP LCD_COLOR8
71 #define CONFIG_ATMEL_LCD_BGR555
73 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
74 #define CONFIG_BOOTDELAY 3
79 #define CONFIG_BOOTP_BOOTFILESIZE
80 #define CONFIG_BOOTP_BOOTPATH
81 #define CONFIG_BOOTP_GATEWAY
82 #define CONFIG_BOOTP_HOSTNAME
85 * Command line configuration.
87 #include <config_cmd_default.h>
89 #undef CONFIG_CMD_FPGA
91 #undef CONFIG_CMD_LOADS
93 #define CONFIG_CMD_BMP
94 #define CONFIG_CMD_DATE
95 #define CONFIG_CMD_DHCP
96 #define CONFIG_CMD_I2C
97 #define CONFIG_CMD_NAND
98 #define CONFIG_CMD_MII
99 #define CONFIG_CMD_PING
100 #define CONFIG_CMD_MD5SUM
101 #define CONFIG_CMD_SHA1SUM
103 #define CONFIG_CMD_SPI
105 #define CONFIG_CMD_FAT
106 #define CONFIG_CMD_USB
108 #define CONFIG_SYS_LONGHELP
112 /*----------------------------------------------------------------------------
113 * Hardware confuguration
114 *---------------------------------------------------------------------------*/
117 #define CONFIG_USB_ATMEL
118 #define CONFIG_USB_ATMEL_CLK_SEL_PLLB
119 #define CONFIG_USB_OHCI_NEW
120 #define CONFIG_DOS_PARTITION
121 #define CONFIG_SYS_USB_OHCI_CPU_INIT
122 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* UHP_BASE */
123 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
124 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
125 #define CONFIG_USB_STORAGE
126 #define CONFIG_AT91C_PQFP_UHPBUG
130 #define CONFIG_SYS_I2C_SPEED 50000
131 #define CONFIG_SYS_I2C_SLAVE 0 /* not used */
133 #ifndef CONFIG_HARD_I2C
134 #define CONFIG_SYS_I2C
135 #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
136 #define CONFIG_SYS_I2C_SOFT_SPEED CONFIG_SYS_I2C_SPEED
137 #define CONFIG_SYS_I2C_SOFT_SLAVE CONFIG_SYS_I2C_SLAVE
139 /* Software I2C driver configuration */
140 #define I2C_DELAY udelay(2500000/CONFIG_SYS_I2C_SPEED)
142 #define AT91_PIN_SDA (1<<4) /* AT91C_PIO_PB4 */
143 #define AT91_PIN_SCL (1<<5) /* AT91C_PIO_PB5 */
145 #define I2C_INIT i2c_init_board();
146 #define I2C_ACTIVE writel(AT91_PIN_SDA, &pio->piob.mddr);
147 #define I2C_TRISTATE writel(AT91_PIN_SDA, &pio->piob.mder);
148 #define I2C_READ ((readl(&pio->piob.pdsr) & AT91_PIN_SDA) != 0)
149 #define I2C_SDA(bit) \
152 writel(AT91_PIN_SDA, &pio->piob.sodr); \
154 writel(AT91_PIN_SDA, &pio->piob.codr); \
156 #define I2C_SCL(bit) \
159 writel(AT91_PIN_SCL, &pio->piob.sodr); \
161 writel(AT91_PIN_SCL, &pio->piob.codr); \
167 #ifdef CONFIG_CMD_DATE
168 #define CONFIG_RTC_DS1338
169 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
174 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
175 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
177 /* define PDC[31:16] as DATA[31:16] */
178 #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
179 #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
181 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
182 #define CONFIG_SYS_MATRIX_EBI0CSA_VAL \
183 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
184 AT91_MATRIX_CSA_EBI_CS1A)
186 /* user reset enable */
187 #define CONFIG_SYS_RSTC_RMR_VAL \
189 AT91_RSTC_MR_URSTEN | \
190 AT91_RSTC_MR_ERSTL(15))
192 /* Disable Watchdog */
193 #define CONFIG_SYS_WDTC_WDMR_VAL \
194 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
195 AT91_WDT_MR_WDV(0xFFF) | \
196 AT91_WDT_MR_WDDIS | \
197 AT91_WDT_MR_WDD(0xFFF))
201 #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock */
206 #define MASTER_PLL_MUL 911
207 #define MASTER_PLL_DIV 56
208 #define MASTER_PLL_OUT 2
209 #elif defined(MHZ180)
211 #define MASTER_PLL_MUL 1875
212 #define MASTER_PLL_DIV 128
213 #define MASTER_PLL_OUT 2
214 #elif defined(MHZTEST)
216 #define CONFIG_DISPLAY_CPUINFO
217 #define MASTER_PLL_MUL 8
218 #define MASTER_PLL_DIV 1
219 #define MASTER_PLL_OUT 2
222 #define MASTER_PLL_MUL 72
223 #define MASTER_PLL_DIV 5
224 #define MASTER_PLL_OUT 2
227 #define CONFIG_SYS_MOR_VAL \
228 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
230 #define CONFIG_SYS_PLLAR_VAL \
231 (AT91_PMC_PLLAR_29 | \
232 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
233 AT91_PMC_PLLXR_PLLCOUNT(63) | \
234 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
235 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
237 /* PCK/2 = MCK Master Clock from PLLA */
238 #define CONFIG_SYS_MCKR1_VAL \
239 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
240 AT91_PMC_MCKR_MDIV_2)
242 /* PCK/2 = MCK Master Clock from PLLA */
243 #define CONFIG_SYS_MCKR2_VAL \
244 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
245 AT91_PMC_MCKR_MDIV_2)
248 #define CONFIG_NR_DRAM_BANKS 1
249 #define CONFIG_SYS_SDRAM_BASE 0x20000000
250 #define CONFIG_SYS_SDRAM_SIZE 0x04000000 /* 64 megs */
251 #define CONFIG_SYS_INIT_SP_ADDR 0x00504000 /* use internal SRAM0 */
253 #define CONFIG_SYS_SDRC_MR_VAL1 0
254 #define CONFIG_SYS_SDRC_TR_VAL1 700
255 #define CONFIG_SYS_SDRC_CR_VAL \
256 (AT91_SDRAMC_NC_9 | \
257 AT91_SDRAMC_NR_13 | \
259 AT91_SDRAMC_CAS_3 | \
260 AT91_SDRAMC_DBW_32 | \
261 (2 << 8) | /* Write Recovery Delay */ \
262 (7 << 12) | /* Row Cycle Delay */ \
263 (2 << 16) | /* Row Precharge Delay */ \
264 (2 << 20) | /* Row to Column Delay */ \
265 (5 << 24) | /* Active to Precharge Delay */ \
266 (8 << 28)) /* Exit Self Refresh to Active Delay */
268 #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
269 #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
270 #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
271 #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
272 #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
273 #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
274 #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
275 #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
276 #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
277 #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
278 #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
279 #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
280 #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
281 #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
282 #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
283 #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
284 #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
285 #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
289 #define CONFIG_FLASH_SHOW_PROGRESS 45
290 #define CONFIG_SYS_FLASH_CFI
291 #define CONFIG_FLASH_CFI_DRIVER
292 #define PHYS_FLASH_1 0x10000000
293 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
294 #define CONFIG_SYS_MAX_FLASH_SECT 256
295 #define CONFIG_SYS_MAX_FLASH_BANKS 1
297 #define CONFIG_ENV_IS_IN_FLASH
298 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000)
300 /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
301 #define CONFIG_SYS_SMC0_SETUP0_VAL \
302 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
303 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
304 #define CONFIG_SYS_SMC0_PULSE0_VAL \
305 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
306 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
307 #define CONFIG_SYS_SMC0_CYCLE0_VAL \
308 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
309 #define CONFIG_SYS_SMC0_MODE0_VAL \
310 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
311 AT91_SMC_MODE_DBW_16 | \
312 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
315 #ifdef CONFIG_CMD_NAND
316 #define CONFIG_NAND_ATMEL
317 #define CONFIG_SYS_MAX_NAND_DEVICE 1
318 #define CONFIG_SYS_NAND_BASE 0x40000000
319 #define CONFIG_SYS_NAND_DBW_8 1
320 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our ALE is AD21 */
321 #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* our CLE is AD22 */
322 #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
323 #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PB(0)
329 #define CONFIG_NET_MULTI
330 #define CONFIG_NET_RETRY_COUNT 5
331 #define CONFIG_AT91_WANTS_COMMON_PHY
333 #define CONFIG_OVERWRITE_ETHADDR_ONCE
335 #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */
337 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
338 #define CONFIG_SYS_MEMTEST_END 0x21e00000
340 /* Address and size of Primary Environment Sector */
341 #ifdef CONFIG_ENV_IS_IN_FLASH
342 #define CONFIG_ENV_SIZE 0x20000
344 #define CONFIG_ENV_SIZE 0x2000
347 #define CONFIG_BAUDRATE 115200
348 #define CONFIG_SYS_BAUDRATE_TABLE {312500, 230400, 115200, 19200, \
351 #define CONFIG_SYS_PROMPT "U-Boot> "
352 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
353 #define CONFIG_SYS_MAXARGS 32 /* max number of command args */
354 #define CONFIG_SYS_PBSIZE \
355 (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
356 #define CONFIG_CMDLINE_EDITING
357 #define CONFIG_AUTO_COMPLETE
360 * Size of malloc() pool
362 #define CONFIG_SYS_MALLOC_LEN \
363 ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000)
365 #ifndef CONFIG_RAMLOAD
366 #define CONFIG_BOOTCOMMAND "run nfsboot"
368 #define CONFIG_BOOT_RETRY_TIME -1
369 #define CONFIG_BOOT_RETRY_MIN 15
371 #define CONFIG_NFSBOOTCOMMAND \
372 "dhcp $(copy_addr) $(kernelname);" \
373 "run bootargsdefaults;" \
374 "set bootargs $(bootargs) boot=nfs " \
375 ";echo $(bootargs)" \
378 #define CONFIG_EXTRA_ENV_SETTINGS \
379 "ubootaddr=10000000\0" \
380 "splashimage=10080000\0" \
381 "kerneladdr=100A0000\0" \
382 "kernelsize=00800000\0" \
383 "minifsaddr=108A0000\0" \
384 "minifssize=00060000\0" \
385 "rootfsaddr=10900000\0" \
386 "copy_addr=20200000\0" \
387 "rootfssize=01700000\0" \
388 "kernelname=uImage_vl_ma2sc\0" \
389 "bootargsdefaults=set bootargs " \
390 "console=ttyS0,115200 " \
391 "video=atmel_lcdfb " \
394 "boardrevison=\\\"${revision}\\\" " \
395 "uboot=\\\"${ver}\\\" " \
397 "update_all=run update_kernel;run update_root;" \
398 "run update_splash; run update_uboot\0" \
399 "update_kernel=protect off $(kerneladdr) +$(kernelsize);" \
400 "dhcp $(copy_addr) $(kernelname);" \
401 "erase $(kerneladdr) +$(kernelsize);" \
402 "cp.b $(fileaddr) $(kerneladdr) $(filesize);" \
403 "protect on $(kerneladdr) +$(kernelsize)" \
405 "update_root=protect off $(rootfsaddr) +$(rootfssize);" \
406 "dhcp $(copy_addr) vl_ma2sc.root;" \
407 "erase $(rootfsaddr) +$(rootfssize);" \
408 "cp.b $(fileaddr) $(rootfsaddr) $(filesize);" \
410 "update_splash=protect off $(splashimage) +20000;" \
411 "dhcp $(copy_addr) splash_vl_ma2sc.bmp;" \
412 "erase $(splashimage) +20000;" \
413 "cp.b $(fileaddr) 10080000 $(filesize);" \
414 "protect on $(splashimage) +20000\0" \
415 "update_uboot=protect off 10000000 1005FFFF;" \
416 "dhcp $(copy_addr) u-boot_vl_ma2sc;" \
417 "erase 10000000 1005FFFF;" \
418 "cp.b $(fileaddr) $(ubootaddr) $(filesize);" \
419 "protect on 10000000 1005FFFF;reset\0" \
420 "emergency=run bootargsdefaults;" \
421 "set bootargs $(bootargs) root=initramfs boot=emergency " \
422 ";bootm $(kerneladdr)\0" \
423 "netemergency=run bootargsdefaults;" \
424 "dhcp $(copy_addr) $(kernelname);" \
425 "set bootargs $(bootargs) root=initramfs boot=emergency " \
426 ";bootm $(copy_addr)\0" \
427 "norboot=run bootargsdefaults;" \
428 "set bootargs $(bootargs) root=initramfs boot=local quiet " \
429 ";bootm $(kerneladdr)\0" \
430 "nandboot=run bootargsdefaults;" \
431 "set bootargs $(bootargs) root=initramfs boot=nand " \
432 ";bootm $(kerneladdr)\0" \
433 "setnorboot=set bootcmd 'run norboot'; set bootdelay 1;save\0" \
434 "clearenv=protect off 10060000 1007FFFF;" \
435 "erase 10060000 1007FFFF;reset\0" \