2 * (C) Copyright 2005 2N TELEKOMUNIKACE, Ladislav Michl
4 * Configuation settings for the TI OMAP VoiceBlue board.
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <configs/omap1510.h>
30 * High Level Configuration Options
33 #define CONFIG_ARM925T 1 /* This is an arm925t CPU */
34 #define CONFIG_OMAP 1 /* in a TI OMAP core */
35 #define CONFIG_OMAP1510 1 /* which is in a 5910 */
37 /* Input clock of PLL */
38 #define CONFIG_SYS_CLK_FREQ 150000000 /* 150MHz input clock */
39 #define CONFIG_XTAL_FREQ 12000000
41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
43 #define CONFIG_MISC_INIT_R /* There is nothing to really init */
44 #define BOARD_LATE_INIT /* but we flash the LEDs here */
46 #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
47 #define CONFIG_SETUP_MEMORY_TAGS 1
48 #define CONFIG_INITRD_TAG 1
53 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
54 #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */
55 #define PHYS_SDRAM_1_SIZE SZ_64M
57 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
58 #define PHYS_FLASH_2 0x0c000000
60 #define CFG_LOAD_ADDR PHYS_SDRAM_1 + 0x400000 /* default load address */
65 #define CFG_FLASH_CFI /* Flash is CFI conformant */
66 #define CFG_FLASH_CFI_DRIVER /* Use the common driver */
67 #define CFG_MAX_FLASH_BANKS 1
68 #ifdef VOICEBLUE_SMALL_FLASH
69 #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_2 }
71 #define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 }
74 /* FIXME: Does not work on AMD flash */
75 /* #define CFG_FLASH_USE_BUFFER_WRITE 1 */ /* use buffered writes (20x faster) */
76 #define CFG_MAX_FLASH_SECT 512 /* max # of sectors on one chip */
78 #define CFG_MONITOR_BASE PHYS_FLASH_1
79 #define CFG_MONITOR_LEN SZ_128K
82 * Environment settings
84 #ifdef VOICEBLUE_SMALL_FLASH
85 #define CFG_ENV_IS_NOWHERE
86 #define CFG_ENV_SIZE SZ_1K
88 #define CFG_ENV_IS_IN_FLASH
89 #define CFG_ENV_ADDR (PHYS_FLASH_1 + CFG_MONITOR_LEN)
90 #define CFG_ENV_SIZE SZ_8K
91 #define CFG_ENV_SECT_SIZE SZ_64K
92 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
93 #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
95 #define CONFIG_ENV_OVERWRITE
97 #define CFG_JFFS_CUSTOM_PART /* see board/voiceblue/jffs2parts.c */
101 * Size of malloc() pool
103 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
104 #ifdef VOICEBLUE_SMALL_FLASH
105 #define CFG_MALLOC_LEN (SZ_64K - CFG_GBL_DATA_SIZE)
107 #define CFG_MALLOC_LEN (SZ_4M - CFG_GBL_DATA_SIZE)
111 * The stack size is set up in start.S using the settings below
113 #define CONFIG_STACKSIZE SZ_8K /* regular stack */
118 #define CONFIG_DRIVER_SMC91111
119 #define CONFIG_SMC91111_BASE 0x08000300
122 * NS16550 Configuration
125 #define CFG_NS16550_SERIAL
126 #define CFG_NS16550_REG_SIZE (-4)
127 #define CFG_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */
128 #define CFG_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */
130 #define CONFIG_CONS_INDEX 1
131 #define CONFIG_BAUDRATE 115200
132 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
134 #ifdef VOICEBLUE_SMALL_FLASH
135 #define CONFIG_COMMANDS (CFG_CMD_BDI | \
146 #define CONFIG_COMMANDS (CFG_CMD_BDI | \
160 #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT
163 #ifdef VOICEBLUE_SMALL_FLASH
164 #define CONFIG_BOOTDELAY 0
165 #undef CONFIG_BOOTARGS /* the preboot command will set bootargs*/
166 #define CFG_AUTOLOAD "n" /* No autoload */
167 #define CONFIG_PREBOOT "run setup"
168 #define CONFIG_EXTRA_ENV_SETTINGS \
169 "setup=setenv bootargs console=ttyS0,$(baudrate) " \
170 "root=/dev/nfs ip=dhcp\0" \
171 "update=erase c000000 c03ffff; " \
172 "cp.b 10400000 c000000 $(filesize)\0"
174 #define CONFIG_BOOTDELAY 3
175 #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
176 #define CFG_AUTOLOAD "n" /* No autoload */
177 #define CONFIG_BOOTCOMMAND "run nboot"
178 #define CONFIG_PREBOOT "run setup"
179 #define CONFIG_EXTRA_ENV_SETTINGS \
183 "if test $swapos = yes; then " \
184 "if test $ospart -eq 0; then chpart 4; else chpart 3; fi; "\
185 "setenv swapos no; saveenv; " \
187 "if test $ospart -eq 0; then chpart 3; else chpart 4; fi; "\
189 "setup=setenv bootargs console=ttyS0,$baudrate " \
190 "mtdparts=$mtdparts\0" \
191 "nfsargs=setenv bootargs $bootargs " \
192 "root=/dev/nfs ip=dhcp; run setpart\0" \
193 "flashargs=setenv bootargs $bootargs " \
194 "root=/dev/mtdblock$partition " \
195 "rootfstype=jffs2; run setpart\0" \
196 "nboot=run nfsargs; bootp; tftp; bootm\0" \
197 "fboot=run flashargs; fsload /boot/uImage; bootm\0"
200 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
201 #include <cmd_confdefs.h>
204 * Miscellaneous configurable options
206 #ifndef VOICEBLUE_SMALL_FLASH
207 #define CFG_HUSH_PARSER
208 #define CFG_PROMPT_HUSH_PS2 "> "
209 #define CONFIG_AUTO_COMPLETE
211 #define CFG_LONGHELP /* undef to save memory */
212 #define CFG_PROMPT "# " /* Monitor Command Prompt */
213 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
214 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
215 #define CFG_MAXARGS 16 /* max number of command args */
216 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
218 #define CFG_MEMTEST_START PHYS_SDRAM_1
219 #define CFG_MEMTEST_END PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE
221 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
223 /* The 1510 has 3 timers, they can be driven by the RefClk (12Mhz) or by DPLL1.
224 * This time is further subdivided by a local divisor.
226 #define CFG_TIMERBASE OMAP1510_TIMER1_BASE
227 #define CFG_PVT 7 /* 2^(pvt+1), divide by 256 */
228 #define CFG_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CFG_PVT))
230 #define OMAP5910_DPLL_DIV 1
231 #define OMAP5910_DPLL_MUL ((CONFIG_SYS_CLK_FREQ * \
232 (1 << OMAP5910_DPLL_DIV)) / CONFIG_XTAL_FREQ)
234 #define OMAP5910_ARM_PER_DIV 2 /* CKL/4 */
235 #define OMAP5910_LCD_DIV 2 /* CKL/4 */
236 #define OMAP5910_ARM_DIV 0 /* CKL/1 */
237 #define OMAP5910_DSP_DIV 0 /* CKL/1 */
238 #define OMAP5910_TC_DIV 1 /* CKL/2 */
239 #define OMAP5910_DSP_MMU_DIV 1 /* CKL/2 */
240 #define OMAP5910_ARM_TIM_SEL 1 /* CKL used for MPU timers */
242 #define OMAP5910_ARM_EN_CLK 0x03d6 /* 0000 0011 1101 0110b Clock Enable */
243 #define OMAP5910_ARM_CKCTL ((OMAP5910_ARM_PER_DIV) | \
244 (OMAP5910_LCD_DIV << 2) | \
245 (OMAP5910_ARM_DIV << 4) | \
246 (OMAP5910_DSP_DIV << 6) | \
247 (OMAP5910_TC_DIV << 8) | \
248 (OMAP5910_DSP_MMU_DIV << 10) | \
249 (OMAP5910_ARM_TIM_SEL << 12))
251 #define VOICEBLUE_LED_REG 0x04030000
253 #endif /* __CONFIG_H */