2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2004-2008 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
9 * xpedite520x board configuration file
15 * High Level Configuration Options
17 #define CONFIG_BOOKE 1 /* BOOKE */
18 #define CONFIG_E500 1 /* BOOKE e500 family */
19 #define CONFIG_MPC8548 1
20 #define CONFIG_XPEDITE5200 1
21 #define CONFIG_SYS_BOARD_NAME "XPedite5200"
22 #define CONFIG_SYS_FORM_PMC_XMC 1
23 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
24 #define CONFIG_DISPLAY_BOARDINFO
26 #ifndef CONFIG_SYS_TEXT_BASE
27 #define CONFIG_SYS_TEXT_BASE 0xfff80000
30 #define CONFIG_PCI 1 /* Enable PCI/PCIE */
31 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
32 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
33 #define CONFIG_PCI1 1 /* PCI controller 1 */
34 #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
35 #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
36 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
37 #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
42 #define CONFIG_SYS_FSL_DDR2
43 #undef CONFIG_FSL_DDR_INTERACTIVE
44 #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
45 #define CONFIG_DDR_SPD
46 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47 #define SPD_EEPROM_ADDRESS 0x54
48 #define CONFIG_NUM_DDR_CONTROLLERS 1
49 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
50 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
51 #define CONFIG_DDR_ECC
52 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
53 #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
54 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
55 #define CONFIG_VERY_BIG_RAM
57 #define CONFIG_SYS_CLK_FREQ 66666666
60 * These can be toggled for performance analysis, otherwise use default.
62 #define CONFIG_L2_CACHE /* toggle L2 cache */
63 #define CONFIG_BTB /* toggle branch predition */
64 #define CONFIG_ENABLE_36BIT_PHYS 1
66 #define CONFIG_SYS_CCSRBAR 0xef000000
67 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
72 #define CONFIG_SYS_ALT_MEMTEST
73 #define CONFIG_SYS_MEMTEST_START 0x10000000
74 #define CONFIG_SYS_MEMTEST_END 0x20000000
75 #define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
77 #define I2C_ADDR_LIST {CONFIG_SYS_I2C_MAX1237_ADDR, \
78 CONFIG_SYS_I2C_EEPROM_ADDR, \
79 CONFIG_SYS_I2C_PCA953X_ADDR0, \
80 CONFIG_SYS_I2C_PCA953X_ADDR1, \
81 CONFIG_SYS_I2C_RTC_ADDR}
85 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
86 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
87 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
88 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
89 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
90 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
91 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
92 * 0xfc00_0000 0xffff_ffff NOR Flash 1 64M non-cacheable
95 #define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
98 * NAND flash configuration
100 #define CONFIG_SYS_NAND_BASE 0xef800000
101 #define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
102 #define CONFIG_SYS_MAX_NAND_DEVICE 1
103 #define CONFIG_NAND_ACTL
104 #define CONFIG_SYS_NAND_ACTL_CLE (1 << 3) /* ADDR3 is CLE */
105 #define CONFIG_SYS_NAND_ACTL_ALE (1 << 4) /* ADDR4 is ALE */
106 #define CONFIG_SYS_NAND_ACTL_NCE (0) /* NCE not controlled by ADDR */
107 #define CONFIG_SYS_NAND_ACTL_DELAY 25
110 * NOR flash configuration
112 #define CONFIG_SYS_FLASH_BASE 0xfc000000
113 #define CONFIG_SYS_FLASH_BASE2 0xf8000000
114 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
115 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
116 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
117 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
118 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
119 #define CONFIG_FLASH_CFI_DRIVER
120 #define CONFIG_SYS_FLASH_CFI
121 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
122 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
123 {0xfbf40000, 0xc0000} }
124 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
127 * Chip select configuration
129 /* NOR Flash 0 on CS0 */
130 #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
133 #define CONFIG_SYS_OR0_PRELIM (OR_AM_64MB | \
137 /* NOR Flash 1 on CS1 */
138 #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
141 #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
143 /* NAND flash on CS2 */
144 #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
148 /* NAND flash on CS2 */
149 #define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
157 /* NAND flash on CS3 */
158 #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
161 #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
164 * Use L1 as initial stack
166 #define CONFIG_SYS_INIT_RAM_LOCK 1
167 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
168 #define CONFIG_SYS_INIT_RAM_SIZE 0x4000
170 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
171 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
173 #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
174 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
179 #define CONFIG_CONS_INDEX 1
180 #define CONFIG_SYS_NS16550_SERIAL
181 #define CONFIG_SYS_NS16550_REG_SIZE 1
182 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
183 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
184 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
185 #define CONFIG_SYS_BAUDRATE_TABLE \
186 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
187 #define CONFIG_BAUDRATE 115200
188 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
189 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
194 #define CONFIG_SYS_I2C
195 #define CONFIG_SYS_I2C_FSL
196 #define CONFIG_SYS_FSL_I2C_SPEED 400000
197 #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
198 #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
199 #define CONFIG_SYS_FSL_I2C2_SPEED 400000
200 #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
201 #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
204 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
205 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
206 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
207 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
210 #define CONFIG_RTC_M41T11 1
211 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
212 #define CONFIG_SYS_M41T11_BASE_YEAR 2000
215 #define CONFIG_PCA953X
216 #define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
217 #define CONFIG_SYS_I2C_PCA953X_ADDR1 0x19
218 #define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
221 #define CONFIG_SYS_PCA953X_BRD_CFG0 0x01
222 #define CONFIG_SYS_PCA953X_BRD_CFG1 0x02
223 #define CONFIG_SYS_PCA953X_BRD_CFG2 0x04
224 #define CONFIG_SYS_PCA953X_XMC_ROOT0 0x08
225 #define CONFIG_SYS_PCA953X_FLASH_PASS_CS 0x10
226 #define CONFIG_SYS_PCA953X_NVM_WP 0x20
227 #define CONFIG_SYS_PCA953X_MONARCH 0x40
228 #define CONFIG_SYS_PCA953X_EREADY 0x80
231 #define CONFIG_SYS_PCA953X_P14_IO0 0x01
232 #define CONFIG_SYS_PCA953X_P14_IO1 0x02
233 #define CONFIG_SYS_PCA953X_P14_IO2 0x04
234 #define CONFIG_SYS_PCA953X_P14_IO3 0x08
235 #define CONFIG_SYS_PCA953X_P14_IO4 0x10
236 #define CONFIG_SYS_PCA953X_P14_IO5 0x20
237 #define CONFIG_SYS_PCA953X_P14_IO6 0x40
238 #define CONFIG_SYS_PCA953X_P14_IO7 0x80
240 /* 12-bit ADC used to measure CPU diode */
241 #define CONFIG_SYS_I2C_MAX1237_ADDR 0x34
245 * Memory space is mapped 1-1, but I/O space must start from 0.
247 #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
248 #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
249 #define CONFIG_SYS_PCI1_MEM_SIZE 0x40000000 /* 1G */
250 #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
251 #define CONFIG_SYS_PCI1_IO_PHYS 0xe8000000
252 #define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 1M */
257 #define CONFIG_TSEC_ENET /* tsec ethernet support */
258 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
259 #define CONFIG_MII 1 /* MII PHY management */
260 #define CONFIG_ETHPRIME "eTSEC1"
262 #define CONFIG_TSEC1 1
263 #define CONFIG_TSEC1_NAME "eTSEC1"
264 #define TSEC1_FLAGS TSEC_GIGABIT
265 #define TSEC1_PHY_ADDR 1
266 #define TSEC1_PHYIDX 0
267 #define CONFIG_HAS_ETH0
269 #define CONFIG_TSEC2 1
270 #define CONFIG_TSEC2_NAME "eTSEC2"
271 #define TSEC2_FLAGS TSEC_GIGABIT
272 #define TSEC2_PHY_ADDR 2
273 #define TSEC2_PHYIDX 0
274 #define CONFIG_HAS_ETH1
276 #define CONFIG_TSEC3 1
277 #define CONFIG_TSEC3_NAME "eTSEC3"
278 #define TSEC3_FLAGS TSEC_GIGABIT
279 #define TSEC3_PHY_ADDR 3
280 #define TSEC3_PHYIDX 0
281 #define CONFIG_HAS_ETH2
283 #define CONFIG_TSEC4 1
284 #define CONFIG_TSEC4_NAME "eTSEC4"
285 #define TSEC4_FLAGS TSEC_GIGABIT
286 #define TSEC4_PHY_ADDR 4
287 #define TSEC4_PHYIDX 0
288 #define CONFIG_HAS_ETH3
293 #define CONFIG_BOOTP_BOOTFILESIZE
294 #define CONFIG_BOOTP_BOOTPATH
295 #define CONFIG_BOOTP_GATEWAY
298 * Command configuration.
300 #define CONFIG_CMD_DATE
301 #define CONFIG_CMD_EEPROM
302 #define CONFIG_CMD_JFFS2
303 #define CONFIG_CMD_NAND
304 #define CONFIG_CMD_PCA953X
305 #define CONFIG_CMD_PCA953X_INFO
306 #define CONFIG_CMD_PCI
307 #define CONFIG_CMD_PCI_ENUM
308 #define CONFIG_CMD_REGINFO
311 * Miscellaneous configurable options
313 #define CONFIG_SYS_LONGHELP /* undef to save memory */
314 #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
315 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
316 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
317 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
318 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
319 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
320 #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
321 #define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
322 #define CONFIG_PANIC_HANG /* do not reset board on panic */
323 #define CONFIG_PREBOOT /* enable preboot variable */
324 #define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
325 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
328 * For booting Linux, the board info and command line data
329 * have to be in the first 16 MB of memory, since this is
330 * the maximum mapped by the Linux kernel during initialization.
332 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
333 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
336 * Environment Configuration
338 #define CONFIG_ENV_IS_IN_FLASH 1
339 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
340 #define CONFIG_ENV_SIZE 0x8000
341 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
345 * fff80000 - ffffffff Pri U-Boot (512 KB)
346 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
347 * fff00000 - fff3ffff Pri FDT (256KB)
348 * fef00000 - ffefffff Pri OS image (16MB)
349 * fc000000 - feefffff Pri OS Use/Filesystem (47MB)
351 * fbf80000 - fbffffff Sec U-Boot (512 KB)
352 * fbf40000 - fbf7ffff Sec U-Boot Environment (256 KB)
353 * fbf00000 - fbf3ffff Sec FDT (256KB)
354 * faf00000 - fbefffff Sec OS image (16MB)
355 * f8000000 - faefffff Sec OS Use/Filesystem (47MB)
357 #define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
358 #define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
359 #define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
360 #define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
361 #define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
362 #define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
364 #define CONFIG_PROG_UBOOT1 \
365 "$download_cmd $loadaddr $ubootfile; " \
366 "if test $? -eq 0; then " \
367 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
368 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
369 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
370 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
371 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
372 "if test $? -ne 0; then " \
373 "echo PROGRAM FAILED; " \
375 "echo PROGRAM SUCCEEDED; " \
378 "echo DOWNLOAD FAILED; " \
381 #define CONFIG_PROG_UBOOT2 \
382 "$download_cmd $loadaddr $ubootfile; " \
383 "if test $? -eq 0; then " \
384 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
385 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
386 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
387 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
388 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
389 "if test $? -ne 0; then " \
390 "echo PROGRAM FAILED; " \
392 "echo PROGRAM SUCCEEDED; " \
395 "echo DOWNLOAD FAILED; " \
398 #define CONFIG_BOOT_OS_NET \
399 "$download_cmd $osaddr $osfile; " \
400 "if test $? -eq 0; then " \
401 "if test -n $fdtaddr; then " \
402 "$download_cmd $fdtaddr $fdtfile; " \
403 "if test $? -eq 0; then " \
404 "bootm $osaddr - $fdtaddr; " \
406 "echo FDT DOWNLOAD FAILED; " \
412 "echo OS DOWNLOAD FAILED; " \
415 #define CONFIG_PROG_OS1 \
416 "$download_cmd $osaddr $osfile; " \
417 "if test $? -eq 0; then " \
418 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
419 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
420 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
421 "if test $? -ne 0; then " \
422 "echo OS PROGRAM FAILED; " \
424 "echo OS PROGRAM SUCCEEDED; " \
427 "echo OS DOWNLOAD FAILED; " \
430 #define CONFIG_PROG_OS2 \
431 "$download_cmd $osaddr $osfile; " \
432 "if test $? -eq 0; then " \
433 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
434 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
435 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
436 "if test $? -ne 0; then " \
437 "echo OS PROGRAM FAILED; " \
439 "echo OS PROGRAM SUCCEEDED; " \
442 "echo OS DOWNLOAD FAILED; " \
445 #define CONFIG_PROG_FDT1 \
446 "$download_cmd $fdtaddr $fdtfile; " \
447 "if test $? -eq 0; then " \
448 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
449 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
450 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
451 "if test $? -ne 0; then " \
452 "echo FDT PROGRAM FAILED; " \
454 "echo FDT PROGRAM SUCCEEDED; " \
457 "echo FDT DOWNLOAD FAILED; " \
460 #define CONFIG_PROG_FDT2 \
461 "$download_cmd $fdtaddr $fdtfile; " \
462 "if test $? -eq 0; then " \
463 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
464 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
465 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
466 "if test $? -ne 0; then " \
467 "echo FDT PROGRAM FAILED; " \
469 "echo FDT PROGRAM SUCCEEDED; " \
472 "echo FDT DOWNLOAD FAILED; " \
475 #define CONFIG_EXTRA_ENV_SETTINGS \
477 "download_cmd=tftp\0" \
478 "console_args=console=ttyS0,115200\0" \
479 "root_args=root=/dev/nfs rw\0" \
480 "misc_args=ip=on\0" \
481 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
482 "bootfile=/home/user/file\0" \
483 "osfile=/home/user/board.uImage\0" \
484 "fdtfile=/home/user/board.dtb\0" \
485 "ubootfile=/home/user/u-boot.bin\0" \
487 "osaddr=0x1000000\0" \
488 "loadaddr=0x1000000\0" \
489 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
490 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
491 "prog_os1="CONFIG_PROG_OS1"\0" \
492 "prog_os2="CONFIG_PROG_OS2"\0" \
493 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
494 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
495 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
496 "bootcmd_flash1=run set_bootargs; " \
497 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
498 "bootcmd_flash2=run set_bootargs; " \
499 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
500 "bootcmd=run bootcmd_flash1\0"
501 #endif /* __CONFIG_H */