2 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 /************************************************************************
24 * 1 january 2005 Alain Saurel <asaurel@amcc.com>
25 * Adapted to current Das U-Boot source
26 ***********************************************************************/
27 /************************************************************************
28 * yucca.h - configuration for AMCC 440SPe Ref (yucca)
29 ***********************************************************************/
34 /*-----------------------------------------------------------------------
35 * High Level Configuration Options
36 *----------------------------------------------------------------------*/
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_440 1 /* ... PPC440 family */
39 #define CONFIG_440SPE 1 /* Specifc SPe support */
40 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
41 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
42 #define EXTCLK_33_33 33333333
43 #define EXTCLK_66_66 66666666
44 #define EXTCLK_50 50000000
45 #define EXTCLK_83 83333333
47 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
48 #undef CONFIG_SHOW_BOOT_PROGRESS
51 /*-----------------------------------------------------------------------
52 * Base addresses -- Note these are effective addresses where the
53 * actual resources get mapped (not physical addresses)
54 *----------------------------------------------------------------------*/
55 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
56 #define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */
57 #define CFG_MONITOR_BASE 0xfffb0000 /* start of monitor */
58 #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
59 #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
61 #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
62 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
63 #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
65 #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
66 #define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
67 #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
69 #define CFG_PCIE0_CFGBASE 0xc0000000
70 #define CFG_PCIE1_CFGBASE 0xc1000000
71 #define CFG_PCIE2_CFGBASE 0xc2000000
72 #define CFG_PCIE0_XCFGBASE 0xc3000000
73 #define CFG_PCIE1_XCFGBASE 0xc3001000
74 #define CFG_PCIE2_XCFGBASE 0xc3002000
76 /* base address of inbound PCIe window */
77 #define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL
79 /* System RAM mapped to PCI space */
80 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
81 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
82 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
84 #define CFG_FPGA_BASE 0xe2000000 /* epld */
85 #define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */
87 /* #define CFG_NVRAM_BASE_ADDR 0x08000000 */
88 /*-----------------------------------------------------------------------
89 * Initial RAM & stack pointer (placed in internal SRAM)
90 *----------------------------------------------------------------------*/
91 #define CFG_TEMP_STACK_OCM 1
92 #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
93 #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
94 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
95 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
97 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
98 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
99 #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
101 #define CFG_MONITOR_LEN (320 * 1024) /* Reserve 320 kB for Mon */
102 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
104 /*-----------------------------------------------------------------------
106 *----------------------------------------------------------------------*/
107 #define CONFIG_SERIAL_MULTI 1
108 #undef CONFIG_UART1_CONSOLE
110 #undef CONFIG_SERIAL_SOFTWARE_FIFO
111 #undef CFG_EXT_SERIAL_CLOCK
112 /* #define CFG_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */
114 #define CONFIG_BAUDRATE 115200
116 #define CFG_BAUDRATE_TABLE \
117 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
119 /*-----------------------------------------------------------------------
121 *----------------------------------------------------------------------*/
122 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
123 #define SPD_EEPROM_ADDRESS {0x53, 0x52} /* SPD i2c spd addresses*/
124 #define CONFIG_DDR_ECC 1 /* with ECC support */
126 /*-----------------------------------------------------------------------
128 *----------------------------------------------------------------------*/
129 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
130 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
131 #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
132 #define CFG_I2C_SLAVE 0x7F
134 #define IIC0_BOOTPROM_ADDR 0x50
135 #define IIC0_ALT_BOOTPROM_ADDR 0x54
137 /* Don't probe these addrs */
138 #define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54}
140 /* #if defined(CONFIG_CMD_EEPROM) */
141 /* #define CFG_I2C_EEPROM_ADDR 0x50 */ /* I2C boot EEPROM */
142 #define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
145 /*-----------------------------------------------------------------------
147 *----------------------------------------------------------------------*/
148 /* #define CFG_NVRAM_SIZE (0x2000 - 8) */ /* NVRAM size(8k)- RTC regs */
150 #undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */
151 #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
152 #undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */
153 #define CONFIG_ENV_OVERWRITE 1
155 #define CONFIG_PREBOOT "echo;" \
156 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
159 #undef CONFIG_BOOTARGS
161 #define CONFIG_EXTRA_ENV_SETTINGS \
164 "nfsargs=setenv bootargs root=/dev/nfs rw " \
165 "nfsroot=${serverip}:${rootpath}\0" \
166 "ramargs=setenv bootargs root=/dev/ram rw\0" \
167 "addip=setenv bootargs ${bootargs} " \
168 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
169 ":${hostname}:${netdev}:off panic=1\0" \
170 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
171 "flash_nfs=run nfsargs addip addtty;" \
172 "bootm ${kernel_addr}\0" \
173 "flash_self=run ramargs addip addtty;" \
174 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
175 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
177 "rootpath=/opt/eldk/ppc_4xx\0" \
178 "bootfile=yucca/uImage\0" \
179 "kernel_addr=E7F10000\0" \
180 "ramdisk_addr=E7F20000\0" \
181 "initrd_high=30000000\0" \
182 "load=tftp 100000 yuca/u-boot.bin\0" \
183 "update=protect off 2:4-7;era 2:4-7;" \
184 "cp.b ${fileaddr} FFFB0000 ${filesize};" \
185 "setenv filesize;saveenv\0" \
186 "upd=run load update\0" \
187 "pciconfighost=1\0" \
188 "pcie_mode=RP:EP:EP\0" \
190 #define CONFIG_BOOTCOMMAND "run flash_self"
192 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
194 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
195 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
201 #define CONFIG_BOOTP_BOOTFILESIZE
202 #define CONFIG_BOOTP_BOOTPATH
203 #define CONFIG_BOOTP_GATEWAY
204 #define CONFIG_BOOTP_HOSTNAME
208 * Command line configuration.
210 #include <config_cmd_default.h>
212 #define CONFIG_CMD_ASKENV
213 #define CONFIG_CMD_EEPROM
214 #define CONFIG_CMD_DHCP
215 #define CONFIG_CMD_DIAG
216 #define CONFIG_CMD_ELF
217 #define CONFIG_CMD_I2C
218 #define CONFIG_CMD_IRQ
219 #define CONFIG_CMD_MII
220 #define CONFIG_CMD_NET
221 #define CONFIG_CMD_NFS
222 #define CONFIG_CMD_PCI
223 #define CONFIG_CMD_PING
224 #define CONFIG_CMD_REGINFO
225 #define CONFIG_CMD_SDRAM
228 #define CONFIG_IBM_EMAC4_V4 1
229 #define CONFIG_MII 1 /* MII PHY management */
230 #undef CONFIG_NET_MULTI
231 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
232 #define CONFIG_HAS_ETH0
233 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
234 #define CONFIG_PHY_RESET_DELAY 1000
235 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
236 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
237 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
239 #define CONFIG_NETCONSOLE /* include NetConsole support */
240 #define CONFIG_NET_MULTI /* needed for NetConsole */
242 #undef CONFIG_WATCHDOG /* watchdog disabled */
245 * Miscellaneous configurable options
247 #define CFG_LONGHELP /* undef to save memory */
248 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
250 #if defined(CONFIG_CMD_KGDB)
251 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
253 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
255 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
256 #define CFG_MAXARGS 16 /* max number of command args */
257 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
259 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
260 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
262 #define CFG_LOAD_ADDR 0x100000 /* default load address */
263 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
265 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
267 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
268 #define CONFIG_LOOPW 1 /* enable loopw command */
269 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
270 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
271 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
273 /*-----------------------------------------------------------------------
275 *----------------------------------------------------------------------*/
276 #define CFG_MAX_FLASH_BANKS 3 /* number of banks */
277 #define CFG_MAX_FLASH_SECT 256 /* sectors per device */
279 #undef CFG_FLASH_CHECKSUM
280 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
281 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
283 #define CFG_FLASH_ADDR0 0x5555
284 #define CFG_FLASH_ADDR1 0x2aaa
285 #define CFG_FLASH_WORD_SIZE unsigned char
287 #define CFG_FLASH_2ND_16BIT_DEV 1 /* evb440SPe has 8 and 16bit device */
288 #define CFG_FLASH_2ND_ADDR 0xe7c00000 /* evb440SPe has 8 and 16bit device*/
290 #ifdef CFG_ENV_IS_IN_FLASH
291 #define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
292 #define CFG_ENV_ADDR 0xfffa0000
293 /* #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) */
294 #define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */
295 #endif /* CFG_ENV_IS_IN_FLASH */
296 /*-----------------------------------------------------------------------
298 *-----------------------------------------------------------------------
301 #define CONFIG_PCI /* include pci support */
302 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
303 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
304 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
306 /* Board-specific PCI */
307 #define CFG_PCI_TARGET_INIT /* let board init pci target */
308 #undef CFG_PCI_MASTER_INIT
310 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
311 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
312 /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
315 * NETWORK Support (PCI):
317 /* Support for Intel 82557/82559/82559ER chips. */
318 #define CONFIG_EEPRO100
321 * For booting Linux, the board info and command line data
322 * have to be in the first 8 MB of memory, since this is
323 * the maximum mapped by the Linux kernel during initialization.
325 #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
328 * Internal Definitions
332 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
333 #define BOOTFLAG_WARM 0x02 /* Software reboot */
335 #if defined(CONFIG_CMD_KGDB)
336 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
337 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
340 /* FB Divisor selection */
341 #define FPGA_FB_DIV_6 6
342 #define FPGA_FB_DIV_10 10
343 #define FPGA_FB_DIV_12 12
344 #define FPGA_FB_DIV_20 20
346 /* VCO Divisor selection */
347 #define FPGA_VCO_DIV_4 4
348 #define FPGA_VCO_DIV_6 6
349 #define FPGA_VCO_DIV_8 8
350 #define FPGA_VCO_DIV_10 10
352 /*----------------------------------------------------------------------------+
353 | FPGA registers and bit definitions
354 +----------------------------------------------------------------------------*/
355 /* PowerPC 440SPe Board FPGA is reached with physical address 0x1 E2000000. */
356 /* TLB initialization makes it correspond to logical address 0xE2000000. */
357 /* => Done init_chip.s in bootlib */
358 #define FPGA_REG_BASE_ADDR 0xE2000000
359 #define FPGA_GPIO_BASE_ADDR 0xE2010000
360 #define FPGA_INT_BASE_ADDR 0xE2020000
362 /*----------------------------------------------------------------------------+
364 +----------------------------------------------------------------------------*/
365 #define PPC440SPE_DISPLAY FPGA_REG_BASE_ADDR
367 #define PPC440SPE_DISPLAY_D8 (FPGA_REG_BASE_ADDR+0x06)
368 #define PPC440SPE_DISPLAY_D4 (FPGA_REG_BASE_ADDR+0x04)
369 #define PPC440SPE_DISPLAY_D2 (FPGA_REG_BASE_ADDR+0x02)
370 #define PPC440SPE_DISPLAY_D1 (FPGA_REG_BASE_ADDR+0x00)
371 /*define WRITE_DISPLAY_DIGIT(n) IOREG8(FPGA_REG_BASE_ADDR + (2*n))*/
372 /*#define IOREG8(addr) *((volatile unsigned char *)(addr))*/
374 /*----------------------------------------------------------------------------+
375 | ethernet/reset/boot Register 1
376 +----------------------------------------------------------------------------*/
377 #define FPGA_REG10 (FPGA_REG_BASE_ADDR+0x10)
379 #define FPGA_REG10_10MHZ_ENABLE 0x8000
380 #define FPGA_REG10_100MHZ_ENABLE 0x4000
381 #define FPGA_REG10_GIGABIT_ENABLE 0x2000
382 #define FPGA_REG10_FULL_DUPLEX 0x1000 /* force Full Duplex*/
383 #define FPGA_REG10_RESET_ETH 0x0800
384 #define FPGA_REG10_AUTO_NEG_DIS 0x0400
385 #define FPGA_REG10_INTP_ETH 0x0200
387 #define FPGA_REG10_RESET_HISR 0x0080
388 #define FPGA_REG10_ENABLE_DISPLAY 0x0040
389 #define FPGA_REG10_RESET_SDRAM 0x0020
390 #define FPGA_REG10_OPER_BOOT 0x0010
391 #define FPGA_REG10_SRAM_BOOT 0x0008
392 #define FPGA_REG10_SMALL_BOOT 0x0004
393 #define FPGA_REG10_FORCE_COLA 0x0002
394 #define FPGA_REG10_COLA_MANUAL 0x0001
396 #define FPGA_REG10_SDRAM_ENABLE 0x0020
398 #define FPGA_REG10_ENET_ENCODE2(n) ((((unsigned long)(n))&0x0F)<<4) /*from ocotea ?*/
399 #define FPGA_REG10_ENET_DECODE2(n) ((((unsigned long)(n))>>4)&0x0F) /*from ocotea ?*/
401 /*----------------------------------------------------------------------------+
403 +----------------------------------------------------------------------------*/
404 #define FPGA_REG12 (FPGA_REG_BASE_ADDR+0x12)
406 #define FPGA_REG12_EBC_CTL 0x8000
407 #define FPGA_REG12_UART1_CTS_RTS 0x4000
408 #define FPGA_REG12_UART0_RX_ENABLE 0x2000
409 #define FPGA_REG12_UART1_RX_ENABLE 0x1000
410 #define FPGA_REG12_UART2_RX_ENABLE 0x0800
411 #define FPGA_REG12_EBC_OUT_ENABLE 0x0400
412 #define FPGA_REG12_GPIO0_OUT_ENABLE 0x0200
413 #define FPGA_REG12_GPIO1_OUT_ENABLE 0x0100
414 #define FPGA_REG12_GPIO_SELECT 0x0010
415 #define FPGA_REG12_GPIO_CHREG 0x0008
416 #define FPGA_REG12_GPIO_CLK_CHREG 0x0004
417 #define FPGA_REG12_GPIO_OETRI 0x0002
418 #define FPGA_REG12_EBC_ERROR 0x0001
420 /*----------------------------------------------------------------------------+
422 +----------------------------------------------------------------------------*/
423 #define FPGA_REG16 (FPGA_REG_BASE_ADDR+0x16)
425 #define FPGA_REG16_PCI_CLK_CTL0 0x8000
426 #define FPGA_REG16_PCI_CLK_CTL1 0x4000
427 #define FPGA_REG16_PCI_CLK_CTL2 0x2000
428 #define FPGA_REG16_PCI_CLK_CTL3 0x1000
429 #define FPGA_REG16_PCI_CLK_CTL4 0x0800
430 #define FPGA_REG16_PCI_CLK_CTL5 0x0400
431 #define FPGA_REG16_PCI_CLK_CTL6 0x0200
432 #define FPGA_REG16_PCI_CLK_CTL7 0x0100
433 #define FPGA_REG16_PCI_CLK_CTL8 0x0080
434 #define FPGA_REG16_PCI_CLK_CTL9 0x0040
435 #define FPGA_REG16_PCI_EXT_ARB0 0x0020
436 #define FPGA_REG16_PCI_MODE_1 0x0010
437 #define FPGA_REG16_PCI_TARGET_MODE 0x0008
438 #define FPGA_REG16_PCI_INTP_MODE 0x0004
440 /* FB1 Divisor selection */
441 #define FPGA_REG16_FB2_DIV_MASK 0x1000
442 #define FPGA_REG16_FB2_DIV_LOW 0x0000
443 #define FPGA_REG16_FB2_DIV_HIGH 0x1000
444 /* FB2 Divisor selection */
445 /* S3 switch on Board */
446 #define FPGA_REG16_FB1_DIV_MASK 0x2000
447 #define FPGA_REG16_FB1_DIV_LOW 0x0000
448 #define FPGA_REG16_FB1_DIV_HIGH 0x2000
449 /* PCI0 Clock Selection */
450 /* S3 switch on Board */
451 #define FPGA_REG16_PCI0_CLK_MASK 0x0c00
452 #define FPGA_REG16_PCI0_CLK_33_33 0x0000
453 #define FPGA_REG16_PCI0_CLK_66_66 0x0800
454 #define FPGA_REG16_PCI0_CLK_100 0x0400
455 #define FPGA_REG16_PCI0_CLK_133_33 0x0c00
456 /* VCO Divisor selection */
457 /* S3 switch on Board */
458 #define FPGA_REG16_VCO_DIV_MASK 0xc000
459 #define FPGA_REG16_VCO_DIV_4 0x0000
460 #define FPGA_REG16_VCO_DIV_8 0x4000
461 #define FPGA_REG16_VCO_DIV_6 0x8000
462 #define FPGA_REG16_VCO_DIV_10 0xc000
463 /* Master Clock Selection */
464 /* S3, S4 switches on Board */
465 #define FPGA_REG16_MASTER_CLK_MASK 0x01c0
466 #define FPGA_REG16_MASTER_CLK_EXT 0x0000
467 #define FPGA_REG16_MASTER_CLK_66_66 0x0040
468 #define FPGA_REG16_MASTER_CLK_50 0x0080
469 #define FPGA_REG16_MASTER_CLK_33_33 0x00c0
470 #define FPGA_REG16_MASTER_CLK_25 0x0100
472 /*----------------------------------------------------------------------------+
474 +----------------------------------------------------------------------------*/
475 #define FPGA_REG18 (FPGA_REG_BASE_ADDR+0x18)
477 #define FPGA_REG18_PCI_PRSNT1 0x8000
478 #define FPGA_REG18_PCI_PRSNT2 0x4000
479 #define FPGA_REG18_PCI_INTA 0x2000
480 #define FPGA_REG18_PCI_SLOT0_INTP 0x1000
481 #define FPGA_REG18_PCI_SLOT1_INTP 0x0800
482 #define FPGA_REG18_PCI_SLOT2_INTP 0x0400
483 #define FPGA_REG18_PCI_SLOT3_INTP 0x0200
484 #define FPGA_REG18_PCI_PCI0_VC 0x0100
485 #define FPGA_REG18_PCI_PCI0_VTH1 0x0080
486 #define FPGA_REG18_PCI_PCI0_VTH2 0x0040
487 #define FPGA_REG18_PCI_PCI0_VTH3 0x0020
489 /*----------------------------------------------------------------------------+
491 +----------------------------------------------------------------------------*/
492 #define FPGA_REG1A (FPGA_REG_BASE_ADDR+0x1A)
494 #define FPGA_REG1A_PE0_GLED 0x8000
495 #define FPGA_REG1A_PE1_GLED 0x4000
496 #define FPGA_REG1A_PE2_GLED 0x2000
497 #define FPGA_REG1A_PE0_YLED 0x1000
498 #define FPGA_REG1A_PE1_YLED 0x0800
499 #define FPGA_REG1A_PE2_YLED 0x0400
500 #define FPGA_REG1A_PE0_PWRON 0x0200
501 #define FPGA_REG1A_PE1_PWRON 0x0100
502 #define FPGA_REG1A_PE2_PWRON 0x0080
503 #define FPGA_REG1A_PE0_REFCLK_ENABLE 0x0040
504 #define FPGA_REG1A_PE1_REFCLK_ENABLE 0x0020
505 #define FPGA_REG1A_PE2_REFCLK_ENABLE 0x0010
506 #define FPGA_REG1A_PE_SPREAD0 0x0008
507 #define FPGA_REG1A_PE_SPREAD1 0x0004
508 #define FPGA_REG1A_PE_SELSOURCE_0 0x0002
509 #define FPGA_REG1A_PE_SELSOURCE_1 0x0001
511 /*----------------------------------------------------------------------------+
513 +----------------------------------------------------------------------------*/
514 #define FPGA_REG1C (FPGA_REG_BASE_ADDR+0x1C)
516 #define FPGA_REG1C_PE0_ROOTPOINT 0x8000
517 #define FPGA_REG1C_PE1_ENDPOINT 0x4000
518 #define FPGA_REG1C_PE2_ENDPOINT 0x2000
519 #define FPGA_REG1C_PE0_PRSNT 0x1000
520 #define FPGA_REG1C_PE1_PRSNT 0x0800
521 #define FPGA_REG1C_PE2_PRSNT 0x0400
522 #define FPGA_REG1C_PE0_WAKE 0x0080
523 #define FPGA_REG1C_PE1_WAKE 0x0040
524 #define FPGA_REG1C_PE2_WAKE 0x0020
525 #define FPGA_REG1C_PE0_PERST 0x0010
526 #define FPGA_REG1C_PE1_PERST 0x0008
527 #define FPGA_REG1C_PE2_PERST 0x0004
529 /*----------------------------------------------------------------------------+
531 +----------------------------------------------------------------------------*/
532 #define PERIOD_133_33MHZ 7500 /* 7,5ns */
533 #define PERIOD_100_00MHZ 10000 /* 10ns */
534 #define PERIOD_83_33MHZ 12000 /* 12ns */
535 #define PERIOD_75_00MHZ 13333 /* 13,333ns */
536 #define PERIOD_66_66MHZ 15000 /* 15ns */
537 #define PERIOD_50_00MHZ 20000 /* 20ns */
538 #define PERIOD_33_33MHZ 30000 /* 30ns */
539 #define PERIOD_25_00MHZ 40000 /* 40ns */
541 /*---------------------------------------------------------------------------*/
543 /* pass open firmware flat tree */
544 #define CONFIG_OF_LIBFDT 1
545 #define CONFIG_OF_BOARD_SETUP 1
547 #endif /* __CONFIG_H */