2 * Common internal memory map for some Freescale SoCs
4 * Copyright 2014 Freescale Semiconductor, Inc.
14 /* Security Engine Block (MS = Most Sig., LS = Least Sig.) */
15 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
16 typedef struct ccsr_sec {
18 u32 mcfgr; /* Master CFG Register */
22 u32 ms; /* Job Ring LIODN Register, MS */
23 u32 ls; /* Job Ring LIODN Register, LS */
26 u32 jrstartr; /* Job Ring Start Register */
28 u32 ms; /* RTIC LIODN Register, MS */
29 u32 ls; /* RTIC LIODN Register, LS */
32 u32 decorr; /* DECO Request Register */
34 u32 ms; /* DECO LIODN Register, MS */
35 u32 ls; /* DECO LIODN Register, LS */
38 u32 dar; /* DECO Avail Register */
39 u32 drr; /* DECO Reset Register */
41 u32 crnr_ms; /* CHA Revision Number Register, MS */
42 u32 crnr_ls; /* CHA Revision Number Register, LS */
43 u32 ctpr_ms; /* Compile Time Parameters Register, MS */
44 u32 ctpr_ls; /* Compile Time Parameters Register, LS */
46 u32 far_ms; /* Fault Address Register, MS */
47 u32 far_ls; /* Fault Address Register, LS */
48 u32 falr; /* Fault Address LIODN Register */
49 u32 fadr; /* Fault Address Detail Register */
51 u32 csta; /* CAAM Status Register */
53 u32 rvid; /* Run Time Integrity Checking Version ID Reg.*/
54 u32 ccbvid; /* CHA Cluster Block Version ID Register */
55 u32 chavid_ms; /* CHA Version ID Register, MS */
56 u32 chavid_ls; /* CHA Version ID Register, LS */
57 u32 chanum_ms; /* CHA Number Register, MS */
58 u32 chanum_ls; /* CHA Number Register, LS */
59 u32 secvid_ms; /* SEC Version ID Register, MS */
60 u32 secvid_ls; /* SEC Version ID Register, LS */
62 u32 qilcr_ms; /* Queue Interface LIODN CFG Register, MS */
63 u32 qilcr_ls; /* Queue Interface LIODN CFG Register, LS */
67 #define SEC_CTPR_MS_AXI_LIODN 0x08000000
68 #define SEC_CTPR_MS_QI 0x02000000
69 #define SEC_CTPR_MS_VIRT_EN_INCL 0x00000001
70 #define SEC_CTPR_MS_VIRT_EN_POR 0x00000002
71 #define SEC_RVID_MA 0x0f000000
72 #define SEC_CHANUM_MS_JRNUM_MASK 0xf0000000
73 #define SEC_CHANUM_MS_JRNUM_SHIFT 28
74 #define SEC_CHANUM_MS_DECONUM_MASK 0x0f000000
75 #define SEC_CHANUM_MS_DECONUM_SHIFT 24
76 #define SEC_SECVID_MS_IPID_MASK 0xffff0000
77 #define SEC_SECVID_MS_IPID_SHIFT 16
78 #define SEC_SECVID_MS_MAJ_REV_MASK 0x0000ff00
79 #define SEC_SECVID_MS_MAJ_REV_SHIFT 8
80 #define SEC_CCBVID_ERA_MASK 0xff000000
81 #define SEC_CCBVID_ERA_SHIFT 24
82 #define SEC_SCFGR_RDBENABLE 0x00000400
83 #define SEC_SCFGR_VIRT_EN 0x00008000
84 #define SEC_CHAVID_LS_RNG_SHIFT 16
85 #define SEC_CHAVID_RNG_LS_MASK 0x000f0000
88 #endif /* __FSL_SEC_H */