2 * See file CREDITS for list of people who contributed to this
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * lh7a40x SoC series common interface
28 /* (SMC) Static Memory Controller (usersguide 4.2.1) */
34 } /*__attribute__((__packed__))*/ lh7a40x_pccard_t;
38 lh7a40x_pccard_t pccard[2];
39 volatile u32 pcmciacon;
40 } /*__attribute__((__packed__))*/ lh7a40x_smc_t;
41 #define LH7A40X_SMC_BASE (0x80002000)
42 #define LH7A40X_SMC_PTR(name) lh7a40x_smc_t* name = (lh7a40x_smc_t*) LH7A40X_SMC_BASE
44 /* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
49 volatile u32 bootstat;
50 volatile u32 sdcsc[4];
51 } /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
52 #define LH7A40X_SDMC_BASE (0x80002400)
53 #define LH7A40X_SDMC_PTR(name) lh7a40x_sdmc_t* name = (lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE
55 /* (CSC) Clock and State Controller (userguide 6.2.1) */
66 volatile u32 scrreg[2];
68 volatile u32 usbreset;
69 } /*__attribute__((__packed__))*/ lh7a40x_csc_t;
70 #define LH7A40X_STPWR_BASE (0x80000400)
71 #define LH7A40X_CSC_PTR(name) lh7a40x_csc_t* name = (lh7a40x_csc_t*) LH7A40X_STPWR_BASE
73 #define CLKSET_SMCROM (0x01000000)
74 #define CLKSET_PS (0x000C0000)
75 #define CLKSET_PS_0 (0x00000000)
76 #define CLKSET_PS_1 (0x00040000)
77 #define CLKSET_PS_2 (0x00080000)
78 #define CLKSET_PS_3 (0x000C0000)
79 #define CLKSET_PCLKDIV (0x00030000)
80 #define CLKSET_PCLKDIV_2 (0x00000000)
81 #define CLKSET_PCLKDIV_4 (0x00010000)
82 #define CLKSET_PCLKDIV_8 (0x00020000)
83 #define CLKSET_MAINDIV2 (0x0000f800)
84 #define CLKSET_MAINDIV1 (0x00000780)
85 #define CLKSET_PREDIV (0x0000007C)
86 #define CLKSET_HCLKDIV (0x00000003)
88 /* (WDT) Watchdog Timer (userguide 11.2.1) */
93 volatile u32 count[4];
94 } /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
95 #define LH7A40X_WDT_BASE (0x80001400)
96 #define LH7A40X_WDT_PTR(name) lh7a40x_wdt_t* name = (lh7a40x_wdt_t*) LH7A40X_WDT_BASE
98 /* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
104 volatile u32 rtcstat_eoi;
106 volatile u32 rsvd1[58];
107 } /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
108 #define LH7A40X_RTC_BASE (0x80000D00)
109 #define LH7A40X_RTC_PTR(name) lh7a40x_rtc_t* name = (lh7a40x_rtc_t*) LH7A40X_RTC_BASE
111 /* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
115 volatile u32 control;
117 } /*__attribute__((__packed__))*/ lh7a40x_timer_t;
120 lh7a40x_timer_t timer1;
121 volatile u32 rsvd1[4];
122 lh7a40x_timer_t timer2;
123 volatile u32 unk1[4];
125 volatile u32 unk2[15];
126 lh7a40x_timer_t timer3;
127 /*volatile u32 rsvd2;*/
128 } /*__attribute__((__packed__))*/ lh7a40x_timers_t;
129 #define LH7A40X_TIMERS_BASE (0x80000C00)
130 #define LH7A40X_TIMERS_PTR(name) lh7a40x_timers_t* name = (lh7a40x_timers_t*) LH7A40X_TIMERS_BASE
132 #define TIMER_EN (0x00000080)
133 #define TIMER_PER (0x00000040)
134 #define TIMER_FREE (0x00000000)
135 #define TIMER_CLK508K (0x00000008)
136 #define TIMER_CLK2K (0x00000000)
138 /* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */
142 volatile u32 irr_roeoi;
146 /*volatile u32 rsvd1[58];*/
147 } /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
148 #define LH7A40X_SSP_BASE (0x80000B00)
149 #define LH7A40X_SSP_PTR(name) lh7a40x_ssp_t* name = (lh7a40x_ssp_t*) LH7A40X_SSP_BASE
151 /* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
161 volatile u32 rsvd1[56];
162 } /*__attribute__((__packed__))*/ lh7a40x_uart_t;
163 #define LH7A40X_UART_BASE (0x80000600)
164 #define LH7A40X_UART_PTR(name,n) \
165 lh7a40x_uart_t* name = (lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t)))
167 #define UART_BE (0x00000800) /* the rx error bits */
168 #define UART_OE (0x00000400)
169 #define UART_PE (0x00000200)
170 #define UART_FE (0x00000100)
172 #define UART_WLEN (0x00000060) /* fcon bits */
173 #define UART_WLEN_8 (0x00000060)
174 #define UART_WLEN_7 (0x00000040)
175 #define UART_WLEN_6 (0x00000020)
176 #define UART_WLEN_5 (0x00000000)
177 #define UART_FEN (0x00000010)
178 #define UART_STP2 (0x00000008)
179 #define UART_STP2_2 (0x00000008)
180 #define UART_STP2_1 (0x00000000)
181 #define UART_EPS (0x00000004)
182 #define UART_EPS_EVEN (0x00000004)
183 #define UART_EPS_ODD (0x00000000)
184 #define UART_PEN (0x00000002)
185 #define UART_BRK (0x00000001)
187 #define UART_BAUDDIV (0x0000ffff) /* brcon bits */
189 #define UART_SIRBD (0x00000080) /* con bits */
190 #define UART_LBE (0x00000040)
191 #define UART_MXP (0x00000020)
192 #define UART_TXP (0x00000010)
193 #define UART_RXP (0x00000008)
194 #define UART_SIRLP (0x00000004)
195 #define UART_SIRD (0x00000002)
196 #define UART_EN (0x00000001)
198 #define UART_TXFE (0x00000080) /* status bits */
199 #define UART_RXFF (0x00000040)
200 #define UART_TXFF (0x00000020)
201 #define UART_RXFE (0x00000010)
202 #define UART_BUSY (0x00000008)
203 #define UART_DCD (0x00000004)
204 #define UART_DSR (0x00000002)
205 #define UART_CTS (0x00000001)
207 #define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */
209 #define UART_RTI (0x00000008) /* generic interrupt bits */
210 #define UART_MI (0x00000004)
211 #define UART_TI (0x00000002)
212 #define UART_RI (0x00000001)
214 /* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */
235 volatile u32 inttype1;
236 volatile u32 inttype2;
237 volatile u32 gpiofeoi;
238 volatile u32 gpiointen;
239 volatile u32 intstatus;
240 volatile u32 rawintstatus;
250 } /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
251 #define LH7A40X_GPIOINT_BASE (0x80000E00)
252 #define LH7A40X_GPIOINT_PTR(name) lh7a40x_gpioint_t* name = (lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE
255 #define CFG_SRAM_BASE (0xB0000000)
256 #define CFG_SRAM_SIZE (80*1024) /* 80kB */
258 #endif /* __LH7A40X_H__ */