2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 * Contains standard defines and IDs for NAND flash devices
16 #ifndef __LINUX_MTD_NAND_H
17 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
29 #include "linux/compat.h"
30 #include "linux/mtd/mtd.h"
31 #include "linux/mtd/flashchip.h"
32 #include "linux/mtd/bbm.h"
36 struct nand_flash_dev;
37 /* Scan and identify a NAND device */
38 extern int nand_scan(struct mtd_info *mtd, int max_chips);
40 * Separate phases of nand_scan(), allowing board driver to intervene
41 * and override command or ECC setup according to flash type.
43 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
44 struct nand_flash_dev *table);
45 extern int nand_scan_tail(struct mtd_info *mtd);
47 /* Free resources held by the NAND device */
48 extern void nand_release(struct mtd_info *mtd);
50 /* Internal helper for board drivers which need to override command function */
51 extern void nand_wait_ready(struct mtd_info *mtd);
54 /* locks all blocks present in the device */
55 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
57 /* unlocks specified locked blocks */
58 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
60 /* The maximum number of NAND chips in an array */
61 #define NAND_MAX_CHIPS 8
65 * This constant declares the max. oobsize / page, which
66 * is supported now. If you add a chip with bigger oobsize/page
67 * adjust this accordingly.
69 #define NAND_MAX_OOBSIZE 744
70 #define NAND_MAX_PAGESIZE 8192
73 * Constants for hardware specific CLE/ALE/NCE function
75 * These are bits which can be or'ed to set/clear multiple
78 /* Select the chip by setting nCE to low */
80 /* Select the command latch by setting CLE to high */
82 /* Select the address latch by setting ALE to high */
85 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
86 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
87 #define NAND_CTRL_CHANGE 0x80
90 * Standard NAND flash commands
92 #define NAND_CMD_READ0 0
93 #define NAND_CMD_READ1 1
94 #define NAND_CMD_RNDOUT 5
95 #define NAND_CMD_PAGEPROG 0x10
96 #define NAND_CMD_READOOB 0x50
97 #define NAND_CMD_ERASE1 0x60
98 #define NAND_CMD_STATUS 0x70
99 #define NAND_CMD_SEQIN 0x80
100 #define NAND_CMD_RNDIN 0x85
101 #define NAND_CMD_READID 0x90
102 #define NAND_CMD_ERASE2 0xd0
103 #define NAND_CMD_PARAM 0xec
104 #define NAND_CMD_GET_FEATURES 0xee
105 #define NAND_CMD_SET_FEATURES 0xef
106 #define NAND_CMD_RESET 0xff
108 #define NAND_CMD_LOCK 0x2a
109 #define NAND_CMD_UNLOCK1 0x23
110 #define NAND_CMD_UNLOCK2 0x24
112 /* Extended commands for large page devices */
113 #define NAND_CMD_READSTART 0x30
114 #define NAND_CMD_RNDOUTSTART 0xE0
115 #define NAND_CMD_CACHEDPROG 0x15
117 /* Extended commands for AG-AND device */
119 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
120 * there is no way to distinguish that from NAND_CMD_READ0
121 * until the remaining sequence of commands has been completed
122 * so add a high order bit and mask it off in the command.
124 #define NAND_CMD_DEPLETE1 0x100
125 #define NAND_CMD_DEPLETE2 0x38
126 #define NAND_CMD_STATUS_MULTI 0x71
127 #define NAND_CMD_STATUS_ERROR 0x72
128 /* multi-bank error status (banks 0-3) */
129 #define NAND_CMD_STATUS_ERROR0 0x73
130 #define NAND_CMD_STATUS_ERROR1 0x74
131 #define NAND_CMD_STATUS_ERROR2 0x75
132 #define NAND_CMD_STATUS_ERROR3 0x76
133 #define NAND_CMD_STATUS_RESET 0x7f
134 #define NAND_CMD_STATUS_CLEAR 0xff
136 #define NAND_CMD_NONE -1
139 #define NAND_STATUS_FAIL 0x01
140 #define NAND_STATUS_FAIL_N1 0x02
141 #define NAND_STATUS_TRUE_READY 0x20
142 #define NAND_STATUS_READY 0x40
143 #define NAND_STATUS_WP 0x80
146 * Constants for ECC_MODES
152 NAND_ECC_HW_SYNDROME,
153 NAND_ECC_HW_OOB_FIRST,
158 * Constants for Hardware ECC
160 /* Reset Hardware ECC for read */
161 #define NAND_ECC_READ 0
162 /* Reset Hardware ECC for write */
163 #define NAND_ECC_WRITE 1
164 /* Enable Hardware ECC before syndrome is read back from flash */
165 #define NAND_ECC_READSYN 2
167 /* Bit mask for flags passed to do_nand_read_ecc */
168 #define NAND_GET_DEVICE 0x80
172 * Option constants for bizarre disfunctionality and real
175 /* Buswidth is 16 bit */
176 #define NAND_BUSWIDTH_16 0x00000002
177 /* Device supports partial programming without padding */
178 #define NAND_NO_PADDING 0x00000004
179 /* Chip has cache program function */
180 #define NAND_CACHEPRG 0x00000008
181 /* Chip has copy back function */
182 #define NAND_COPYBACK 0x00000010
184 * Chip requires ready check on read (for auto-incremented sequential read).
185 * True only for small page devices; large page devices do not support
188 #define NAND_NEED_READRDY 0x00000100
190 /* Chip does not allow subpage writes */
191 #define NAND_NO_SUBPAGE_WRITE 0x00000200
193 /* Device is one of 'new' xD cards that expose fake nand command set */
194 #define NAND_BROKEN_XD 0x00000400
196 /* Device behaves just like nand, but is readonly */
197 #define NAND_ROM 0x00000800
199 /* Device supports subpage reads */
200 #define NAND_SUBPAGE_READ 0x00001000
202 /* Options valid for Samsung large page devices */
203 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
205 /* Macros to identify the above */
206 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
207 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
209 /* Non chip related options */
210 /* This option skips the bbt scan during initialization. */
211 #define NAND_SKIP_BBTSCAN 0x00010000
213 * This option is defined if the board driver allocates its own buffers
214 * (e.g. because it needs them DMA-coherent).
216 #define NAND_OWN_BUFFERS 0x00020000
217 /* Chip may not exist, so silence any errors in scan */
218 #define NAND_SCAN_SILENT_NODEV 0x00040000
220 * Autodetect nand buswidth with readid/onfi.
221 * This suppose the driver will configure the hardware in 8 bits mode
222 * when calling nand_scan_ident, and update its configuration
223 * before calling nand_scan_tail.
225 #define NAND_BUSWIDTH_AUTO 0x00080000
227 /* Options set by nand scan */
228 /* bbt has already been read */
229 #define NAND_BBT_SCANNED 0x40000000
230 /* Nand scan has allocated controller struct */
231 #define NAND_CONTROLLER_ALLOC 0x80000000
233 /* Cell info constants */
234 #define NAND_CI_CHIPNR_MSK 0x03
235 #define NAND_CI_CELLTYPE_MSK 0x0C
236 #define NAND_CI_CELLTYPE_SHIFT 2
242 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
243 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
245 /* ONFI timing mode, used in both asynchronous and synchronous mode */
246 #define ONFI_TIMING_MODE_0 (1 << 0)
247 #define ONFI_TIMING_MODE_1 (1 << 1)
248 #define ONFI_TIMING_MODE_2 (1 << 2)
249 #define ONFI_TIMING_MODE_3 (1 << 3)
250 #define ONFI_TIMING_MODE_4 (1 << 4)
251 #define ONFI_TIMING_MODE_5 (1 << 5)
252 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
254 /* ONFI feature address */
255 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
257 /* Vendor-specific feature address (Micron) */
258 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
260 /* ONFI subfeature parameters length */
261 #define ONFI_SUBFEATURE_PARAM_LEN 4
263 /* ONFI optional commands SET/GET FEATURES supported? */
264 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
266 struct nand_onfi_params {
267 /* rev info and features block */
268 /* 'O' 'N' 'F' 'I' */
274 __le16 ext_param_page_length; /* since ONFI 2.1 */
275 u8 num_of_param_pages; /* since ONFI 2.1 */
278 /* manufacturer information block */
279 char manufacturer[12];
285 /* memory organization block */
286 __le32 byte_per_page;
287 __le16 spare_bytes_per_page;
288 __le32 data_bytes_per_ppage;
289 __le16 spare_bytes_per_ppage;
290 __le32 pages_per_block;
291 __le32 blocks_per_lun;
296 __le16 block_endurance;
297 u8 guaranteed_good_blocks;
298 __le16 guaranteed_block_endurance;
299 u8 programs_per_page;
306 /* electrical parameter block */
307 u8 io_pin_capacitance_max;
308 __le16 async_timing_mode;
309 __le16 program_cache_timing_mode;
314 __le16 src_sync_timing_mode;
315 __le16 src_ssync_features;
316 __le16 clk_pin_capacitance_typ;
317 __le16 io_pin_capacitance_typ;
318 __le16 input_pin_capacitance_typ;
319 u8 input_pin_capacitance_max;
320 u8 driver_strength_support;
326 __le16 vendor_revision;
332 #define ONFI_CRC_BASE 0x4F4E
334 /* Extended ECC information Block Definition (since ONFI 2.1) */
335 struct onfi_ext_ecc_info {
339 __le16 block_endurance;
343 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
344 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
345 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
346 struct onfi_ext_section {
351 #define ONFI_EXT_SECTION_MAX 8
353 /* Extended Parameter Page Definition (since ONFI 2.1) */
354 struct onfi_ext_param_page {
356 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
358 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
361 * The actual size of the Extended Parameter Page is in
362 * @ext_param_page_length of nand_onfi_params{}.
363 * The following are the variable length sections.
364 * So we do not add any fields below. Please see the ONFI spec.
368 struct nand_onfi_vendor_micron {
373 u8 dq_imped_num_settings;
374 u8 dq_imped_feat_addr;
375 u8 rb_pulldown_strength;
376 u8 rb_pulldown_strength_feat_addr;
377 u8 rb_pulldown_strength_num_settings;
380 u8 otp_data_prot_addr;
383 u8 read_retry_options;
389 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
390 * @lock: protection lock
391 * @active: the mtd device which holds the controller currently
392 * @wq: wait queue to sleep on if a NAND operation is in
393 * progress used instead of the per chip wait queue
394 * when a hw controller is available.
396 struct nand_hw_control {
398 struct nand_chip *active;
400 wait_queue_head_t wq;
405 * struct nand_ecc_ctrl - Control structure for ECC
407 * @steps: number of ECC steps per page
408 * @size: data bytes per ECC step
409 * @bytes: ECC bytes per step
410 * @strength: max number of correctible bits per ECC step
411 * @total: total number of ECC bytes per page
412 * @prepad: padding information for syndrome based ECC generators
413 * @postpad: padding information for syndrome based ECC generators
414 * @layout: ECC layout control struct pointer
415 * @priv: pointer to private ECC control data
416 * @hwctl: function to control hardware ECC generator. Must only
417 * be provided if an hardware ECC is available
418 * @calculate: function for ECC calculation or readback from ECC hardware
419 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
420 * @read_page_raw: function to read a raw page without ECC
421 * @write_page_raw: function to write a raw page without ECC
422 * @read_page: function to read a page according to the ECC generator
423 * requirements; returns maximum number of bitflips corrected in
424 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
425 * @read_subpage: function to read parts of the page covered by ECC;
426 * returns same as read_page()
427 * @write_subpage: function to write parts of the page covered by ECC.
428 * @write_page: function to write a page according to the ECC generator
430 * @write_oob_raw: function to write chip OOB data without ECC
431 * @read_oob_raw: function to read chip OOB data without ECC
432 * @read_oob: function to read chip OOB data
433 * @write_oob: function to write chip OOB data
435 struct nand_ecc_ctrl {
436 nand_ecc_modes_t mode;
444 struct nand_ecclayout *layout;
446 void (*hwctl)(struct mtd_info *mtd, int mode);
447 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
449 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
451 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
452 uint8_t *buf, int oob_required, int page);
453 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
454 const uint8_t *buf, int oob_required);
455 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
456 uint8_t *buf, int oob_required, int page);
457 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
458 uint32_t offs, uint32_t len, uint8_t *buf);
459 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
460 uint32_t offset, uint32_t data_len,
461 const uint8_t *data_buf, int oob_required);
462 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
463 const uint8_t *buf, int oob_required);
464 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
466 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
468 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
469 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
474 * struct nand_buffers - buffer structure for read/write
475 * @ecccalc: buffer for calculated ECC
476 * @ecccode: buffer for ECC read from flash
477 * @databuf: buffer for data - dynamically sized
479 * Do not change the order of buffers. databuf and oobrbuf must be in
482 struct nand_buffers {
488 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
489 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
490 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
496 * struct nand_chip - NAND Private Flash Chip Data
497 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
499 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
501 * @read_byte: [REPLACEABLE] read one byte from the chip
502 * @read_word: [REPLACEABLE] read one word from the chip
503 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
505 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
506 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
507 * @select_chip: [REPLACEABLE] select chip nr
508 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
509 * @block_markbad: [REPLACEABLE] mark a block bad
510 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
511 * ALE/CLE/nCE. Also used to write command and address
512 * @init_size: [BOARDSPECIFIC] hardwarespecific function for setting
513 * mtd->oobsize, mtd->writesize and so on.
514 * @id_data contains the 8 bytes values of NAND_CMD_READID.
515 * Return with the bus width.
516 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
517 * device ready/busy line. If set to NULL no access to
518 * ready/busy is available and the ready/busy information
519 * is read from the chip status register.
520 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
521 * commands to the chip.
522 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
524 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
525 * setting the read-retry mode. Mostly needed for MLC NAND.
526 * @ecc: [BOARDSPECIFIC] ECC control structure
527 * @buffers: buffer structure for read/write
528 * @hwcontrol: platform-specific hardware control structure
529 * @erase_cmd: [INTERN] erase command write function, selectable due
531 * @scan_bbt: [REPLACEABLE] function to scan bad block table
532 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
533 * data from array to read regs (tR).
534 * @state: [INTERN] the current state of the NAND device
535 * @oob_poi: "poison value buffer," used for laying out OOB data
537 * @page_shift: [INTERN] number of address bits in a page (column
539 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
540 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
541 * @chip_shift: [INTERN] number of address bits in one chip
542 * @options: [BOARDSPECIFIC] various chip options. They can partly
543 * be set to inform nand_scan about special functionality.
544 * See the defines for further explanation.
545 * @bbt_options: [INTERN] bad block specific options. All options used
546 * here must come from bbm.h. By default, these options
547 * will be copied to the appropriate nand_bbt_descr's.
548 * @badblockpos: [INTERN] position of the bad block marker in the oob
550 * @badblockbits: [INTERN] minimum number of set bits in a good block's
551 * bad block marker position; i.e., BBM == 11110111b is
552 * not bad when badblockbits == 7
553 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
554 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
555 * Minimum amount of bit errors per @ecc_step_ds guaranteed
556 * to be correctable. If unknown, set to zero.
557 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
558 * also from the datasheet. It is the recommended ECC step
559 * size, if known; if unknown, set to zero.
560 * @numchips: [INTERN] number of physical chips
561 * @chipsize: [INTERN] the size of one chip for multichip arrays
562 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
563 * @pagebuf: [INTERN] holds the pagenumber which is currently in
565 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
566 * currently in data_buf.
567 * @subpagesize: [INTERN] holds the subpagesize
568 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
569 * non 0 if ONFI supported.
570 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
571 * supported, 0 otherwise.
572 * @read_retries: [INTERN] the number of read retry modes supported
573 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
574 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
575 * @bbt: [INTERN] bad block table pointer
576 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
578 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
579 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
581 * @controller: [REPLACEABLE] a pointer to a hardware controller
582 * structure which is shared among multiple independent
584 * @priv: [OPTIONAL] pointer to private chip data
585 * @errstat: [OPTIONAL] hardware specific function to perform
586 * additional error status checks (determine if errors are
588 * @write_page: [REPLACEABLE] High-level page write function
592 void __iomem *IO_ADDR_R;
593 void __iomem *IO_ADDR_W;
595 uint8_t (*read_byte)(struct mtd_info *mtd);
596 u16 (*read_word)(struct mtd_info *mtd);
597 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
598 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
599 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
601 #if defined(CONFIG_MTD_NAND_VERIFY_WRITE)
602 int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
605 void (*select_chip)(struct mtd_info *mtd, int chip);
606 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
607 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
608 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
609 int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
611 int (*dev_ready)(struct mtd_info *mtd);
612 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
614 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
615 void (*erase_cmd)(struct mtd_info *mtd, int page);
616 int (*scan_bbt)(struct mtd_info *mtd);
617 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
618 int status, int page);
619 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
620 uint32_t offset, int data_len, const uint8_t *buf,
621 int oob_required, int page, int cached, int raw);
622 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
623 int feature_addr, uint8_t *subfeature_para);
624 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
625 int feature_addr, uint8_t *subfeature_para);
626 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
629 unsigned int options;
630 unsigned int bbt_options;
633 int phys_erase_shift;
640 unsigned int pagebuf_bitflips;
642 uint8_t bits_per_cell;
643 uint16_t ecc_strength_ds;
644 uint16_t ecc_step_ds;
649 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
650 struct nand_onfi_params onfi_params;
658 struct nand_hw_control *controller;
660 struct nand_ecclayout *ecclayout;
663 struct nand_ecc_ctrl ecc;
664 struct nand_buffers *buffers;
665 struct nand_hw_control hwcontrol;
668 struct nand_bbt_descr *bbt_td;
669 struct nand_bbt_descr *bbt_md;
671 struct nand_bbt_descr *badblock_pattern;
677 * NAND Flash Manufacturer ID Codes
679 #define NAND_MFR_TOSHIBA 0x98
680 #define NAND_MFR_SAMSUNG 0xec
681 #define NAND_MFR_FUJITSU 0x04
682 #define NAND_MFR_NATIONAL 0x8f
683 #define NAND_MFR_RENESAS 0x07
684 #define NAND_MFR_STMICRO 0x20
685 #define NAND_MFR_HYNIX 0xad
686 #define NAND_MFR_MICRON 0x2c
687 #define NAND_MFR_AMD 0x01
688 #define NAND_MFR_MACRONIX 0xc2
689 #define NAND_MFR_EON 0x92
690 #define NAND_MFR_SANDISK 0x45
691 #define NAND_MFR_INTEL 0x89
693 /* The maximum expected count of bytes in the NAND ID sequence */
694 #define NAND_MAX_ID_LEN 8
697 * A helper for defining older NAND chips where the second ID byte fully
698 * defined the chip, including the geometry (chip size, eraseblock size, page
699 * size). All these chips have 512 bytes NAND page size.
701 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
702 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
703 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
706 * A helper for defining newer chips which report their page size and
707 * eraseblock size via the extended ID bytes.
709 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
710 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
711 * device ID now only represented a particular total chip size (and voltage,
712 * buswidth), and the page size, eraseblock size, and OOB size could vary while
713 * using the same device ID.
715 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
716 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
719 #define NAND_ECC_INFO(_strength, _step) \
720 { .strength_ds = (_strength), .step_ds = (_step) }
721 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
722 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
725 * struct nand_flash_dev - NAND Flash Device ID Structure
726 * @name: a human-readable name of the NAND chip
727 * @dev_id: the device ID (the second byte of the full chip ID array)
728 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
729 * memory address as @id[0])
730 * @dev_id: device ID part of the full chip ID array (refers the same memory
732 * @id: full device ID array
733 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
734 * well as the eraseblock size) is determined from the extended NAND
736 * @chipsize: total chip size in MiB
737 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
738 * @options: stores various chip bit options
739 * @id_len: The valid length of the @id.
741 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
742 * @ecc_strength_ds in nand_chip{}.
743 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
744 * @ecc_step_ds in nand_chip{}, also from the datasheet.
745 * For example, the "4bit ECC for each 512Byte" can be set with
746 * NAND_ECC_INFO(4, 512).
748 struct nand_flash_dev {
755 uint8_t id[NAND_MAX_ID_LEN];
757 unsigned int pagesize;
758 unsigned int chipsize;
759 unsigned int erasesize;
760 unsigned int options;
764 uint16_t strength_ds;
770 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
771 * @name: Manufacturer name
772 * @id: manufacturer ID code of device.
774 struct nand_manufacturers {
779 extern struct nand_flash_dev nand_flash_ids[];
780 extern struct nand_manufacturers nand_manuf_ids[];
782 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
783 extern int nand_default_bbt(struct mtd_info *mtd);
784 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
785 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
786 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
788 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
789 size_t *retlen, uint8_t *buf);
793 * Constants for oob configuration
795 #define NAND_SMALL_BADBLOCK_POS 5
796 #define NAND_LARGE_BADBLOCK_POS 0
800 * struct platform_nand_chip - chip level device structure
801 * @nr_chips: max. number of chips to scan for
802 * @chip_offset: chip number offset
803 * @nr_partitions: number of partitions pointed to by partitions (or zero)
804 * @partitions: mtd partition list
805 * @chip_delay: R/B delay value in us
806 * @options: Option flags, e.g. 16bit buswidth
807 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
808 * @ecclayout: ECC layout info structure
809 * @part_probe_types: NULL-terminated array of probe types
811 struct platform_nand_chip {
815 struct mtd_partition *partitions;
816 struct nand_ecclayout *ecclayout;
818 unsigned int options;
819 unsigned int bbt_options;
820 const char **part_probe_types;
824 struct platform_device;
827 * struct platform_nand_ctrl - controller level device structure
828 * @probe: platform specific function to probe/setup hardware
829 * @remove: platform specific function to remove/teardown hardware
830 * @hwcontrol: platform specific hardware control structure
831 * @dev_ready: platform specific function to read ready/busy pin
832 * @select_chip: platform specific chip select function
833 * @cmd_ctrl: platform specific function for controlling
834 * ALE/CLE/nCE. Also used to write command and address
835 * @write_buf: platform specific function for write buffer
836 * @read_buf: platform specific function for read buffer
837 * @read_byte: platform specific function to read one byte from chip
838 * @priv: private data to transport driver specific settings
840 * All fields are optional and depend on the hardware driver requirements
842 struct platform_nand_ctrl {
843 int (*probe)(struct platform_device *pdev);
844 void (*remove)(struct platform_device *pdev);
845 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
846 int (*dev_ready)(struct mtd_info *mtd);
847 void (*select_chip)(struct mtd_info *mtd, int chip);
848 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
849 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
850 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
851 unsigned char (*read_byte)(struct mtd_info *mtd);
856 * struct platform_nand_data - container structure for platform-specific data
857 * @chip: chip level chip structure
858 * @ctrl: controller level device structure
860 struct platform_nand_data {
861 struct platform_nand_chip chip;
862 struct platform_nand_ctrl ctrl;
865 /* Some helpers to access the data structures */
867 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
869 struct nand_chip *chip = mtd->priv;
874 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
875 /* return the supported features. */
876 static inline int onfi_feature(struct nand_chip *chip)
878 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
881 /* return the supported asynchronous timing mode. */
882 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
884 if (!chip->onfi_version)
885 return ONFI_TIMING_MODE_UNKNOWN;
886 return le16_to_cpu(chip->onfi_params.async_timing_mode);
889 /* return the supported synchronous timing mode. */
890 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
892 if (!chip->onfi_version)
893 return ONFI_TIMING_MODE_UNKNOWN;
894 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
899 * Check if it is a SLC nand.
900 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
901 * We do not distinguish the MLC and TLC now.
903 static inline bool nand_is_slc(struct nand_chip *chip)
905 return chip->bits_per_cell == 1;
909 * Check if the opcode's address should be sent only on the lower 8 bits
910 * @command: opcode to check
912 static inline int nand_opcode_8bits(unsigned int command)
915 case NAND_CMD_READID:
917 case NAND_CMD_GET_FEATURES:
918 case NAND_CMD_SET_FEATURES:
927 /* Standard NAND functions from nand_base.c */
928 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
929 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
930 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
931 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
932 uint8_t nand_read_byte(struct mtd_info *mtd);
934 #endif /* __LINUX_MTD_NAND_H */