2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * SPDX-License-Identifier: GPL-2.0+
11 * Contains standard defines and IDs for NAND flash devices
16 #ifndef __LINUX_MTD_NAND_H
17 #define __LINUX_MTD_NAND_H
21 #include <linux/compat.h>
22 #include <linux/mtd/mtd.h>
23 #include <linux/mtd/flashchip.h>
24 #include <linux/mtd/bbm.h>
27 struct nand_flash_dev;
30 /* Scan and identify a NAND device */
31 int nand_scan(struct mtd_info *mtd, int max_chips);
33 * Separate phases of nand_scan(), allowing board driver to intervene
34 * and override command or ECC setup according to flash type.
36 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
37 struct nand_flash_dev *table);
38 int nand_scan_tail(struct mtd_info *mtd);
40 /* Free resources held by the NAND device */
41 void nand_release(struct mtd_info *mtd);
43 /* Internal helper for board drivers which need to override command function */
44 void nand_wait_ready(struct mtd_info *mtd);
47 * This constant declares the max. oobsize / page, which
48 * is supported now. If you add a chip with bigger oobsize/page
49 * adjust this accordingly.
51 #define NAND_MAX_OOBSIZE 1664
52 #define NAND_MAX_PAGESIZE 16384
55 * Constants for hardware specific CLE/ALE/NCE function
57 * These are bits which can be or'ed to set/clear multiple
60 /* Select the chip by setting nCE to low */
62 /* Select the command latch by setting CLE to high */
64 /* Select the address latch by setting ALE to high */
67 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
68 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
69 #define NAND_CTRL_CHANGE 0x80
72 * Standard NAND flash commands
74 #define NAND_CMD_READ0 0
75 #define NAND_CMD_READ1 1
76 #define NAND_CMD_RNDOUT 5
77 #define NAND_CMD_PAGEPROG 0x10
78 #define NAND_CMD_READOOB 0x50
79 #define NAND_CMD_ERASE1 0x60
80 #define NAND_CMD_STATUS 0x70
81 #define NAND_CMD_SEQIN 0x80
82 #define NAND_CMD_RNDIN 0x85
83 #define NAND_CMD_READID 0x90
84 #define NAND_CMD_ERASE2 0xd0
85 #define NAND_CMD_PARAM 0xec
86 #define NAND_CMD_GET_FEATURES 0xee
87 #define NAND_CMD_SET_FEATURES 0xef
88 #define NAND_CMD_RESET 0xff
90 #define NAND_CMD_LOCK 0x2a
91 #define NAND_CMD_UNLOCK1 0x23
92 #define NAND_CMD_UNLOCK2 0x24
94 /* Extended commands for large page devices */
95 #define NAND_CMD_READSTART 0x30
96 #define NAND_CMD_RNDOUTSTART 0xE0
97 #define NAND_CMD_CACHEDPROG 0x15
99 /* Extended commands for AG-AND device */
101 * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
102 * there is no way to distinguish that from NAND_CMD_READ0
103 * until the remaining sequence of commands has been completed
104 * so add a high order bit and mask it off in the command.
106 #define NAND_CMD_DEPLETE1 0x100
107 #define NAND_CMD_DEPLETE2 0x38
108 #define NAND_CMD_STATUS_MULTI 0x71
109 #define NAND_CMD_STATUS_ERROR 0x72
110 /* multi-bank error status (banks 0-3) */
111 #define NAND_CMD_STATUS_ERROR0 0x73
112 #define NAND_CMD_STATUS_ERROR1 0x74
113 #define NAND_CMD_STATUS_ERROR2 0x75
114 #define NAND_CMD_STATUS_ERROR3 0x76
115 #define NAND_CMD_STATUS_RESET 0x7f
116 #define NAND_CMD_STATUS_CLEAR 0xff
118 #define NAND_CMD_NONE -1
121 #define NAND_STATUS_FAIL 0x01
122 #define NAND_STATUS_FAIL_N1 0x02
123 #define NAND_STATUS_TRUE_READY 0x20
124 #define NAND_STATUS_READY 0x40
125 #define NAND_STATUS_WP 0x80
128 * Constants for ECC_MODES
134 NAND_ECC_HW_SYNDROME,
135 NAND_ECC_HW_OOB_FIRST,
140 * Constants for Hardware ECC
142 /* Reset Hardware ECC for read */
143 #define NAND_ECC_READ 0
144 /* Reset Hardware ECC for write */
145 #define NAND_ECC_WRITE 1
146 /* Enable Hardware ECC before syndrome is read back from flash */
147 #define NAND_ECC_READSYN 2
150 * Enable generic NAND 'page erased' check. This check is only done when
151 * ecc.correct() returns -EBADMSG.
152 * Set this flag if your implementation does not fix bitflips in erased
153 * pages and you want to rely on the default implementation.
155 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
156 #define NAND_ECC_MAXIMIZE BIT(1)
158 * If your controller already sends the required NAND commands when
159 * reading or writing a page, then the framework is not supposed to
160 * send READ0 and SEQIN/PAGEPROG respectively.
162 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
164 /* Bit mask for flags passed to do_nand_read_ecc */
165 #define NAND_GET_DEVICE 0x80
169 * Option constants for bizarre disfunctionality and real
172 /* Buswidth is 16 bit */
173 #define NAND_BUSWIDTH_16 0x00000002
174 /* Device supports partial programming without padding */
175 #define NAND_NO_PADDING 0x00000004
176 /* Chip has cache program function */
177 #define NAND_CACHEPRG 0x00000008
178 /* Chip has copy back function */
179 #define NAND_COPYBACK 0x00000010
181 * Chip requires ready check on read (for auto-incremented sequential read).
182 * True only for small page devices; large page devices do not support
185 #define NAND_NEED_READRDY 0x00000100
187 /* Chip does not allow subpage writes */
188 #define NAND_NO_SUBPAGE_WRITE 0x00000200
190 /* Device is one of 'new' xD cards that expose fake nand command set */
191 #define NAND_BROKEN_XD 0x00000400
193 /* Device behaves just like nand, but is readonly */
194 #define NAND_ROM 0x00000800
196 /* Device supports subpage reads */
197 #define NAND_SUBPAGE_READ 0x00001000
200 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
203 #define NAND_NEED_SCRAMBLING 0x00002000
205 /* Options valid for Samsung large page devices */
206 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
208 /* Macros to identify the above */
209 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
210 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
211 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
213 /* Non chip related options */
214 /* This option skips the bbt scan during initialization. */
215 #define NAND_SKIP_BBTSCAN 0x00010000
217 * This option is defined if the board driver allocates its own buffers
218 * (e.g. because it needs them DMA-coherent).
220 #define NAND_OWN_BUFFERS 0x00020000
221 /* Chip may not exist, so silence any errors in scan */
222 #define NAND_SCAN_SILENT_NODEV 0x00040000
224 * Autodetect nand buswidth with readid/onfi.
225 * This suppose the driver will configure the hardware in 8 bits mode
226 * when calling nand_scan_ident, and update its configuration
227 * before calling nand_scan_tail.
229 #define NAND_BUSWIDTH_AUTO 0x00080000
231 * This option could be defined by controller drivers to protect against
232 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
234 #define NAND_USE_BOUNCE_BUFFER 0x00100000
236 /* Options set by nand scan */
237 /* bbt has already been read */
238 #define NAND_BBT_SCANNED 0x40000000
239 /* Nand scan has allocated controller struct */
240 #define NAND_CONTROLLER_ALLOC 0x80000000
242 /* Cell info constants */
243 #define NAND_CI_CHIPNR_MSK 0x03
244 #define NAND_CI_CELLTYPE_MSK 0x0C
245 #define NAND_CI_CELLTYPE_SHIFT 2
251 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
252 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
254 /* ONFI timing mode, used in both asynchronous and synchronous mode */
255 #define ONFI_TIMING_MODE_0 (1 << 0)
256 #define ONFI_TIMING_MODE_1 (1 << 1)
257 #define ONFI_TIMING_MODE_2 (1 << 2)
258 #define ONFI_TIMING_MODE_3 (1 << 3)
259 #define ONFI_TIMING_MODE_4 (1 << 4)
260 #define ONFI_TIMING_MODE_5 (1 << 5)
261 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
263 /* ONFI feature address */
264 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
266 /* Vendor-specific feature address (Micron) */
267 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
269 /* ONFI subfeature parameters length */
270 #define ONFI_SUBFEATURE_PARAM_LEN 4
272 /* ONFI optional commands SET/GET FEATURES supported? */
273 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
275 struct nand_onfi_params {
276 /* rev info and features block */
277 /* 'O' 'N' 'F' 'I' */
283 __le16 ext_param_page_length; /* since ONFI 2.1 */
284 u8 num_of_param_pages; /* since ONFI 2.1 */
287 /* manufacturer information block */
288 char manufacturer[12];
294 /* memory organization block */
295 __le32 byte_per_page;
296 __le16 spare_bytes_per_page;
297 __le32 data_bytes_per_ppage;
298 __le16 spare_bytes_per_ppage;
299 __le32 pages_per_block;
300 __le32 blocks_per_lun;
305 __le16 block_endurance;
306 u8 guaranteed_good_blocks;
307 __le16 guaranteed_block_endurance;
308 u8 programs_per_page;
315 /* electrical parameter block */
316 u8 io_pin_capacitance_max;
317 __le16 async_timing_mode;
318 __le16 program_cache_timing_mode;
323 __le16 src_sync_timing_mode;
324 u8 src_ssync_features;
325 __le16 clk_pin_capacitance_typ;
326 __le16 io_pin_capacitance_typ;
327 __le16 input_pin_capacitance_typ;
328 u8 input_pin_capacitance_max;
329 u8 driver_strength_support;
335 __le16 vendor_revision;
341 #define ONFI_CRC_BASE 0x4F4E
343 /* Extended ECC information Block Definition (since ONFI 2.1) */
344 struct onfi_ext_ecc_info {
348 __le16 block_endurance;
352 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
353 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
354 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
355 struct onfi_ext_section {
360 #define ONFI_EXT_SECTION_MAX 8
362 /* Extended Parameter Page Definition (since ONFI 2.1) */
363 struct onfi_ext_param_page {
365 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
367 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
370 * The actual size of the Extended Parameter Page is in
371 * @ext_param_page_length of nand_onfi_params{}.
372 * The following are the variable length sections.
373 * So we do not add any fields below. Please see the ONFI spec.
377 struct nand_onfi_vendor_micron {
382 u8 dq_imped_num_settings;
383 u8 dq_imped_feat_addr;
384 u8 rb_pulldown_strength;
385 u8 rb_pulldown_strength_feat_addr;
386 u8 rb_pulldown_strength_num_settings;
389 u8 otp_data_prot_addr;
392 u8 read_retry_options;
397 struct jedec_ecc_info {
401 __le16 block_endurance;
406 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
408 struct nand_jedec_params {
409 /* rev info and features block */
410 /* 'J' 'E' 'S' 'D' */
416 u8 num_of_param_pages;
419 /* manufacturer information block */
420 char manufacturer[12];
425 /* memory organization block */
426 __le32 byte_per_page;
427 __le16 spare_bytes_per_page;
429 __le32 pages_per_block;
430 __le32 blocks_per_lun;
434 u8 programs_per_page;
436 u8 multi_plane_op_attr;
439 /* electrical parameter block */
440 __le16 async_sdr_speed_grade;
441 __le16 toggle_ddr_speed_grade;
442 __le16 sync_ddr_speed_grade;
443 u8 async_sdr_features;
444 u8 toggle_ddr_features;
445 u8 sync_ddr_features;
449 __le16 t_r_multi_plane;
451 __le16 io_pin_capacitance_typ;
452 __le16 input_pin_capacitance_typ;
453 __le16 clk_pin_capacitance_typ;
454 u8 driver_strength_support;
458 /* ECC and endurance block */
459 u8 guaranteed_good_blocks;
460 __le16 guaranteed_block_endurance;
461 struct jedec_ecc_info ecc_info[4];
468 __le16 vendor_rev_num;
471 /* CRC for Parameter Page */
476 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
477 * @lock: protection lock
478 * @active: the mtd device which holds the controller currently
479 * @wq: wait queue to sleep on if a NAND operation is in
480 * progress used instead of the per chip wait queue
481 * when a hw controller is available.
483 struct nand_hw_control {
485 struct nand_chip *active;
489 * struct nand_ecc_ctrl - Control structure for ECC
491 * @steps: number of ECC steps per page
492 * @size: data bytes per ECC step
493 * @bytes: ECC bytes per step
494 * @strength: max number of correctible bits per ECC step
495 * @total: total number of ECC bytes per page
496 * @prepad: padding information for syndrome based ECC generators
497 * @postpad: padding information for syndrome based ECC generators
498 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
499 * @layout: ECC layout control struct pointer
500 * @priv: pointer to private ECC control data
501 * @hwctl: function to control hardware ECC generator. Must only
502 * be provided if an hardware ECC is available
503 * @calculate: function for ECC calculation or readback from ECC hardware
504 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
505 * Should return a positive number representing the number of
506 * corrected bitflips, -EBADMSG if the number of bitflips exceed
507 * ECC strength, or any other error code if the error is not
508 * directly related to correction.
509 * If -EBADMSG is returned the input buffers should be left
511 * @read_page_raw: function to read a raw page without ECC. This function
512 * should hide the specific layout used by the ECC
513 * controller and always return contiguous in-band and
514 * out-of-band data even if they're not stored
515 * contiguously on the NAND chip (e.g.
516 * NAND_ECC_HW_SYNDROME interleaves in-band and
518 * @write_page_raw: function to write a raw page without ECC. This function
519 * should hide the specific layout used by the ECC
520 * controller and consider the passed data as contiguous
521 * in-band and out-of-band data. ECC controller is
522 * responsible for doing the appropriate transformations
523 * to adapt to its specific layout (e.g.
524 * NAND_ECC_HW_SYNDROME interleaves in-band and
526 * @read_page: function to read a page according to the ECC generator
527 * requirements; returns maximum number of bitflips corrected in
528 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
529 * @read_subpage: function to read parts of the page covered by ECC;
530 * returns same as read_page()
531 * @write_subpage: function to write parts of the page covered by ECC.
532 * @write_page: function to write a page according to the ECC generator
534 * @write_oob_raw: function to write chip OOB data without ECC
535 * @read_oob_raw: function to read chip OOB data without ECC
536 * @read_oob: function to read chip OOB data
537 * @write_oob: function to write chip OOB data
539 struct nand_ecc_ctrl {
540 nand_ecc_modes_t mode;
548 unsigned int options;
549 struct nand_ecclayout *layout;
551 void (*hwctl)(struct mtd_info *mtd, int mode);
552 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
554 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
556 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
557 uint8_t *buf, int oob_required, int page);
558 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
559 const uint8_t *buf, int oob_required, int page);
560 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
561 uint8_t *buf, int oob_required, int page);
562 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
563 uint32_t offs, uint32_t len, uint8_t *buf, int page);
564 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
565 uint32_t offset, uint32_t data_len,
566 const uint8_t *data_buf, int oob_required, int page);
567 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
568 const uint8_t *buf, int oob_required, int page);
569 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
571 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
573 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
574 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
578 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
580 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
584 * struct nand_buffers - buffer structure for read/write
585 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
586 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
587 * @databuf: buffer pointer for data, size is (page size + oobsize).
589 * Do not change the order of buffers. databuf and oobrbuf must be in
592 struct nand_buffers {
593 uint8_t ecccalc[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
594 uint8_t ecccode[ALIGN(NAND_MAX_OOBSIZE, ARCH_DMA_MINALIGN)];
595 uint8_t databuf[ALIGN(NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE,
600 * struct nand_sdr_timings - SDR NAND chip timings
602 * This struct defines the timing requirements of a SDR NAND chip.
603 * These information can be found in every NAND datasheets and the timings
604 * meaning are described in the ONFI specifications:
605 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
608 * All these timings are expressed in picoseconds.
610 * @tBERS_max: Block erase time
611 * @tCCS_min: Change column setup time
612 * @tPROG_max: Page program time
613 * @tR_max: Page read time
614 * @tALH_min: ALE hold time
615 * @tADL_min: ALE to data loading time
616 * @tALS_min: ALE setup time
617 * @tAR_min: ALE to RE# delay
618 * @tCEA_max: CE# access time
619 * @tCEH_min: CE# high hold time
620 * @tCH_min: CE# hold time
621 * @tCHZ_max: CE# high to output hi-Z
622 * @tCLH_min: CLE hold time
623 * @tCLR_min: CLE to RE# delay
624 * @tCLS_min: CLE setup time
625 * @tCOH_min: CE# high to output hold
626 * @tCS_min: CE# setup time
627 * @tDH_min: Data hold time
628 * @tDS_min: Data setup time
629 * @tFEAT_max: Busy time for Set Features and Get Features
630 * @tIR_min: Output hi-Z to RE# low
631 * @tITC_max: Interface and Timing Mode Change time
632 * @tRC_min: RE# cycle time
633 * @tREA_max: RE# access time
634 * @tREH_min: RE# high hold time
635 * @tRHOH_min: RE# high to output hold
636 * @tRHW_min: RE# high to WE# low
637 * @tRHZ_max: RE# high to output hi-Z
638 * @tRLOH_min: RE# low to output hold
639 * @tRP_min: RE# pulse width
640 * @tRR_min: Ready to RE# low (data only)
641 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
642 * rising edge of R/B#.
643 * @tWB_max: WE# high to SR[6] low
644 * @tWC_min: WE# cycle time
645 * @tWH_min: WE# high hold time
646 * @tWHR_min: WE# high to RE# low
647 * @tWP_min: WE# pulse width
648 * @tWW_min: WP# transition to WE# low
650 struct nand_sdr_timings {
692 * enum nand_data_interface_type - NAND interface timing type
693 * @NAND_SDR_IFACE: Single Data Rate interface
695 enum nand_data_interface_type {
700 * struct nand_data_interface - NAND interface timing
701 * @type: type of the timing
702 * @timings: The timing, type according to @type
704 struct nand_data_interface {
705 enum nand_data_interface_type type;
707 struct nand_sdr_timings sdr;
712 * nand_get_sdr_timings - get SDR timing from data interface
713 * @conf: The data interface
715 static inline const struct nand_sdr_timings *
716 nand_get_sdr_timings(const struct nand_data_interface *conf)
718 if (conf->type != NAND_SDR_IFACE)
719 return ERR_PTR(-EINVAL);
721 return &conf->timings.sdr;
725 * struct nand_chip - NAND Private Flash Chip Data
726 * @mtd: MTD device registered to the MTD framework
727 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
729 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
731 * @flash_node: [BOARDSPECIFIC] device node describing this instance
732 * @read_byte: [REPLACEABLE] read one byte from the chip
733 * @read_word: [REPLACEABLE] read one word from the chip
734 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
736 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
737 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
738 * @select_chip: [REPLACEABLE] select chip nr
739 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
740 * @block_markbad: [REPLACEABLE] mark a block bad
741 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
742 * ALE/CLE/nCE. Also used to write command and address
743 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
744 * device ready/busy line. If set to NULL no access to
745 * ready/busy is available and the ready/busy information
746 * is read from the chip status register.
747 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
748 * commands to the chip.
749 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
751 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
752 * setting the read-retry mode. Mostly needed for MLC NAND.
753 * @ecc: [BOARDSPECIFIC] ECC control structure
754 * @buffers: buffer structure for read/write
755 * @hwcontrol: platform-specific hardware control structure
756 * @erase: [REPLACEABLE] erase function
757 * @scan_bbt: [REPLACEABLE] function to scan bad block table
758 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
759 * data from array to read regs (tR).
760 * @state: [INTERN] the current state of the NAND device
761 * @oob_poi: "poison value buffer," used for laying out OOB data
763 * @page_shift: [INTERN] number of address bits in a page (column
765 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
766 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
767 * @chip_shift: [INTERN] number of address bits in one chip
768 * @options: [BOARDSPECIFIC] various chip options. They can partly
769 * be set to inform nand_scan about special functionality.
770 * See the defines for further explanation.
771 * @bbt_options: [INTERN] bad block specific options. All options used
772 * here must come from bbm.h. By default, these options
773 * will be copied to the appropriate nand_bbt_descr's.
774 * @badblockpos: [INTERN] position of the bad block marker in the oob
776 * @badblockbits: [INTERN] minimum number of set bits in a good block's
777 * bad block marker position; i.e., BBM == 11110111b is
778 * not bad when badblockbits == 7
779 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
780 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
781 * Minimum amount of bit errors per @ecc_step_ds guaranteed
782 * to be correctable. If unknown, set to zero.
783 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
784 * also from the datasheet. It is the recommended ECC step
785 * size, if known; if unknown, set to zero.
786 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
787 * set to the actually used ONFI mode if the chip is
788 * ONFI compliant or deduced from the datasheet if
789 * the NAND chip is not ONFI compliant.
790 * @numchips: [INTERN] number of physical chips
791 * @chipsize: [INTERN] the size of one chip for multichip arrays
792 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
793 * @pagebuf: [INTERN] holds the pagenumber which is currently in
795 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
796 * currently in data_buf.
797 * @subpagesize: [INTERN] holds the subpagesize
798 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
799 * non 0 if ONFI supported.
800 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
801 * non 0 if JEDEC supported.
802 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
803 * supported, 0 otherwise.
804 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
805 * supported, 0 otherwise.
806 * @read_retries: [INTERN] the number of read retry modes supported
807 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
808 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
809 * @setup_data_interface: [OPTIONAL] setup the data interface and timing
810 * @bbt: [INTERN] bad block table pointer
811 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
813 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
814 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
816 * @controller: [REPLACEABLE] a pointer to a hardware controller
817 * structure which is shared among multiple independent
819 * @priv: [OPTIONAL] pointer to private chip data
820 * @errstat: [OPTIONAL] hardware specific function to perform
821 * additional error status checks (determine if errors are
823 * @write_page: [REPLACEABLE] High-level page write function
828 void __iomem *IO_ADDR_R;
829 void __iomem *IO_ADDR_W;
833 uint8_t (*read_byte)(struct mtd_info *mtd);
834 u16 (*read_word)(struct mtd_info *mtd);
835 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
836 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
837 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
838 void (*select_chip)(struct mtd_info *mtd, int chip);
839 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
840 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
841 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
842 int (*dev_ready)(struct mtd_info *mtd);
843 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
845 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
846 int (*erase)(struct mtd_info *mtd, int page);
847 int (*scan_bbt)(struct mtd_info *mtd);
848 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
849 int status, int page);
850 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
851 uint32_t offset, int data_len, const uint8_t *buf,
852 int oob_required, int page, int cached, int raw);
853 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
854 int feature_addr, uint8_t *subfeature_para);
855 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
856 int feature_addr, uint8_t *subfeature_para);
857 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
858 int (*setup_data_interface)(struct mtd_info *mtd,
859 const struct nand_data_interface *conf,
864 unsigned int options;
865 unsigned int bbt_options;
868 int phys_erase_shift;
875 unsigned int pagebuf_bitflips;
877 uint8_t bits_per_cell;
878 uint16_t ecc_strength_ds;
879 uint16_t ecc_step_ds;
880 int onfi_timing_mode_default;
886 struct nand_onfi_params onfi_params;
887 struct nand_jedec_params jedec_params;
889 struct nand_data_interface *data_interface;
896 struct nand_hw_control *controller;
897 struct nand_ecclayout *ecclayout;
899 struct nand_ecc_ctrl ecc;
900 struct nand_buffers *buffers;
901 struct nand_hw_control hwcontrol;
904 struct nand_bbt_descr *bbt_td;
905 struct nand_bbt_descr *bbt_md;
907 struct nand_bbt_descr *badblock_pattern;
912 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
914 return container_of(mtd, struct nand_chip, mtd);
917 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
922 static inline void *nand_get_controller_data(struct nand_chip *chip)
927 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
933 * NAND Flash Manufacturer ID Codes
935 #define NAND_MFR_TOSHIBA 0x98
936 #define NAND_MFR_SAMSUNG 0xec
937 #define NAND_MFR_FUJITSU 0x04
938 #define NAND_MFR_NATIONAL 0x8f
939 #define NAND_MFR_RENESAS 0x07
940 #define NAND_MFR_STMICRO 0x20
941 #define NAND_MFR_HYNIX 0xad
942 #define NAND_MFR_MICRON 0x2c
943 #define NAND_MFR_AMD 0x01
944 #define NAND_MFR_MACRONIX 0xc2
945 #define NAND_MFR_EON 0x92
946 #define NAND_MFR_SANDISK 0x45
947 #define NAND_MFR_INTEL 0x89
948 #define NAND_MFR_ATO 0x9b
950 /* The maximum expected count of bytes in the NAND ID sequence */
951 #define NAND_MAX_ID_LEN 8
954 * A helper for defining older NAND chips where the second ID byte fully
955 * defined the chip, including the geometry (chip size, eraseblock size, page
956 * size). All these chips have 512 bytes NAND page size.
958 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
959 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
960 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
963 * A helper for defining newer chips which report their page size and
964 * eraseblock size via the extended ID bytes.
966 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
967 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
968 * device ID now only represented a particular total chip size (and voltage,
969 * buswidth), and the page size, eraseblock size, and OOB size could vary while
970 * using the same device ID.
972 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
973 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
976 #define NAND_ECC_INFO(_strength, _step) \
977 { .strength_ds = (_strength), .step_ds = (_step) }
978 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
979 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
982 * struct nand_flash_dev - NAND Flash Device ID Structure
983 * @name: a human-readable name of the NAND chip
984 * @dev_id: the device ID (the second byte of the full chip ID array)
985 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
986 * memory address as @id[0])
987 * @dev_id: device ID part of the full chip ID array (refers the same memory
989 * @id: full device ID array
990 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
991 * well as the eraseblock size) is determined from the extended NAND
993 * @chipsize: total chip size in MiB
994 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
995 * @options: stores various chip bit options
996 * @id_len: The valid length of the @id.
998 * @ecc: ECC correctability and step information from the datasheet.
999 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1000 * @ecc_strength_ds in nand_chip{}.
1001 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1002 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1003 * For example, the "4bit ECC for each 512Byte" can be set with
1004 * NAND_ECC_INFO(4, 512).
1005 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1006 * reset. Should be deduced from timings described
1010 struct nand_flash_dev {
1017 uint8_t id[NAND_MAX_ID_LEN];
1019 unsigned int pagesize;
1020 unsigned int chipsize;
1021 unsigned int erasesize;
1022 unsigned int options;
1026 uint16_t strength_ds;
1029 int onfi_timing_mode_default;
1033 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
1034 * @name: Manufacturer name
1035 * @id: manufacturer ID code of device.
1037 struct nand_manufacturers {
1042 extern struct nand_flash_dev nand_flash_ids[];
1043 extern struct nand_manufacturers nand_manuf_ids[];
1045 int nand_default_bbt(struct mtd_info *mtd);
1046 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1047 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1048 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1049 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1051 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1052 size_t *retlen, uint8_t *buf);
1055 * Constants for oob configuration
1057 #define NAND_SMALL_BADBLOCK_POS 5
1058 #define NAND_LARGE_BADBLOCK_POS 0
1061 * struct platform_nand_chip - chip level device structure
1062 * @nr_chips: max. number of chips to scan for
1063 * @chip_offset: chip number offset
1064 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1065 * @partitions: mtd partition list
1066 * @chip_delay: R/B delay value in us
1067 * @options: Option flags, e.g. 16bit buswidth
1068 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1069 * @part_probe_types: NULL-terminated array of probe types
1071 struct platform_nand_chip {
1075 struct mtd_partition *partitions;
1077 unsigned int options;
1078 unsigned int bbt_options;
1079 const char **part_probe_types;
1082 /* Keep gcc happy */
1083 struct platform_device;
1086 * struct platform_nand_ctrl - controller level device structure
1087 * @probe: platform specific function to probe/setup hardware
1088 * @remove: platform specific function to remove/teardown hardware
1089 * @hwcontrol: platform specific hardware control structure
1090 * @dev_ready: platform specific function to read ready/busy pin
1091 * @select_chip: platform specific chip select function
1092 * @cmd_ctrl: platform specific function for controlling
1093 * ALE/CLE/nCE. Also used to write command and address
1094 * @write_buf: platform specific function for write buffer
1095 * @read_buf: platform specific function for read buffer
1096 * @read_byte: platform specific function to read one byte from chip
1097 * @priv: private data to transport driver specific settings
1099 * All fields are optional and depend on the hardware driver requirements
1101 struct platform_nand_ctrl {
1102 int (*probe)(struct platform_device *pdev);
1103 void (*remove)(struct platform_device *pdev);
1104 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1105 int (*dev_ready)(struct mtd_info *mtd);
1106 void (*select_chip)(struct mtd_info *mtd, int chip);
1107 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1108 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1109 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1110 unsigned char (*read_byte)(struct mtd_info *mtd);
1115 * struct platform_nand_data - container structure for platform-specific data
1116 * @chip: chip level chip structure
1117 * @ctrl: controller level device structure
1119 struct platform_nand_data {
1120 struct platform_nand_chip chip;
1121 struct platform_nand_ctrl ctrl;
1124 #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
1125 /* return the supported features. */
1126 static inline int onfi_feature(struct nand_chip *chip)
1128 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1131 /* return the supported asynchronous timing mode. */
1132 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1134 if (!chip->onfi_version)
1135 return ONFI_TIMING_MODE_UNKNOWN;
1136 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1139 /* return the supported synchronous timing mode. */
1140 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1142 if (!chip->onfi_version)
1143 return ONFI_TIMING_MODE_UNKNOWN;
1144 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1147 static inline int onfi_feature(struct nand_chip *chip)
1152 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1154 return ONFI_TIMING_MODE_UNKNOWN;
1157 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1159 return ONFI_TIMING_MODE_UNKNOWN;
1163 int onfi_init_data_interface(struct nand_chip *chip,
1164 struct nand_data_interface *iface,
1165 enum nand_data_interface_type type,
1169 * Check if it is a SLC nand.
1170 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1171 * We do not distinguish the MLC and TLC now.
1173 static inline bool nand_is_slc(struct nand_chip *chip)
1175 return chip->bits_per_cell == 1;
1179 * Check if the opcode's address should be sent only on the lower 8 bits
1180 * @command: opcode to check
1182 static inline int nand_opcode_8bits(unsigned int command)
1185 case NAND_CMD_READID:
1186 case NAND_CMD_PARAM:
1187 case NAND_CMD_GET_FEATURES:
1188 case NAND_CMD_SET_FEATURES:
1196 /* return the supported JEDEC features. */
1197 static inline int jedec_feature(struct nand_chip *chip)
1199 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1203 /* Standard NAND functions from nand_base.c */
1204 void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
1205 void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len);
1206 void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
1207 void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len);
1208 uint8_t nand_read_byte(struct mtd_info *mtd);
1210 /* get timing characteristics from ONFI timing mode. */
1211 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1212 /* get data interface from ONFI timing mode 0, used after reset. */
1213 const struct nand_data_interface *nand_get_default_data_interface(void);
1215 int nand_check_erased_ecc_chunk(void *data, int datalen,
1216 void *ecc, int ecclen,
1217 void *extraoob, int extraooblen,
1220 /* Reset and initialize a NAND device */
1221 int nand_reset(struct nand_chip *chip, int chipnr);
1223 #endif /* __LINUX_MTD_NAND_H */