2 * Copyright 2015-2016 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
11 #define TMU_VERSION (TMU_CSR_BASE_ADDR + 0x000)
12 #define TMU_INQ_WATERMARK (TMU_CSR_BASE_ADDR + 0x004)
13 #define TMU_PHY_INQ_PKTPTR (TMU_CSR_BASE_ADDR + 0x008)
14 #define TMU_PHY_INQ_PKTINFO (TMU_CSR_BASE_ADDR + 0x00c)
15 #define TMU_PHY_INQ_FIFO_CNT (TMU_CSR_BASE_ADDR + 0x010)
16 #define TMU_SYS_GENERIC_CONTROL (TMU_CSR_BASE_ADDR + 0x014)
17 #define TMU_SYS_GENERIC_STATUS (TMU_CSR_BASE_ADDR + 0x018)
18 #define TMU_SYS_GEN_CON0 (TMU_CSR_BASE_ADDR + 0x01c)
19 #define TMU_SYS_GEN_CON1 (TMU_CSR_BASE_ADDR + 0x020)
20 #define TMU_SYS_GEN_CON2 (TMU_CSR_BASE_ADDR + 0x024)
21 #define TMU_SYS_GEN_CON3 (TMU_CSR_BASE_ADDR + 0x028)
22 #define TMU_SYS_GEN_CON4 (TMU_CSR_BASE_ADDR + 0x02c)
23 #define TMU_TEQ_DISABLE_DROPCHK (TMU_CSR_BASE_ADDR + 0x030)
24 #define TMU_TEQ_CTRL (TMU_CSR_BASE_ADDR + 0x034)
25 #define TMU_TEQ_QCFG (TMU_CSR_BASE_ADDR + 0x038)
26 #define TMU_TEQ_DROP_STAT (TMU_CSR_BASE_ADDR + 0x03c)
27 #define TMU_TEQ_QAVG (TMU_CSR_BASE_ADDR + 0x040)
28 #define TMU_TEQ_WREG_PROB (TMU_CSR_BASE_ADDR + 0x044)
29 #define TMU_TEQ_TRANS_STAT (TMU_CSR_BASE_ADDR + 0x048)
30 #define TMU_TEQ_HW_PROB_CFG0 (TMU_CSR_BASE_ADDR + 0x04c)
31 #define TMU_TEQ_HW_PROB_CFG1 (TMU_CSR_BASE_ADDR + 0x050)
32 #define TMU_TEQ_HW_PROB_CFG2 (TMU_CSR_BASE_ADDR + 0x054)
33 #define TMU_TEQ_HW_PROB_CFG3 (TMU_CSR_BASE_ADDR + 0x058)
34 #define TMU_TEQ_HW_PROB_CFG4 (TMU_CSR_BASE_ADDR + 0x05c)
35 #define TMU_TEQ_HW_PROB_CFG5 (TMU_CSR_BASE_ADDR + 0x060)
36 #define TMU_TEQ_HW_PROB_CFG6 (TMU_CSR_BASE_ADDR + 0x064)
37 #define TMU_TEQ_HW_PROB_CFG7 (TMU_CSR_BASE_ADDR + 0x068)
38 #define TMU_TEQ_HW_PROB_CFG8 (TMU_CSR_BASE_ADDR + 0x06c)
39 #define TMU_TEQ_HW_PROB_CFG9 (TMU_CSR_BASE_ADDR + 0x070)
40 #define TMU_TEQ_HW_PROB_CFG10 (TMU_CSR_BASE_ADDR + 0x074)
41 #define TMU_TEQ_HW_PROB_CFG11 (TMU_CSR_BASE_ADDR + 0x078)
42 #define TMU_TEQ_HW_PROB_CFG12 (TMU_CSR_BASE_ADDR + 0x07c)
43 #define TMU_TEQ_HW_PROB_CFG13 (TMU_CSR_BASE_ADDR + 0x080)
44 #define TMU_TEQ_HW_PROB_CFG14 (TMU_CSR_BASE_ADDR + 0x084)
45 #define TMU_TEQ_HW_PROB_CFG15 (TMU_CSR_BASE_ADDR + 0x088)
46 #define TMU_TEQ_HW_PROB_CFG16 (TMU_CSR_BASE_ADDR + 0x08c)
47 #define TMU_TEQ_HW_PROB_CFG17 (TMU_CSR_BASE_ADDR + 0x090)
48 #define TMU_TEQ_HW_PROB_CFG18 (TMU_CSR_BASE_ADDR + 0x094)
49 #define TMU_TEQ_HW_PROB_CFG19 (TMU_CSR_BASE_ADDR + 0x098)
50 #define TMU_TEQ_HW_PROB_CFG20 (TMU_CSR_BASE_ADDR + 0x09c)
51 #define TMU_TEQ_HW_PROB_CFG21 (TMU_CSR_BASE_ADDR + 0x0a0)
52 #define TMU_TEQ_HW_PROB_CFG22 (TMU_CSR_BASE_ADDR + 0x0a4)
53 #define TMU_TEQ_HW_PROB_CFG23 (TMU_CSR_BASE_ADDR + 0x0a8)
54 #define TMU_TEQ_HW_PROB_CFG24 (TMU_CSR_BASE_ADDR + 0x0ac)
55 #define TMU_TEQ_HW_PROB_CFG25 (TMU_CSR_BASE_ADDR + 0x0b0)
56 #define TMU_TDQ_IIFG_CFG (TMU_CSR_BASE_ADDR + 0x0b4)
57 /* [9:0] Scheduler Enable for each of the scheduler in the TDQ.
58 * This is a global Enable for all schedulers in PHY0
60 #define TMU_TDQ0_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x0b8)
61 #define TMU_LLM_CTRL (TMU_CSR_BASE_ADDR + 0x0bc)
62 #define TMU_LLM_BASE_ADDR (TMU_CSR_BASE_ADDR + 0x0c0)
63 #define TMU_LLM_QUE_LEN (TMU_CSR_BASE_ADDR + 0x0c4)
64 #define TMU_LLM_QUE_HEADPTR (TMU_CSR_BASE_ADDR + 0x0c8)
65 #define TMU_LLM_QUE_TAILPTR (TMU_CSR_BASE_ADDR + 0x0cc)
66 #define TMU_LLM_QUE_DROPCNT (TMU_CSR_BASE_ADDR + 0x0d0)
67 #define TMU_INT_EN (TMU_CSR_BASE_ADDR + 0x0d4)
68 #define TMU_INT_SRC (TMU_CSR_BASE_ADDR + 0x0d8)
69 #define TMU_INQ_STAT (TMU_CSR_BASE_ADDR + 0x0dc)
70 #define TMU_CTRL (TMU_CSR_BASE_ADDR + 0x0e0)
72 /* [31] Mem Access Command. 0 = Internal Memory Read, 1 = Internal
73 * memory Write [27:24] Byte Enables of the Internal memory access [23:0]
74 * Address of the internal memory. This address is used to access both the
75 * PM and DM of all the PE's
77 #define TMU_MEM_ACCESS_ADDR (TMU_CSR_BASE_ADDR + 0x0e4)
79 /* Internal Memory Access Write Data */
80 #define TMU_MEM_ACCESS_WDATA (TMU_CSR_BASE_ADDR + 0x0e8)
81 /* Internal Memory Access Read Data. The commands are blocked at the
84 #define TMU_MEM_ACCESS_RDATA (TMU_CSR_BASE_ADDR + 0x0ec)
86 /* [31:0] PHY0 in queue address (must be initialized with one of the
87 * xxx_INQ_PKTPTR cbus addresses)
89 #define TMU_PHY0_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f0)
90 /* [31:0] PHY1 in queue address (must be initialized with one of the
91 * xxx_INQ_PKTPTR cbus addresses)
93 #define TMU_PHY1_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0f4)
94 /* [31:0] PHY3 in queue address (must be initialized with one of the
95 * xxx_INQ_PKTPTR cbus addresses)
97 #define TMU_PHY3_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x0fc)
98 #define TMU_BMU_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x100)
99 #define TMU_TX_CTRL (TMU_CSR_BASE_ADDR + 0x104)
101 #define TMU_PE_SYS_CLK_RATIO (TMU_CSR_BASE_ADDR + 0x114)
102 #define TMU_PE_STATUS (TMU_CSR_BASE_ADDR + 0x118)
103 #define TMU_TEQ_MAX_THRESHOLD (TMU_CSR_BASE_ADDR + 0x11c)
105 /* [31:0] PHY4 in queue address (must be initialized with one of the
106 * xxx_INQ_PKTPTR cbus addresses)
108 #define TMU_PHY4_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x134)
110 /* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
111 * is a global Enable for all schedulers in PHY1
113 #define TMU_TDQ1_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x138)
114 /* [9:0] Scheduler Enable for each of the scheduler in the TDQ. This
115 * is a global Enable for all schedulers in PHY3
117 #define TMU_TDQ3_SCH_CTRL (TMU_CSR_BASE_ADDR + 0x140)
119 #define TMU_BMU_BUF_SIZE (TMU_CSR_BASE_ADDR + 0x144)
120 /* [31:0] PHY5 in queue address (must be initialized with one of the
121 * xxx_INQ_PKTPTR cbus addresses)
123 #define TMU_PHY5_INQ_ADDR (TMU_CSR_BASE_ADDR + 0x148)
125 #define TMU_AXI_CTRL (TMU_CSR_BASE_ADDR + 0x17c)
127 #define SW_RESET BIT(0) /* Global software reset */
128 #define INQ_RESET BIT(2)
129 #define TEQ_RESET BIT(3)
130 #define TDQ_RESET BIT(4)
131 #define PE_RESET BIT(5)
132 #define MEM_INIT BIT(6)
133 #define MEM_INIT_DONE BIT(7)
134 #define LLM_INIT BIT(8)
135 #define LLM_INIT_DONE BIT(9)
136 #define ECC_MEM_INIT_DONE BIT(10)
143 /* Not HW related for pfe_ctrl/pfe common defines */
144 #define DEFAULT_MAX_QDEPTH 80
145 #define DEFAULT_Q0_QDEPTH 511 /* We keep 1 large queue for host tx qos */
146 #define DEFAULT_TMU3_QDEPTH 127
148 #endif /* _TMU_CSR_H_ */