2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
7 #ifndef __PMIC_STPMU1_H_
8 #define __PMIC_STPMU1_H_
10 #define STPMU1_MASK_RESET_BUCK 0x18
11 #define STPMU1_BUCKX_CTRL_REG(buck) (0x20 + (buck))
12 #define STPMU1_VREF_CTRL_REG 0x24
13 #define STPMU1_LDOX_CTRL_REG(ldo) (0x25 + (ldo))
14 #define STPMU1_USB_CTRL_REG 0x40
15 #define STPMU1_NVM_USER_STATUS_REG 0xb8
16 #define STPMU1_NVM_USER_CONTROL_REG 0xb9
18 #define STPMU1_MASK_RESET_BUCK3 BIT(2)
20 #define STPMU1_BUCK_EN BIT(0)
21 #define STPMU1_BUCK_MODE BIT(1)
22 #define STPMU1_BUCK_OUTPUT_MASK GENMASK(7, 2)
23 #define STPMU1_BUCK_OUTPUT_SHIFT 2
24 #define STPMU1_BUCK2_1200000V (24 << STPMU1_BUCK_OUTPUT_SHIFT)
25 #define STPMU1_BUCK2_1350000V (30 << STPMU1_BUCK_OUTPUT_SHIFT)
26 #define STPMU1_BUCK3_1800000V (39 << STPMU1_BUCK_OUTPUT_SHIFT)
28 #define STPMU1_VREF_EN BIT(0)
30 #define STPMU1_LDO_EN BIT(0)
31 #define STPMU1_LDO12356_OUTPUT_MASK GENMASK(6, 2)
32 #define STPMU1_LDO12356_OUTPUT_SHIFT 2
33 #define STPMU1_LDO3_MODE BIT(7)
34 #define STPMU1_LDO3_DDR_SEL 31
35 #define STPMU1_LDO3_1800000 (9 << STPMU1_LDO12356_OUTPUT_SHIFT)
36 #define STPMU1_LDO4_UV 3300000
38 #define STPMU1_USB_BOOST_EN BIT(0)
39 #define STPMU1_USB_PWR_SW_EN GENMASK(2, 1)
41 #define STPMU1_NVM_USER_CONTROL_PROGRAM BIT(0)
42 #define STPMU1_NVM_USER_CONTROL_READ BIT(1)
44 #define STPMU1_NVM_USER_STATUS_BUSY BIT(0)
45 #define STPMU1_NVM_USER_STATUS_ERROR BIT(1)
47 #define STPMU1_DEFAULT_START_UP_DELAY_MS 1
48 #define STPMU1_USB_BOOST_START_UP_DELAY_MS 10
74 STPMU1_LDO_MODE_NORMAL,
75 STPMU1_LDO_MODE_BYPASS,
76 STPMU1_LDO_MODE_SINK_SOURCE,