2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
13 * Supports: IT8603E Super I/O chip w/LPC interface
14 * IT8607E Super I/O chip w/LPC interface
15 * IT8613E Super I/O chip w/LPC interface
16 * IT8620E Super I/O chip w/LPC interface
17 * IT8622E Super I/O chip w/LPC interface
18 * IT8623E Super I/O chip w/LPC interface
19 * IT8625E Super I/O chip w/LPC interface
20 * IT8628E Super I/O chip w/LPC interface
21 * IT8655E Super I/O chip w/LPC interface
22 * IT8665E Super I/O chip w/LPC interface
23 * IT8686E Super I/O chip w/LPC interface
24 * IT8705F Super I/O chip w/LPC interface
25 * IT8712F Super I/O chip w/LPC interface
26 * IT8716F Super I/O chip w/LPC interface
27 * IT8718F Super I/O chip w/LPC interface
28 * IT8720F Super I/O chip w/LPC interface
29 * IT8721F Super I/O chip w/LPC interface
30 * IT8726F Super I/O chip w/LPC interface
31 * IT8728F Super I/O chip w/LPC interface
32 * IT8732F Super I/O chip w/LPC interface
33 * IT8758E Super I/O chip w/LPC interface
34 * IT8771E Super I/O chip w/LPC interface
35 * IT8772E Super I/O chip w/LPC interface
36 * IT8781F Super I/O chip w/LPC interface
37 * IT8782F Super I/O chip w/LPC interface
38 * IT8783E/F Super I/O chip w/LPC interface
39 * IT8786E Super I/O chip w/LPC interface
40 * IT8790E Super I/O chip w/LPC interface
41 * IT8792E Super I/O chip w/LPC interface
42 * Sis950 A clone of the IT8705F
44 * Copyright (C) 2001 Chris Gauthron
45 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
47 * This program is free software; you can redistribute it and/or modify
48 * it under the terms of the GNU General Public License as published by
49 * the Free Software Foundation; either version 2 of the License, or
50 * (at your option) any later version.
52 * This program is distributed in the hope that it will be useful,
53 * but WITHOUT ANY WARRANTY; without even the implied warranty of
54 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
55 * GNU General Public License for more details.
58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
60 #include <linux/bitops.h>
61 #include <linux/module.h>
62 #include <linux/init.h>
63 #include <linux/slab.h>
64 #include <linux/jiffies.h>
65 #include <linux/platform_device.h>
66 #include <linux/hwmon.h>
67 #include <linux/hwmon-sysfs.h>
68 #include <linux/hwmon-vid.h>
69 #include <linux/err.h>
70 #include <linux/mutex.h>
71 #include <linux/sysfs.h>
72 #include <linux/string.h>
73 #include <linux/dmi.h>
74 #include <linux/acpi.h>
79 #define DRVNAME "it87"
81 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
82 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
83 it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
84 it8655, it8665, it8686 };
86 static unsigned short force_id;
87 module_param(force_id, ushort, 0);
88 MODULE_PARM_DESC(force_id, "Override the detected device ID");
90 static bool ignore_resource_conflict;
91 module_param(ignore_resource_conflict, bool, 0);
92 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
94 static struct platform_device *it87_pdev[2];
96 #define REG_2E 0x2e /* The register to read/write */
97 #define REG_4E 0x4e /* Secondary register to read/write */
99 #define DEV 0x07 /* Register: Logical device select */
100 #define PME 0x04 /* The device with the fan registers in it */
102 /* The device with the IT8718F/IT8720F VID value in it */
105 #define DEVID 0x20 /* Register: Device ID */
106 #define DEVREV 0x22 /* Register: Device Revision */
108 static inline void __superio_enter(int ioreg)
113 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
116 static inline int superio_inb(int ioreg, int reg)
121 val = inb(ioreg + 1);
126 static inline void superio_outb(int ioreg, int reg, int val)
129 outb(val, ioreg + 1);
132 static int superio_inw(int ioreg, int reg)
134 return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
137 static inline void superio_select(int ioreg, int ldn)
140 outb(ldn, ioreg + 1);
143 static inline int superio_enter(int ioreg)
146 * Try to reserve ioreg and ioreg + 1 for exclusive access.
148 if (!request_muxed_region(ioreg, 2, DRVNAME))
151 __superio_enter(ioreg);
158 static inline void superio_exit(int ioreg, bool doexit)
162 outb(0x02, ioreg + 1);
164 release_region(ioreg, 2);
167 /* Logical device 4 registers */
168 #define IT8712F_DEVID 0x8712
169 #define IT8705F_DEVID 0x8705
170 #define IT8716F_DEVID 0x8716
171 #define IT8718F_DEVID 0x8718
172 #define IT8720F_DEVID 0x8720
173 #define IT8721F_DEVID 0x8721
174 #define IT8726F_DEVID 0x8726
175 #define IT8728F_DEVID 0x8728
176 #define IT8732F_DEVID 0x8732
177 #define IT8792E_DEVID 0x8733
178 #define IT8771E_DEVID 0x8771
179 #define IT8772E_DEVID 0x8772
180 #define IT8781F_DEVID 0x8781
181 #define IT8782F_DEVID 0x8782
182 #define IT8783E_DEVID 0x8783
183 #define IT8786E_DEVID 0x8786
184 #define IT8790E_DEVID 0x8790
185 #define IT8603E_DEVID 0x8603
186 #define IT8607E_DEVID 0x8607
187 #define IT8613E_DEVID 0x8613
188 #define IT8620E_DEVID 0x8620
189 #define IT8622E_DEVID 0x8622
190 #define IT8623E_DEVID 0x8623
191 #define IT8625E_DEVID 0x8625
192 #define IT8628E_DEVID 0x8628
193 #define IT8655E_DEVID 0x8655
194 #define IT8665E_DEVID 0x8665
195 #define IT8686E_DEVID 0x8686
196 #define IT87_ACT_REG 0x30
197 #define IT87_BASE_REG 0x60
199 /* Logical device 7 registers (IT8712F and later) */
200 #define IT87_SIO_GPIO1_REG 0x25
201 #define IT87_SIO_GPIO2_REG 0x26
202 #define IT87_SIO_GPIO3_REG 0x27
203 #define IT87_SIO_GPIO4_REG 0x28
204 #define IT87_SIO_GPIO5_REG 0x29
205 #define IT87_SIO_GPIO9_REG 0xd3
206 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
207 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
208 #define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
209 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
210 #define IT87_SIO_VID_REG 0xfc /* VID value */
211 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
213 /* Update battery voltage after every reading if true */
214 static bool update_vbat;
216 /* Not all BIOSes properly configure the PWM registers */
217 static bool fix_pwm_polarity;
219 /* Many IT87 constants specified below */
221 /* Length of ISA address segment */
222 #define IT87_EXTENT 8
224 /* Length of ISA address segment for Environmental Controller */
225 #define IT87_EC_EXTENT 2
227 /* Offset of EC registers from ISA base address */
228 #define IT87_EC_OFFSET 5
230 /* Where are the ISA address/data registers relative to the EC base address */
231 #define IT87_ADDR_REG_OFFSET 0
232 #define IT87_DATA_REG_OFFSET 1
234 /*----- The IT87 registers -----*/
236 #define IT87_REG_CONFIG 0x00
238 #define IT87_REG_ALARM1 0x01
239 #define IT87_REG_ALARM2 0x02
240 #define IT87_REG_ALARM3 0x03
242 #define IT87_REG_BANK 0x06
245 * The IT8718F and IT8720F have the VID value in a different register, in
246 * Super-I/O configuration space.
248 #define IT87_REG_VID 0x0a
250 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
251 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
254 #define IT87_REG_FAN_DIV 0x0b
255 #define IT87_REG_FAN_16BIT 0x0c
259 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
260 * - up to 6 temp (1 to 6)
261 * - up to 6 fan (1 to 6)
264 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
265 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
266 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
267 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
269 static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
270 static const u8 IT87_REG_FAN_MIN_8665[] =
271 { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
272 static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
273 static const u8 IT87_REG_FANX_MIN_8665[] =
274 { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
276 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
278 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
280 #define IT87_REG_FAN_MAIN_CTRL 0x13
281 #define IT87_REG_FAN_CTL 0x14
283 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
284 static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
286 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
288 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
289 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
291 #define IT87_REG_TEMP(nr) (0x29 + (nr))
293 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
294 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
296 static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
297 static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
299 static const u8 IT87_REG_TEMP_HIGH_8686[] =
300 { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
301 static const u8 IT87_REG_TEMP_LOW_8686[] =
302 { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
304 #define IT87_REG_VIN_ENABLE 0x50
305 #define IT87_REG_TEMP_ENABLE 0x51
306 #define IT87_REG_TEMP_EXTRA 0x55
307 #define IT87_REG_BEEP_ENABLE 0x5c
309 #define IT87_REG_CHIPID 0x58
311 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
313 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
314 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
316 #define IT87_REG_TEMP456_ENABLE 0x77
318 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
319 #define IT87_REG_TEMP_SRC2 0x23d
321 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
322 #define NUM_VIN_LIMIT 8
324 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
325 #define NUM_FAN_DIV 3
326 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
327 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
329 struct it87_devices {
331 const char * const suffix;
335 u8 num_temp_map; /* Number of temperature sources for pwm */
340 #define FEAT_12MV_ADC BIT(0)
341 #define FEAT_NEWER_AUTOPWM BIT(1)
342 #define FEAT_OLD_AUTOPWM BIT(2)
343 #define FEAT_16BIT_FANS BIT(3)
344 #define FEAT_TEMP_PECI BIT(5)
345 #define FEAT_TEMP_OLD_PECI BIT(6)
346 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
347 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
348 #define FEAT_VID BIT(9) /* Set if chip supports VID */
349 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
350 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
351 #define FEAT_10_9MV_ADC BIT(12)
352 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
353 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
354 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
355 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
356 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
357 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
358 #define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
359 #define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
360 #define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
361 #define FEAT_SCALING BIT(22) /* Internal voltage scaling */
362 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
363 #define FEAT_11MV_ADC BIT(24)
364 #define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
366 static const struct it87_devices it87_devices[] = {
370 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
371 /* may need to overwrite */
373 .num_temp_offset = 0,
379 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
380 /* may need to overwrite */
382 .num_temp_offset = 0,
388 .features = FEAT_16BIT_FANS | FEAT_VID
389 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
392 .num_temp_offset = 3,
398 .features = FEAT_16BIT_FANS | FEAT_VID
399 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
400 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
402 .num_temp_offset = 3,
404 .old_peci_mask = 0x4,
409 .features = FEAT_16BIT_FANS | FEAT_VID
410 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
411 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
413 .num_temp_offset = 3,
415 .old_peci_mask = 0x4,
420 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
421 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
422 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
423 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
425 .num_temp_offset = 3,
428 .old_peci_mask = 0x02, /* Actually reports PCH */
433 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
434 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
435 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
438 .num_temp_offset = 3,
445 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
446 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
447 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
448 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
450 .num_temp_offset = 3,
453 .old_peci_mask = 0x02, /* Actually reports PCH */
458 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
459 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
460 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
461 /* PECI: guesswork */
463 /* 16 bit fans (OHM) */
464 /* three fans, always 16 bit (guesswork) */
466 .num_temp_offset = 3,
473 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
474 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
475 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
476 /* PECI (coreboot) */
477 /* 12mV ADC (HWSensors4, OHM) */
478 /* 16 bit fans (HWSensors4, OHM) */
479 /* three fans, always 16 bit (datasheet) */
481 .num_temp_offset = 3,
488 .features = FEAT_16BIT_FANS
489 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
492 .num_temp_offset = 3,
494 .old_peci_mask = 0x4,
499 .features = FEAT_16BIT_FANS
500 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
503 .num_temp_offset = 3,
505 .old_peci_mask = 0x4,
510 .features = FEAT_16BIT_FANS
511 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
514 .num_temp_offset = 3,
516 .old_peci_mask = 0x4,
521 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
522 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
523 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
525 .num_temp_offset = 3,
532 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
533 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
534 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
536 .num_temp_offset = 3,
543 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
544 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
545 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
547 .num_temp_offset = 3,
554 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
555 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
556 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
558 .num_temp_offset = 3,
565 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
566 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
567 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
570 .num_temp_offset = 3,
577 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
578 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
579 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
580 | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
582 .num_temp_offset = 6,
589 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
590 | FEAT_TEMP_PECI | FEAT_SIX_FANS
591 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
592 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
595 .num_temp_offset = 3,
602 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
603 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
604 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
605 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
607 .num_temp_offset = 3,
614 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
615 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
616 | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
617 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
619 .num_temp_offset = 6,
625 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
626 | FEAT_TEMP_PECI | FEAT_SIX_FANS
627 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
628 | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
631 .num_temp_offset = 3,
638 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
639 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
640 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
642 .num_temp_offset = 6,
648 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
649 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
650 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
651 | FEAT_SIX_PWM | FEAT_BANK_SEL,
653 .num_temp_offset = 6,
659 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
660 | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
661 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
662 | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
664 .num_temp_offset = 6,
669 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
670 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
671 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
672 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
673 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
674 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
675 ((data)->peci_mask & BIT(nr)))
676 #define has_temp_old_peci(data, nr) \
677 (((data)->features & FEAT_TEMP_OLD_PECI) && \
678 ((data)->old_peci_mask & BIT(nr)))
679 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
680 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
682 #define has_vid(data) ((data)->features & FEAT_VID)
683 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
684 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
685 #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
686 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
688 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
689 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
690 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
691 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
692 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
695 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
698 #define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
699 #define has_scaling(data) ((data)->features & FEAT_SCALING)
700 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
701 #define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
702 #define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
704 struct it87_sio_data {
706 /* Values read from Super-I/O config space */
710 u8 internal; /* Internal sensors can be labeled */
711 /* Features skipped based on config or DMI */
720 * For each registered chip, we need to keep some data in memory.
721 * The structure is dynamically allocated.
724 const struct attribute_group *groups[7];
732 const u8 *REG_FAN_MIN;
733 const u8 *REG_FANX_MIN;
737 const u8 *REG_TEMP_OFFSET;
738 const u8 *REG_TEMP_LOW;
739 const u8 *REG_TEMP_HIGH;
743 struct mutex update_lock;
744 char valid; /* !=0 if following fields are valid */
745 unsigned long last_updated; /* In jiffies */
747 u16 in_scaled; /* Internal voltage sensors are scaled */
748 u16 in_internal; /* Bitfield, internal sensors (for labels) */
749 u16 has_in; /* Bitfield, voltage sensors enabled */
750 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
751 u8 has_fan; /* Bitfield, fans enabled */
752 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
753 u8 has_temp; /* Bitfield, temp sensors enabled */
754 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
755 u8 num_temp_limit; /* Number of temperature limit registers */
756 u8 num_temp_offset; /* Number of temperature offset registers */
757 u8 temp_src[4]; /* Up to 4 temperature source registers */
758 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
759 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
760 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
761 bool has_vid; /* True if VID supported */
762 u8 vid; /* Register encoding, combined */
764 u32 alarms; /* Register encoding, combined */
765 bool has_beep; /* true if beep supported */
766 u8 beeps; /* Register encoding */
767 u8 fan_main_ctrl; /* Register value */
768 u8 fan_ctl; /* Register value */
771 * The following 3 arrays correspond to the same registers up to
772 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
773 * 7, and we want to preserve settings on mode changes, so we have
774 * to track all values separately.
775 * Starting with the IT8721F, the manual PWM duty cycles are stored
776 * in separate registers (8-bit values), so the separate tracking
777 * is no longer needed, but it is still done to keep the driver
780 u8 has_pwm; /* Bitfield, pwm control enabled */
781 u8 pwm_ctrl[NUM_PWM]; /* Register value */
782 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
783 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
784 u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */
785 u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */
786 u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */
788 /* Automatic fan speed control registers */
789 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
790 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
793 static int adc_lsb(const struct it87_data *data, int nr)
797 if (has_12mv_adc(data))
799 else if (has_10_9mv_adc(data))
801 else if (has_11mv_adc(data))
805 if (data->in_scaled & BIT(nr))
810 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
812 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
813 return clamp_val(val, 0, 255);
816 static int in_from_reg(const struct it87_data *data, int nr, int val)
818 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
821 static inline u8 FAN_TO_REG(long rpm, int div)
825 rpm = clamp_val(rpm, 1, 1000000);
826 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
829 static inline u16 FAN16_TO_REG(long rpm)
833 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
836 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
837 1350000 / ((val) * (div)))
838 /* The divider is fixed to 2 in 16-bit mode */
839 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
840 1350000 / ((val) * 2))
842 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
843 ((val) + 500) / 1000), -128, 127))
844 #define TEMP_FROM_REG(val) ((val) * 1000)
846 static u8 pwm_to_reg(const struct it87_data *data, long val)
848 if (has_newer_autopwm(data))
854 static int pwm_from_reg(const struct it87_data *data, u8 reg)
856 if (has_newer_autopwm(data))
859 return (reg & 0x7f) << 1;
862 static int DIV_TO_REG(int val)
866 while (answer < 7 && (val >>= 1))
871 #define DIV_FROM_REG(val) BIT(val)
873 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
877 map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
878 if (map >= data->pwm_num_temp_map) /* map is 0-based */
884 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
886 u8 ctrl = data->pwm_ctrl[nr];
888 return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
889 (map << data->pwm_temp_map_shift);
893 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
894 * depending on the chip type, to calculate the actual PWM frequency.
896 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
897 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
898 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
899 * sometimes just one. It is unknown if this is a datasheet error or real,
900 * so this is ignored for now.
902 static const unsigned int pwm_freq[8] = {
913 static int _it87_read_value(struct it87_data *data, u8 reg)
915 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
916 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
919 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
921 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
922 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
925 static u8 it87_set_bank(struct it87_data *data, u8 bank)
929 if (has_bank_sel(data)) {
930 u8 breg = _it87_read_value(data, IT87_REG_BANK);
936 _it87_write_value(data, IT87_REG_BANK, breg);
943 * Must be called with data->update_lock held, except during initialization.
944 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
945 * would slow down the IT87 access and should not be necessary.
947 static int it87_read_value(struct it87_data *data, u16 reg)
952 bank = it87_set_bank(data, reg >> 8);
953 val = _it87_read_value(data, reg & 0xff);
954 it87_set_bank(data, bank);
960 * Must be called with data->update_lock held, except during initialization.
961 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
962 * would slow down the IT87 access and should not be necessary.
964 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
968 bank = it87_set_bank(data, reg >> 8);
969 _it87_write_value(data, reg & 0xff, value);
970 it87_set_bank(data, bank);
973 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
977 ctrl = it87_read_value(data, data->REG_PWM[nr]);
978 data->pwm_ctrl[nr] = ctrl;
979 if (has_newer_autopwm(data)) {
980 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
981 data->pwm_duty[nr] = it87_read_value(data,
982 IT87_REG_PWM_DUTY[nr]);
984 if (ctrl & 0x80) /* Automatic mode */
985 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
986 else /* Manual mode */
987 data->pwm_duty[nr] = ctrl & 0x7f;
990 if (has_old_autopwm(data)) {
993 for (i = 0; i < 5 ; i++)
994 data->auto_temp[nr][i] = it87_read_value(data,
995 IT87_REG_AUTO_TEMP(nr, i));
996 for (i = 0; i < 3 ; i++)
997 data->auto_pwm[nr][i] = it87_read_value(data,
998 IT87_REG_AUTO_PWM(nr, i));
999 } else if (has_newer_autopwm(data)) {
1003 * 0: temperature hysteresis (base + 5)
1004 * 1: fan off temperature (base + 0)
1005 * 2: fan start temperature (base + 1)
1006 * 3: fan max temperature (base + 2)
1008 data->auto_temp[nr][0] =
1009 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
1011 for (i = 0; i < 3 ; i++)
1012 data->auto_temp[nr][i + 1] =
1013 it87_read_value(data,
1014 IT87_REG_AUTO_TEMP(nr, i));
1016 * 0: start pwm value (base + 3)
1017 * 1: pwm slope (base + 4, 1/8th pwm)
1019 data->auto_pwm[nr][0] =
1020 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
1021 data->auto_pwm[nr][1] =
1022 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
1026 static struct it87_data *it87_update_device(struct device *dev)
1028 struct it87_data *data = dev_get_drvdata(dev);
1031 mutex_lock(&data->update_lock);
1033 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1037 * Cleared after each update, so reenable. Value
1038 * returned by this read will be previous value
1040 it87_write_value(data, IT87_REG_CONFIG,
1041 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
1043 for (i = 0; i < NUM_VIN; i++) {
1044 if (!(data->has_in & BIT(i)))
1048 it87_read_value(data, IT87_REG_VIN[i]);
1050 /* VBAT and AVCC don't have limit registers */
1051 if (i >= NUM_VIN_LIMIT)
1055 it87_read_value(data, IT87_REG_VIN_MIN(i));
1057 it87_read_value(data, IT87_REG_VIN_MAX(i));
1060 for (i = 0; i < NUM_FAN; i++) {
1061 /* Skip disabled fans */
1062 if (!(data->has_fan & BIT(i)))
1066 it87_read_value(data, data->REG_FAN_MIN[i]);
1067 data->fan[i][0] = it87_read_value(data,
1069 /* Add high byte if in 16-bit mode */
1070 if (has_16bit_fans(data)) {
1071 data->fan[i][0] |= it87_read_value(data,
1072 data->REG_FANX[i]) << 8;
1073 data->fan[i][1] |= it87_read_value(data,
1074 data->REG_FANX_MIN[i]) << 8;
1077 for (i = 0; i < NUM_TEMP; i++) {
1078 if (!(data->has_temp & BIT(i)))
1081 it87_read_value(data, IT87_REG_TEMP(i));
1083 if (i >= data->num_temp_limit)
1086 if (i < data->num_temp_offset)
1088 it87_read_value(data,
1089 data->REG_TEMP_OFFSET[i]);
1092 it87_read_value(data, data->REG_TEMP_LOW[i]);
1094 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1097 /* Newer chips don't have clock dividers */
1098 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1099 i = it87_read_value(data, IT87_REG_FAN_DIV);
1100 data->fan_div[0] = i & 0x07;
1101 data->fan_div[1] = (i >> 3) & 0x07;
1102 data->fan_div[2] = (i & 0x40) ? 3 : 1;
1106 it87_read_value(data, IT87_REG_ALARM1) |
1107 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1108 (it87_read_value(data, IT87_REG_ALARM3) << 16);
1109 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1111 data->fan_main_ctrl = it87_read_value(data,
1112 IT87_REG_FAN_MAIN_CTRL);
1113 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1114 for (i = 0; i < NUM_PWM; i++) {
1115 if (!(data->has_pwm & BIT(i)))
1117 it87_update_pwm_ctrl(data, i);
1120 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1121 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1123 * The IT8705F does not have VID capability.
1124 * The IT8718F and later don't use IT87_REG_VID for the
1127 if (data->type == it8712 || data->type == it8716) {
1128 data->vid = it87_read_value(data, IT87_REG_VID);
1130 * The older IT8712F revisions had only 5 VID pins,
1131 * but we assume it is always safe to read 6 bits.
1135 data->last_updated = jiffies;
1139 mutex_unlock(&data->update_lock);
1144 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1147 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1148 struct it87_data *data = it87_update_device(dev);
1149 int index = sattr->index;
1152 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1155 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1156 const char *buf, size_t count)
1158 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1159 struct it87_data *data = dev_get_drvdata(dev);
1160 int index = sattr->index;
1164 if (kstrtoul(buf, 10, &val) < 0)
1167 mutex_lock(&data->update_lock);
1168 data->in[nr][index] = in_to_reg(data, nr, val);
1169 it87_write_value(data,
1170 index == 1 ? IT87_REG_VIN_MIN(nr)
1171 : IT87_REG_VIN_MAX(nr),
1172 data->in[nr][index]);
1173 mutex_unlock(&data->update_lock);
1177 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1178 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1180 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1183 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1184 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1186 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1189 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1190 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1192 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1195 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1196 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1198 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1201 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1202 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1204 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1207 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1208 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1210 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1213 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1214 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1216 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1219 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1220 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1222 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1225 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1226 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1227 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1228 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1229 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1231 /* Up to 6 temperatures */
1232 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1235 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1237 int index = sattr->index;
1238 struct it87_data *data = it87_update_device(dev);
1240 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1243 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1244 const char *buf, size_t count)
1246 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1248 int index = sattr->index;
1249 struct it87_data *data = dev_get_drvdata(dev);
1253 if (kstrtol(buf, 10, &val) < 0)
1256 mutex_lock(&data->update_lock);
1261 reg = data->REG_TEMP_LOW[nr];
1264 reg = data->REG_TEMP_HIGH[nr];
1267 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1268 if (!(regval & 0x80)) {
1270 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1273 reg = data->REG_TEMP_OFFSET[nr];
1277 data->temp[nr][index] = TEMP_TO_REG(val);
1278 it87_write_value(data, reg, data->temp[nr][index]);
1279 mutex_unlock(&data->update_lock);
1283 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1284 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1286 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1288 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1290 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1291 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1293 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1295 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1297 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1298 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1300 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1302 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1304 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1305 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1307 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1309 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1311 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1312 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1314 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1316 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1318 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1319 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1321 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1323 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1326 static const u8 temp_types_8686[NUM_TEMP][9] = {
1327 { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1328 { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1329 { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1330 { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1331 { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1332 { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1335 static int get_temp_type(struct it87_data *data, int index)
1340 if (has_bank_sel(data)) {
1343 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1345 switch (data->type) {
1348 type = temp_types_8686[index][src1];
1359 src2 = data->temp_src[3];
1362 type = (src2 & BIT(index)) ? 6 : 5;
1365 type = (src2 & BIT(index)) ? 4 : 6;
1368 type = (src2 & BIT(index)) ? 5 : 0;
1378 if (type || index >= 3)
1381 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1382 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1384 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1385 (has_temp_old_peci(data, index) && (extra & 0x80)))
1386 type = 6; /* Intel PECI */
1387 if (reg & BIT(index))
1388 type = 3; /* thermal diode */
1389 else if (reg & BIT(index + 3))
1390 type = 4; /* thermistor */
1395 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1398 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1399 struct it87_data *data = it87_update_device(dev);
1400 int type = get_temp_type(data, sensor_attr->index);
1402 return sprintf(buf, "%d\n", type);
1405 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1406 const char *buf, size_t count)
1408 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1409 int nr = sensor_attr->index;
1411 struct it87_data *data = dev_get_drvdata(dev);
1415 if (kstrtol(buf, 10, &val) < 0)
1418 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1421 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1423 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1424 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1426 if (val == 2) { /* backwards compatibility */
1428 "Sensor type 2 is deprecated, please use 4 instead\n");
1431 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1436 else if (has_temp_peci(data, nr) && val == 6)
1437 reg |= (nr + 1) << 6;
1438 else if (has_temp_old_peci(data, nr) && val == 6)
1443 mutex_lock(&data->update_lock);
1445 data->extra = extra;
1446 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1447 if (has_temp_old_peci(data, nr))
1448 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1449 data->valid = 0; /* Force cache refresh */
1450 mutex_unlock(&data->update_lock);
1454 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1456 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1458 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1460 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1462 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1464 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1469 static int pwm_mode(const struct it87_data *data, int nr)
1471 if (has_fanctl_onoff(data) && nr < 3 &&
1472 !(data->fan_main_ctrl & BIT(nr)))
1473 return 0; /* Full speed */
1474 if (data->pwm_ctrl[nr] & 0x80)
1475 return 2; /* Automatic mode */
1476 if ((!has_fanctl_onoff(data) || nr >= 3) &&
1477 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1478 return 0; /* Full speed */
1480 return 1; /* Manual mode */
1483 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1486 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1488 int index = sattr->index;
1490 struct it87_data *data = it87_update_device(dev);
1492 speed = has_16bit_fans(data) ?
1493 FAN16_FROM_REG(data->fan[nr][index]) :
1494 FAN_FROM_REG(data->fan[nr][index],
1495 DIV_FROM_REG(data->fan_div[nr]));
1496 return sprintf(buf, "%d\n", speed);
1499 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1502 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1503 struct it87_data *data = it87_update_device(dev);
1504 int nr = sensor_attr->index;
1506 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1509 static ssize_t show_pwm_enable(struct device *dev,
1510 struct device_attribute *attr, char *buf)
1512 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1513 struct it87_data *data = it87_update_device(dev);
1514 int nr = sensor_attr->index;
1516 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1519 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1522 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1523 struct it87_data *data = it87_update_device(dev);
1524 int nr = sensor_attr->index;
1526 return sprintf(buf, "%d\n",
1527 pwm_from_reg(data, data->pwm_duty[nr]));
1530 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1533 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1534 struct it87_data *data = it87_update_device(dev);
1535 int nr = sensor_attr->index;
1539 if (has_pwm_freq2(data) && nr == 1)
1540 index = (data->extra >> 4) & 0x07;
1542 index = (data->fan_ctl >> 4) & 0x07;
1544 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1546 return sprintf(buf, "%u\n", freq);
1549 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1550 const char *buf, size_t count)
1552 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1554 int index = sattr->index;
1556 struct it87_data *data = dev_get_drvdata(dev);
1560 if (kstrtol(buf, 10, &val) < 0)
1563 mutex_lock(&data->update_lock);
1565 if (has_16bit_fans(data)) {
1566 data->fan[nr][index] = FAN16_TO_REG(val);
1567 it87_write_value(data, data->REG_FAN_MIN[nr],
1568 data->fan[nr][index] & 0xff);
1569 it87_write_value(data, data->REG_FANX_MIN[nr],
1570 data->fan[nr][index] >> 8);
1572 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1575 data->fan_div[nr] = reg & 0x07;
1578 data->fan_div[nr] = (reg >> 3) & 0x07;
1581 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1584 data->fan[nr][index] =
1585 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1586 it87_write_value(data, data->REG_FAN_MIN[nr],
1587 data->fan[nr][index]);
1590 mutex_unlock(&data->update_lock);
1594 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1595 const char *buf, size_t count)
1597 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1598 struct it87_data *data = dev_get_drvdata(dev);
1599 int nr = sensor_attr->index;
1604 if (kstrtoul(buf, 10, &val) < 0)
1607 mutex_lock(&data->update_lock);
1608 old = it87_read_value(data, IT87_REG_FAN_DIV);
1610 /* Save fan min limit */
1611 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1616 data->fan_div[nr] = DIV_TO_REG(val);
1620 data->fan_div[nr] = 1;
1622 data->fan_div[nr] = 3;
1625 val |= (data->fan_div[0] & 0x07);
1626 val |= (data->fan_div[1] & 0x07) << 3;
1627 if (data->fan_div[2] == 3)
1629 it87_write_value(data, IT87_REG_FAN_DIV, val);
1631 /* Restore fan min limit */
1632 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1633 it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1635 mutex_unlock(&data->update_lock);
1639 /* Returns 0 if OK, -EINVAL otherwise */
1640 static int check_trip_points(struct device *dev, int nr)
1642 const struct it87_data *data = dev_get_drvdata(dev);
1645 if (has_old_autopwm(data)) {
1646 for (i = 0; i < 3; i++) {
1647 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1650 for (i = 0; i < 2; i++) {
1651 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1654 } else if (has_newer_autopwm(data)) {
1655 for (i = 1; i < 3; i++) {
1656 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1663 "Inconsistent trip points, not switching to automatic mode\n");
1664 dev_err(dev, "Adjust the trip points and try again\n");
1669 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1670 const char *buf, size_t count)
1672 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1673 struct it87_data *data = dev_get_drvdata(dev);
1674 int nr = sensor_attr->index;
1677 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1680 /* Check trip points before switching to automatic mode */
1682 if (check_trip_points(dev, nr) < 0)
1686 mutex_lock(&data->update_lock);
1687 it87_update_pwm_ctrl(data, nr);
1690 if (nr < 3 && has_fanctl_onoff(data)) {
1692 /* make sure the fan is on when in on/off mode */
1693 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1694 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1695 /* set on/off mode */
1696 data->fan_main_ctrl &= ~BIT(nr);
1697 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1698 data->fan_main_ctrl);
1702 /* No on/off mode, set maximum pwm value */
1703 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1704 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1705 data->pwm_duty[nr]);
1706 /* and set manual mode */
1707 if (has_newer_autopwm(data)) {
1708 ctrl = temp_map_to_reg(data, nr,
1709 data->pwm_temp_map[nr]);
1712 ctrl = data->pwm_duty[nr];
1714 data->pwm_ctrl[nr] = ctrl;
1715 it87_write_value(data, data->REG_PWM[nr], ctrl);
1720 if (has_newer_autopwm(data)) {
1721 ctrl = temp_map_to_reg(data, nr,
1722 data->pwm_temp_map[nr]);
1728 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1730 data->pwm_ctrl[nr] = ctrl;
1731 it87_write_value(data, data->REG_PWM[nr], ctrl);
1733 if (has_fanctl_onoff(data) && nr < 3) {
1734 /* set SmartGuardian mode */
1735 data->fan_main_ctrl |= BIT(nr);
1736 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1737 data->fan_main_ctrl);
1741 mutex_unlock(&data->update_lock);
1745 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1746 const char *buf, size_t count)
1748 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1749 struct it87_data *data = dev_get_drvdata(dev);
1750 int nr = sensor_attr->index;
1753 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1756 mutex_lock(&data->update_lock);
1757 it87_update_pwm_ctrl(data, nr);
1758 if (has_newer_autopwm(data)) {
1760 * If we are in automatic mode, the PWM duty cycle register
1761 * is read-only so we can't write the value.
1763 if (data->pwm_ctrl[nr] & 0x80) {
1764 mutex_unlock(&data->update_lock);
1767 data->pwm_duty[nr] = pwm_to_reg(data, val);
1768 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1769 data->pwm_duty[nr]);
1771 data->pwm_duty[nr] = pwm_to_reg(data, val);
1773 * If we are in manual mode, write the duty cycle immediately;
1774 * otherwise, just store it for later use.
1776 if (!(data->pwm_ctrl[nr] & 0x80)) {
1777 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1778 it87_write_value(data, data->REG_PWM[nr],
1779 data->pwm_ctrl[nr]);
1782 mutex_unlock(&data->update_lock);
1786 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1787 const char *buf, size_t count)
1789 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1790 struct it87_data *data = dev_get_drvdata(dev);
1791 int nr = sensor_attr->index;
1795 if (kstrtoul(buf, 10, &val) < 0)
1798 val = clamp_val(val, 0, 1000000);
1799 val *= has_newer_autopwm(data) ? 256 : 128;
1801 /* Search for the nearest available frequency */
1802 for (i = 0; i < 7; i++) {
1803 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1807 mutex_lock(&data->update_lock);
1809 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1810 data->fan_ctl |= i << 4;
1811 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1813 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1814 data->extra |= i << 4;
1815 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1817 mutex_unlock(&data->update_lock);
1822 static ssize_t show_pwm_temp_map(struct device *dev,
1823 struct device_attribute *attr, char *buf)
1825 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1826 struct it87_data *data = it87_update_device(dev);
1827 int nr = sensor_attr->index;
1829 return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1832 static ssize_t set_pwm_temp_map(struct device *dev,
1833 struct device_attribute *attr, const char *buf,
1836 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1837 struct it87_data *data = dev_get_drvdata(dev);
1838 int nr = sensor_attr->index;
1842 if (kstrtoul(buf, 10, &val) < 0)
1845 if (!val || val > data->pwm_num_temp_map)
1850 mutex_lock(&data->update_lock);
1851 it87_update_pwm_ctrl(data, nr);
1852 data->pwm_temp_map[nr] = map;
1854 * If we are in automatic mode, write the temp mapping immediately;
1855 * otherwise, just store it for later use.
1857 if (data->pwm_ctrl[nr] & 0x80) {
1858 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
1859 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1861 mutex_unlock(&data->update_lock);
1865 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1868 struct it87_data *data = it87_update_device(dev);
1869 struct sensor_device_attribute_2 *sensor_attr =
1870 to_sensor_dev_attr_2(attr);
1871 int nr = sensor_attr->nr;
1872 int point = sensor_attr->index;
1874 return sprintf(buf, "%d\n",
1875 pwm_from_reg(data, data->auto_pwm[nr][point]));
1878 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1879 const char *buf, size_t count)
1881 struct it87_data *data = dev_get_drvdata(dev);
1882 struct sensor_device_attribute_2 *sensor_attr =
1883 to_sensor_dev_attr_2(attr);
1884 int nr = sensor_attr->nr;
1885 int point = sensor_attr->index;
1889 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1892 mutex_lock(&data->update_lock);
1893 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1894 if (has_newer_autopwm(data))
1895 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1897 regaddr = IT87_REG_AUTO_PWM(nr, point);
1898 it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1899 mutex_unlock(&data->update_lock);
1903 static ssize_t show_auto_pwm_slope(struct device *dev,
1904 struct device_attribute *attr, char *buf)
1906 struct it87_data *data = it87_update_device(dev);
1907 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1908 int nr = sensor_attr->index;
1910 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1913 static ssize_t set_auto_pwm_slope(struct device *dev,
1914 struct device_attribute *attr,
1915 const char *buf, size_t count)
1917 struct it87_data *data = dev_get_drvdata(dev);
1918 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1919 int nr = sensor_attr->index;
1922 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1925 mutex_lock(&data->update_lock);
1926 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1927 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1928 data->auto_pwm[nr][1]);
1929 mutex_unlock(&data->update_lock);
1933 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1936 struct it87_data *data = it87_update_device(dev);
1937 struct sensor_device_attribute_2 *sensor_attr =
1938 to_sensor_dev_attr_2(attr);
1939 int nr = sensor_attr->nr;
1940 int point = sensor_attr->index;
1943 if (has_old_autopwm(data) || point)
1944 reg = data->auto_temp[nr][point];
1946 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1948 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1951 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1952 const char *buf, size_t count)
1954 struct it87_data *data = dev_get_drvdata(dev);
1955 struct sensor_device_attribute_2 *sensor_attr =
1956 to_sensor_dev_attr_2(attr);
1957 int nr = sensor_attr->nr;
1958 int point = sensor_attr->index;
1962 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1965 mutex_lock(&data->update_lock);
1966 if (has_newer_autopwm(data) && !point) {
1967 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1968 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1969 data->auto_temp[nr][0] = reg;
1970 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1972 reg = TEMP_TO_REG(val);
1973 data->auto_temp[nr][point] = reg;
1974 if (has_newer_autopwm(data))
1976 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1978 mutex_unlock(&data->update_lock);
1982 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1983 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1985 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1988 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1989 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1991 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1994 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1995 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1997 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
2000 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
2001 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2004 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
2005 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2008 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
2009 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
2012 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
2013 show_pwm_enable, set_pwm_enable, 0);
2014 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
2015 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
2017 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
2018 show_pwm_temp_map, set_pwm_temp_map, 0);
2019 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2020 show_auto_pwm, set_auto_pwm, 0, 0);
2021 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2022 show_auto_pwm, set_auto_pwm, 0, 1);
2023 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2024 show_auto_pwm, set_auto_pwm, 0, 2);
2025 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2026 show_auto_pwm, NULL, 0, 3);
2027 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2028 show_auto_temp, set_auto_temp, 0, 1);
2029 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2030 show_auto_temp, set_auto_temp, 0, 0);
2031 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2032 show_auto_temp, set_auto_temp, 0, 2);
2033 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2034 show_auto_temp, set_auto_temp, 0, 3);
2035 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2036 show_auto_temp, set_auto_temp, 0, 4);
2037 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2038 show_auto_pwm, set_auto_pwm, 0, 0);
2039 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2040 show_auto_pwm_slope, set_auto_pwm_slope, 0);
2042 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2043 show_pwm_enable, set_pwm_enable, 1);
2044 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2045 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2046 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2047 show_pwm_temp_map, set_pwm_temp_map, 1);
2048 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2049 show_auto_pwm, set_auto_pwm, 1, 0);
2050 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2051 show_auto_pwm, set_auto_pwm, 1, 1);
2052 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2053 show_auto_pwm, set_auto_pwm, 1, 2);
2054 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2055 show_auto_pwm, NULL, 1, 3);
2056 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2057 show_auto_temp, set_auto_temp, 1, 1);
2058 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2059 show_auto_temp, set_auto_temp, 1, 0);
2060 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2061 show_auto_temp, set_auto_temp, 1, 2);
2062 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2063 show_auto_temp, set_auto_temp, 1, 3);
2064 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2065 show_auto_temp, set_auto_temp, 1, 4);
2066 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2067 show_auto_pwm, set_auto_pwm, 1, 0);
2068 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2069 show_auto_pwm_slope, set_auto_pwm_slope, 1);
2071 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2072 show_pwm_enable, set_pwm_enable, 2);
2073 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2074 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2075 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2076 show_pwm_temp_map, set_pwm_temp_map, 2);
2077 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2078 show_auto_pwm, set_auto_pwm, 2, 0);
2079 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2080 show_auto_pwm, set_auto_pwm, 2, 1);
2081 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2082 show_auto_pwm, set_auto_pwm, 2, 2);
2083 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2084 show_auto_pwm, NULL, 2, 3);
2085 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2086 show_auto_temp, set_auto_temp, 2, 1);
2087 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2088 show_auto_temp, set_auto_temp, 2, 0);
2089 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2090 show_auto_temp, set_auto_temp, 2, 2);
2091 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2092 show_auto_temp, set_auto_temp, 2, 3);
2093 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2094 show_auto_temp, set_auto_temp, 2, 4);
2095 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2096 show_auto_pwm, set_auto_pwm, 2, 0);
2097 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2098 show_auto_pwm_slope, set_auto_pwm_slope, 2);
2100 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2101 show_pwm_enable, set_pwm_enable, 3);
2102 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2103 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2104 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2105 show_pwm_temp_map, set_pwm_temp_map, 3);
2106 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2107 show_auto_temp, set_auto_temp, 2, 1);
2108 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2109 show_auto_temp, set_auto_temp, 2, 0);
2110 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2111 show_auto_temp, set_auto_temp, 2, 2);
2112 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2113 show_auto_temp, set_auto_temp, 2, 3);
2114 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2115 show_auto_pwm, set_auto_pwm, 3, 0);
2116 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2117 show_auto_pwm_slope, set_auto_pwm_slope, 3);
2119 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2120 show_pwm_enable, set_pwm_enable, 4);
2121 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2122 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2123 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2124 show_pwm_temp_map, set_pwm_temp_map, 4);
2125 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2126 show_auto_temp, set_auto_temp, 2, 1);
2127 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2128 show_auto_temp, set_auto_temp, 2, 0);
2129 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2130 show_auto_temp, set_auto_temp, 2, 2);
2131 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2132 show_auto_temp, set_auto_temp, 2, 3);
2133 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2134 show_auto_pwm, set_auto_pwm, 4, 0);
2135 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2136 show_auto_pwm_slope, set_auto_pwm_slope, 4);
2138 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2139 show_pwm_enable, set_pwm_enable, 5);
2140 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2141 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2142 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2143 show_pwm_temp_map, set_pwm_temp_map, 5);
2144 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2145 show_auto_temp, set_auto_temp, 2, 1);
2146 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2147 show_auto_temp, set_auto_temp, 2, 0);
2148 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2149 show_auto_temp, set_auto_temp, 2, 2);
2150 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2151 show_auto_temp, set_auto_temp, 2, 3);
2152 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2153 show_auto_pwm, set_auto_pwm, 5, 0);
2154 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2155 show_auto_pwm_slope, set_auto_pwm_slope, 5);
2158 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2161 struct it87_data *data = it87_update_device(dev);
2163 return sprintf(buf, "%u\n", data->alarms);
2165 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2167 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2170 struct it87_data *data = it87_update_device(dev);
2171 int bitnr = to_sensor_dev_attr(attr)->index;
2173 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2176 static ssize_t clear_intrusion(struct device *dev,
2177 struct device_attribute *attr, const char *buf,
2180 struct it87_data *data = dev_get_drvdata(dev);
2184 if (kstrtol(buf, 10, &val) < 0 || val != 0)
2187 mutex_lock(&data->update_lock);
2188 config = it87_read_value(data, IT87_REG_CONFIG);
2193 it87_write_value(data, IT87_REG_CONFIG, config);
2194 /* Invalidate cache to force re-read */
2197 mutex_unlock(&data->update_lock);
2202 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2203 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2204 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2205 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2206 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2207 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2208 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2209 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2210 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2211 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2212 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2213 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2214 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2215 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2216 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2217 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2218 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2219 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2220 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2221 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2222 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2223 show_alarm, clear_intrusion, 4);
2225 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2228 struct it87_data *data = it87_update_device(dev);
2229 int bitnr = to_sensor_dev_attr(attr)->index;
2231 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2234 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2235 const char *buf, size_t count)
2237 int bitnr = to_sensor_dev_attr(attr)->index;
2238 struct it87_data *data = dev_get_drvdata(dev);
2241 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2244 mutex_lock(&data->update_lock);
2245 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2247 data->beeps |= BIT(bitnr);
2249 data->beeps &= ~BIT(bitnr);
2250 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2251 mutex_unlock(&data->update_lock);
2255 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2256 show_beep, set_beep, 1);
2257 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2258 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2259 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2260 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2261 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2262 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2263 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2264 /* fanX_beep writability is set later */
2265 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2266 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2267 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2268 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2269 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2270 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2271 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2272 show_beep, set_beep, 2);
2273 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2274 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2275 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2276 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2277 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2279 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2282 struct it87_data *data = dev_get_drvdata(dev);
2284 return sprintf(buf, "%u\n", data->vrm);
2287 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2288 const char *buf, size_t count)
2290 struct it87_data *data = dev_get_drvdata(dev);
2293 if (kstrtoul(buf, 10, &val) < 0)
2300 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2302 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2305 struct it87_data *data = it87_update_device(dev);
2307 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2309 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2311 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2314 static const char * const labels[] = {
2320 static const char * const labels_it8721[] = {
2326 struct it87_data *data = dev_get_drvdata(dev);
2327 int nr = to_sensor_dev_attr(attr)->index;
2330 if (has_vin3_5v(data) && nr == 0)
2332 else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2334 label = labels_it8721[nr];
2338 return sprintf(buf, "%s\n", label);
2340 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2341 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2342 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2344 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2346 static umode_t it87_in_is_visible(struct kobject *kobj,
2347 struct attribute *attr, int index)
2349 struct device *dev = container_of(kobj, struct device, kobj);
2350 struct it87_data *data = dev_get_drvdata(dev);
2351 int i = index / 5; /* voltage index */
2352 int a = index % 5; /* attribute index */
2354 if (index >= 40) { /* in8 and higher only have input attributes */
2359 if (!(data->has_in & BIT(i)))
2362 if (a == 4 && !data->has_beep)
2368 static struct attribute *it87_attributes_in[] = {
2369 &sensor_dev_attr_in0_input.dev_attr.attr,
2370 &sensor_dev_attr_in0_min.dev_attr.attr,
2371 &sensor_dev_attr_in0_max.dev_attr.attr,
2372 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2373 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2375 &sensor_dev_attr_in1_input.dev_attr.attr,
2376 &sensor_dev_attr_in1_min.dev_attr.attr,
2377 &sensor_dev_attr_in1_max.dev_attr.attr,
2378 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2379 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2381 &sensor_dev_attr_in2_input.dev_attr.attr,
2382 &sensor_dev_attr_in2_min.dev_attr.attr,
2383 &sensor_dev_attr_in2_max.dev_attr.attr,
2384 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2385 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2387 &sensor_dev_attr_in3_input.dev_attr.attr,
2388 &sensor_dev_attr_in3_min.dev_attr.attr,
2389 &sensor_dev_attr_in3_max.dev_attr.attr,
2390 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2391 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2393 &sensor_dev_attr_in4_input.dev_attr.attr,
2394 &sensor_dev_attr_in4_min.dev_attr.attr,
2395 &sensor_dev_attr_in4_max.dev_attr.attr,
2396 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2397 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2399 &sensor_dev_attr_in5_input.dev_attr.attr,
2400 &sensor_dev_attr_in5_min.dev_attr.attr,
2401 &sensor_dev_attr_in5_max.dev_attr.attr,
2402 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2403 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2405 &sensor_dev_attr_in6_input.dev_attr.attr,
2406 &sensor_dev_attr_in6_min.dev_attr.attr,
2407 &sensor_dev_attr_in6_max.dev_attr.attr,
2408 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2409 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2411 &sensor_dev_attr_in7_input.dev_attr.attr,
2412 &sensor_dev_attr_in7_min.dev_attr.attr,
2413 &sensor_dev_attr_in7_max.dev_attr.attr,
2414 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2415 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2417 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2418 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
2419 &sensor_dev_attr_in10_input.dev_attr.attr, /* 42 */
2420 &sensor_dev_attr_in11_input.dev_attr.attr, /* 43 */
2421 &sensor_dev_attr_in12_input.dev_attr.attr, /* 44 */
2425 static const struct attribute_group it87_group_in = {
2426 .attrs = it87_attributes_in,
2427 .is_visible = it87_in_is_visible,
2430 static umode_t it87_temp_is_visible(struct kobject *kobj,
2431 struct attribute *attr, int index)
2433 struct device *dev = container_of(kobj, struct device, kobj);
2434 struct it87_data *data = dev_get_drvdata(dev);
2435 int i = index / 7; /* temperature index */
2436 int a = index % 7; /* attribute index */
2438 if (!(data->has_temp & BIT(i)))
2441 if (a && i >= data->num_temp_limit)
2445 int type = get_temp_type(data, i);
2449 if (has_bank_sel(data))
2454 if (a == 5 && i >= data->num_temp_offset)
2457 if (a == 6 && !data->has_beep)
2463 static struct attribute *it87_attributes_temp[] = {
2464 &sensor_dev_attr_temp1_input.dev_attr.attr,
2465 &sensor_dev_attr_temp1_max.dev_attr.attr,
2466 &sensor_dev_attr_temp1_min.dev_attr.attr,
2467 &sensor_dev_attr_temp1_type.dev_attr.attr, /* 3 */
2468 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2469 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2470 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2472 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2473 &sensor_dev_attr_temp2_max.dev_attr.attr,
2474 &sensor_dev_attr_temp2_min.dev_attr.attr,
2475 &sensor_dev_attr_temp2_type.dev_attr.attr,
2476 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2477 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2478 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2480 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2481 &sensor_dev_attr_temp3_max.dev_attr.attr,
2482 &sensor_dev_attr_temp3_min.dev_attr.attr,
2483 &sensor_dev_attr_temp3_type.dev_attr.attr,
2484 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2485 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2486 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2488 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2489 &sensor_dev_attr_temp4_max.dev_attr.attr,
2490 &sensor_dev_attr_temp4_min.dev_attr.attr,
2491 &sensor_dev_attr_temp4_type.dev_attr.attr,
2492 &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2493 &sensor_dev_attr_temp4_offset.dev_attr.attr,
2494 &sensor_dev_attr_temp4_beep.dev_attr.attr,
2496 &sensor_dev_attr_temp5_input.dev_attr.attr,
2497 &sensor_dev_attr_temp5_max.dev_attr.attr,
2498 &sensor_dev_attr_temp5_min.dev_attr.attr,
2499 &sensor_dev_attr_temp5_type.dev_attr.attr,
2500 &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2501 &sensor_dev_attr_temp5_offset.dev_attr.attr,
2502 &sensor_dev_attr_temp5_beep.dev_attr.attr,
2504 &sensor_dev_attr_temp6_input.dev_attr.attr,
2505 &sensor_dev_attr_temp6_max.dev_attr.attr,
2506 &sensor_dev_attr_temp6_min.dev_attr.attr,
2507 &sensor_dev_attr_temp6_type.dev_attr.attr,
2508 &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2509 &sensor_dev_attr_temp6_offset.dev_attr.attr,
2510 &sensor_dev_attr_temp6_beep.dev_attr.attr,
2514 static const struct attribute_group it87_group_temp = {
2515 .attrs = it87_attributes_temp,
2516 .is_visible = it87_temp_is_visible,
2519 static umode_t it87_is_visible(struct kobject *kobj,
2520 struct attribute *attr, int index)
2522 struct device *dev = container_of(kobj, struct device, kobj);
2523 struct it87_data *data = dev_get_drvdata(dev);
2525 if ((index == 2 || index == 3) && !data->has_vid)
2528 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2534 static struct attribute *it87_attributes[] = {
2535 &dev_attr_alarms.attr,
2536 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2537 &dev_attr_vrm.attr, /* 2 */
2538 &dev_attr_cpu0_vid.attr, /* 3 */
2539 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2540 &sensor_dev_attr_in7_label.dev_attr.attr,
2541 &sensor_dev_attr_in8_label.dev_attr.attr,
2542 &sensor_dev_attr_in9_label.dev_attr.attr,
2546 static const struct attribute_group it87_group = {
2547 .attrs = it87_attributes,
2548 .is_visible = it87_is_visible,
2551 static umode_t it87_fan_is_visible(struct kobject *kobj,
2552 struct attribute *attr, int index)
2554 struct device *dev = container_of(kobj, struct device, kobj);
2555 struct it87_data *data = dev_get_drvdata(dev);
2556 int i = index / 5; /* fan index */
2557 int a = index % 5; /* attribute index */
2559 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2560 i = (index - 15) / 4 + 3;
2561 a = (index - 15) % 4;
2564 if (!(data->has_fan & BIT(i)))
2567 if (a == 3) { /* beep */
2568 if (!data->has_beep)
2570 /* first fan beep attribute is writable */
2571 if (i == __ffs(data->has_fan))
2572 return attr->mode | S_IWUSR;
2575 if (a == 4 && has_16bit_fans(data)) /* divisor */
2581 static struct attribute *it87_attributes_fan[] = {
2582 &sensor_dev_attr_fan1_input.dev_attr.attr,
2583 &sensor_dev_attr_fan1_min.dev_attr.attr,
2584 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2585 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2586 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2588 &sensor_dev_attr_fan2_input.dev_attr.attr,
2589 &sensor_dev_attr_fan2_min.dev_attr.attr,
2590 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2591 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2592 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2594 &sensor_dev_attr_fan3_input.dev_attr.attr,
2595 &sensor_dev_attr_fan3_min.dev_attr.attr,
2596 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2597 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2598 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2600 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2601 &sensor_dev_attr_fan4_min.dev_attr.attr,
2602 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2603 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2605 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2606 &sensor_dev_attr_fan5_min.dev_attr.attr,
2607 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2608 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2610 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2611 &sensor_dev_attr_fan6_min.dev_attr.attr,
2612 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2613 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2617 static const struct attribute_group it87_group_fan = {
2618 .attrs = it87_attributes_fan,
2619 .is_visible = it87_fan_is_visible,
2622 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2623 struct attribute *attr, int index)
2625 struct device *dev = container_of(kobj, struct device, kobj);
2626 struct it87_data *data = dev_get_drvdata(dev);
2627 int i = index / 4; /* pwm index */
2628 int a = index % 4; /* attribute index */
2630 if (!(data->has_pwm & BIT(i)))
2633 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2634 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2635 return attr->mode | S_IWUSR;
2637 /* pwm2_freq is writable if there are two pwm frequency selects */
2638 if (has_pwm_freq2(data) && i == 1 && a == 2)
2639 return attr->mode | S_IWUSR;
2644 static struct attribute *it87_attributes_pwm[] = {
2645 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2646 &sensor_dev_attr_pwm1.dev_attr.attr,
2647 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2648 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2650 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2651 &sensor_dev_attr_pwm2.dev_attr.attr,
2652 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2653 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2655 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2656 &sensor_dev_attr_pwm3.dev_attr.attr,
2657 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2658 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2660 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2661 &sensor_dev_attr_pwm4.dev_attr.attr,
2662 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2663 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2665 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2666 &sensor_dev_attr_pwm5.dev_attr.attr,
2667 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2668 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2670 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2671 &sensor_dev_attr_pwm6.dev_attr.attr,
2672 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2673 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2678 static const struct attribute_group it87_group_pwm = {
2679 .attrs = it87_attributes_pwm,
2680 .is_visible = it87_pwm_is_visible,
2683 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2684 struct attribute *attr, int index)
2686 struct device *dev = container_of(kobj, struct device, kobj);
2687 struct it87_data *data = dev_get_drvdata(dev);
2688 int i = index / 11; /* pwm index */
2689 int a = index % 11; /* attribute index */
2691 if (index >= 33) { /* pwm 4..6 */
2692 i = (index - 33) / 6 + 3;
2693 a = (index - 33) % 6 + 4;
2696 if (!(data->has_pwm & BIT(i)))
2699 if (has_newer_autopwm(data)) {
2700 if (a < 4) /* no auto point pwm */
2702 if (a == 8) /* no auto_point4 */
2705 if (has_old_autopwm(data)) {
2706 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2713 static struct attribute *it87_attributes_auto_pwm[] = {
2714 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2715 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2716 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2717 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2718 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2719 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2720 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2721 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2722 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2723 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2724 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2726 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2727 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2728 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2729 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2730 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2731 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2732 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2733 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2734 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2735 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2736 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2738 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2739 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2740 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2741 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2742 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2743 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2744 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2745 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2746 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2747 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2748 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2750 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2751 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2752 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2753 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2754 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2755 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2757 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2758 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2759 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2760 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2761 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2762 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2764 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2765 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2766 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2767 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2768 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2769 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2774 static const struct attribute_group it87_group_auto_pwm = {
2775 .attrs = it87_attributes_auto_pwm,
2776 .is_visible = it87_auto_pwm_is_visible,
2779 /* SuperIO detection - will change isa_address if a chip is found */
2780 static int __init it87_find(int sioaddr, unsigned short *address,
2781 struct it87_sio_data *sio_data)
2783 const struct it87_devices *config;
2788 err = superio_enter(sioaddr);
2793 chip_type = superio_inw(sioaddr, DEVID);
2794 if (chip_type == 0xffff)
2798 chip_type = force_id;
2800 switch (chip_type) {
2802 sio_data->type = it87;
2805 sio_data->type = it8712;
2809 sio_data->type = it8716;
2812 sio_data->type = it8718;
2815 sio_data->type = it8720;
2818 sio_data->type = it8721;
2821 sio_data->type = it8728;
2824 sio_data->type = it8732;
2827 sio_data->type = it8792;
2829 * Disabling configuration mode on IT8792E can result in system
2830 * hang-ups and access failures to the Super-IO chip at the
2831 * second SIO address. Never exit configuration mode on this
2832 * chip to avoid the problem.
2837 sio_data->type = it8771;
2840 sio_data->type = it8772;
2843 sio_data->type = it8781;
2846 sio_data->type = it8782;
2849 sio_data->type = it8783;
2852 sio_data->type = it8786;
2855 sio_data->type = it8790;
2856 doexit = false; /* See IT8792E comment above */
2860 sio_data->type = it8603;
2863 sio_data->type = it8607;
2866 sio_data->type = it8613;
2869 sio_data->type = it8620;
2872 sio_data->type = it8622;
2875 sio_data->type = it8625;
2878 sio_data->type = it8628;
2881 sio_data->type = it8655;
2884 sio_data->type = it8665;
2887 sio_data->type = it8686;
2889 case 0xffff: /* No device at all */
2892 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2896 superio_select(sioaddr, PME);
2897 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2898 pr_info("Device not activated, skipping\n");
2902 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2903 if (*address == 0) {
2904 pr_info("Base address not set, skipping\n");
2909 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2910 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2911 it87_devices[sio_data->type].suffix,
2912 *address, sio_data->revision);
2914 config = &it87_devices[sio_data->type];
2916 /* in7 (VSB or VCCH5V) is always internal on some chips */
2917 if (has_in7_internal(config))
2918 sio_data->internal |= BIT(1);
2920 /* in8 (Vbat) is always internal */
2921 sio_data->internal |= BIT(2);
2923 /* in9 (AVCC3), always internal if supported */
2924 if (has_avcc3(config))
2925 sio_data->internal |= BIT(3); /* in9 is AVCC */
2927 sio_data->skip_in |= BIT(9);
2929 if (!has_four_pwm(config))
2930 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2931 else if (!has_five_pwm(config))
2932 sio_data->skip_pwm |= BIT(4) | BIT(5);
2933 else if (!has_six_pwm(config))
2934 sio_data->skip_pwm |= BIT(5);
2936 if (!has_vid(config))
2937 sio_data->skip_vid = 1;
2939 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2940 if (sio_data->type == it87) {
2941 /* The IT8705F has a different LD number for GPIO */
2942 superio_select(sioaddr, 5);
2943 sio_data->beep_pin = superio_inb(sioaddr,
2944 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2945 } else if (sio_data->type == it8783) {
2946 int reg25, reg27, reg2a, reg2c, regef;
2948 superio_select(sioaddr, GPIO);
2950 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2951 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2952 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2953 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2954 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2956 /* Check if fan3 is there or not */
2957 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2958 sio_data->skip_fan |= BIT(2);
2959 if ((reg25 & BIT(4)) ||
2960 (!(reg2a & BIT(1)) && (regef & BIT(0))))
2961 sio_data->skip_pwm |= BIT(2);
2963 /* Check if fan2 is there or not */
2965 sio_data->skip_fan |= BIT(1);
2967 sio_data->skip_pwm |= BIT(1);
2970 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2971 sio_data->skip_in |= BIT(5); /* No VIN5 */
2975 sio_data->skip_in |= BIT(6); /* No VIN6 */
2979 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2981 if (reg27 & BIT(2)) {
2983 * The data sheet is a bit unclear regarding the
2984 * internal voltage divider for VCCH5V. It says
2985 * "This bit enables and switches VIN7 (pin 91) to the
2986 * internal voltage divider for VCCH5V".
2987 * This is different to other chips, where the internal
2988 * voltage divider would connect VIN7 to an internal
2989 * voltage source. Maybe that is the case here as well.
2991 * Since we don't know for sure, re-route it if that is
2992 * not the case, and ask the user to report if the
2993 * resulting voltage is sane.
2995 if (!(reg2c & BIT(1))) {
2997 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2999 pr_notice("Routing internal VCCH5V to in7.\n");
3001 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3002 pr_notice("Please report if it displays a reasonable voltage.\n");
3006 sio_data->internal |= BIT(0);
3008 sio_data->internal |= BIT(1);
3010 sio_data->beep_pin = superio_inb(sioaddr,
3011 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3012 } else if (sio_data->type == it8603 || sio_data->type == it8607) {
3015 superio_select(sioaddr, GPIO);
3017 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3019 /* Check if fan3 is there or not */
3021 sio_data->skip_pwm |= BIT(2);
3023 sio_data->skip_fan |= BIT(2);
3025 /* Check if fan2 is there or not */
3026 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3028 sio_data->skip_pwm |= BIT(1);
3030 sio_data->skip_fan |= BIT(1);
3032 switch (sio_data->type) {
3034 sio_data->skip_in |= BIT(5); /* No VIN5 */
3035 sio_data->skip_in |= BIT(6); /* No VIN6 */
3038 sio_data->skip_pwm |= BIT(0);/* No fan1 */
3039 sio_data->skip_fan |= BIT(0);
3044 sio_data->beep_pin = superio_inb(sioaddr,
3045 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3046 } else if (sio_data->type == it8613) {
3047 int reg27, reg29, reg2a;
3049 superio_select(sioaddr, GPIO);
3051 /* Check for pwm3, fan3, pwm5, fan5 */
3052 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3054 sio_data->skip_fan |= BIT(4);
3056 sio_data->skip_pwm |= BIT(4);
3058 sio_data->skip_pwm |= BIT(2);
3060 sio_data->skip_fan |= BIT(2);
3062 /* Check for pwm2, fan2 */
3063 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3065 sio_data->skip_pwm |= BIT(1);
3067 sio_data->skip_fan |= BIT(1);
3069 /* Check for pwm4, fan4 */
3070 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3071 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3072 sio_data->skip_fan |= BIT(3);
3073 sio_data->skip_pwm |= BIT(3);
3076 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3077 sio_data->skip_fan |= BIT(0); /* No fan1 */
3078 sio_data->skip_in |= BIT(3); /* No VIN3 */
3079 sio_data->skip_in |= BIT(6); /* No VIN6 */
3081 sio_data->beep_pin = superio_inb(sioaddr,
3082 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3083 } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3084 sio_data->type == it8686) {
3087 superio_select(sioaddr, GPIO);
3089 /* Check for pwm5 */
3090 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3092 sio_data->skip_pwm |= BIT(4);
3094 /* Check for fan4, fan5 */
3095 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3096 if (!(reg & BIT(5)))
3097 sio_data->skip_fan |= BIT(3);
3098 if (!(reg & BIT(4)))
3099 sio_data->skip_fan |= BIT(4);
3101 /* Check for pwm3, fan3 */
3102 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3104 sio_data->skip_pwm |= BIT(2);
3106 sio_data->skip_fan |= BIT(2);
3108 /* Check for pwm4 */
3109 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3111 sio_data->skip_pwm |= BIT(3);
3113 /* Check for pwm2, fan2 */
3114 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3116 sio_data->skip_pwm |= BIT(1);
3118 sio_data->skip_fan |= BIT(1);
3119 /* Check for pwm6, fan6 */
3120 if (!(reg & BIT(7))) {
3121 sio_data->skip_pwm |= BIT(5);
3122 sio_data->skip_fan |= BIT(5);
3125 /* Check if AVCC is on VIN3 */
3126 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3128 /* For it8686, the bit just enables AVCC3 */
3129 if (sio_data->type != it8686)
3130 sio_data->internal |= BIT(0);
3132 sio_data->internal &= ~BIT(3);
3133 sio_data->skip_in |= BIT(9);
3136 sio_data->beep_pin = superio_inb(sioaddr,
3137 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3138 } else if (sio_data->type == it8622) {
3141 superio_select(sioaddr, GPIO);
3143 /* Check for pwm4, fan4 */
3144 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3146 sio_data->skip_fan |= BIT(3);
3148 sio_data->skip_pwm |= BIT(3);
3150 /* Check for pwm3, fan3, pwm5, fan5 */
3151 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3153 sio_data->skip_pwm |= BIT(2);
3155 sio_data->skip_fan |= BIT(2);
3157 sio_data->skip_pwm |= BIT(4);
3159 sio_data->skip_fan |= BIT(4);
3161 /* Check for pwm2, fan2 */
3162 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3164 sio_data->skip_pwm |= BIT(1);
3166 sio_data->skip_fan |= BIT(1);
3168 /* Check for AVCC */
3169 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3170 if (!(reg & BIT(0)))
3171 sio_data->skip_in |= BIT(9);
3173 sio_data->beep_pin = superio_inb(sioaddr,
3174 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3175 } else if (sio_data->type == it8732) {
3178 superio_select(sioaddr, GPIO);
3180 /* Check for pwm2, fan2 */
3181 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3183 sio_data->skip_pwm |= BIT(1);
3185 sio_data->skip_fan |= BIT(1);
3187 /* Check for pwm3, fan3, fan4 */
3188 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3190 sio_data->skip_pwm |= BIT(2);
3192 sio_data->skip_fan |= BIT(2);
3194 sio_data->skip_fan |= BIT(3);
3196 /* Check if AVCC is on VIN3 */
3197 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3199 sio_data->internal |= BIT(0);
3201 sio_data->beep_pin = superio_inb(sioaddr,
3202 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3203 } else if (sio_data->type == it8655) {
3206 superio_select(sioaddr, GPIO);
3208 /* Check for pwm2 */
3209 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3211 sio_data->skip_pwm |= BIT(1);
3213 /* Check for fan2 */
3214 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3216 sio_data->skip_fan |= BIT(1);
3218 /* Check for pwm3, fan3 */
3219 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3221 sio_data->skip_pwm |= BIT(2);
3223 sio_data->skip_fan |= BIT(2);
3225 sio_data->beep_pin = superio_inb(sioaddr,
3226 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3227 } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3228 int reg27, reg29, reg2d, regd3;
3230 superio_select(sioaddr, GPIO);
3232 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3233 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3234 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3235 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3237 /* Check for pwm2, fan2 */
3239 sio_data->skip_pwm |= BIT(1);
3241 sio_data->skip_fan |= BIT(1);
3243 /* Check for pwm3, fan3 */
3245 sio_data->skip_pwm |= BIT(2);
3247 sio_data->skip_fan |= BIT(2);
3249 /* Check for pwm4, fan4, pwm5, fan5 */
3250 if (sio_data->type == it8625) {
3251 int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3254 sio_data->skip_fan |= BIT(3);
3256 sio_data->skip_pwm |= BIT(3);
3258 sio_data->skip_pwm |= BIT(4);
3260 sio_data->skip_fan |= BIT(4);
3262 int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3265 sio_data->skip_pwm |= BIT(3);
3267 sio_data->skip_fan |= BIT(3);
3269 sio_data->skip_pwm |= BIT(4);
3270 if (!(reg26 & BIT(4)))
3271 sio_data->skip_fan |= BIT(4);
3274 /* Check for pwm6, fan6 */
3276 sio_data->skip_pwm |= BIT(5);
3278 sio_data->skip_fan |= BIT(5);
3280 sio_data->beep_pin = superio_inb(sioaddr,
3281 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3286 superio_select(sioaddr, GPIO);
3288 /* Check for fan4, fan5 */
3289 if (has_five_fans(config)) {
3290 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3291 switch (sio_data->type) {
3294 sio_data->skip_fan |= BIT(3);
3296 sio_data->skip_fan |= BIT(4);
3301 if (!(reg & BIT(5)))
3302 sio_data->skip_fan |= BIT(3);
3303 if (!(reg & BIT(4)))
3304 sio_data->skip_fan |= BIT(4);
3311 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3312 if (!sio_data->skip_vid) {
3313 /* We need at least 4 VID pins */
3315 pr_info("VID is disabled (pins used for GPIO)\n");
3316 sio_data->skip_vid = 1;
3320 /* Check if fan3 is there or not */
3322 sio_data->skip_pwm |= BIT(2);
3324 sio_data->skip_fan |= BIT(2);
3326 /* Check if fan2 is there or not */
3327 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3329 sio_data->skip_pwm |= BIT(1);
3331 sio_data->skip_fan |= BIT(1);
3333 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3334 !(sio_data->skip_vid))
3335 sio_data->vid_value = superio_inb(sioaddr,
3338 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3340 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3343 * The IT8720F has no VIN7 pin, so VCCH should always be
3344 * routed internally to VIN7 with an internal divider.
3345 * Curiously, there still is a configuration bit to control
3346 * this, which means it can be set incorrectly. And even
3347 * more curiously, many boards out there are improperly
3348 * configured, even though the IT8720F datasheet claims
3349 * that the internal routing of VCCH to VIN7 is the default
3350 * setting. So we force the internal routing in this case.
3352 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3353 * If UART6 is enabled, re-route VIN7 to the internal divider
3354 * if that is not already the case.
3356 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3358 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3359 pr_notice("Routing internal VCCH to in7\n");
3362 sio_data->internal |= BIT(0);
3364 sio_data->internal |= BIT(1);
3367 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3368 * While VIN7 can be routed to the internal voltage divider,
3369 * VIN5 and VIN6 are not available if UART6 is enabled.
3371 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3372 * is the temperature source. Since we can not read the
3373 * temperature source here, skip_temp is preliminary.
3376 sio_data->skip_in |= BIT(5) | BIT(6);
3377 sio_data->skip_temp |= BIT(2);
3380 sio_data->beep_pin = superio_inb(sioaddr,
3381 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3383 if (sio_data->beep_pin)
3384 pr_info("Beeping is supported\n");
3387 superio_exit(sioaddr, doexit);
3391 static void it87_init_regs(struct platform_device *pdev)
3393 struct it87_data *data = platform_get_drvdata(pdev);
3395 /* Initialize chip specific register pointers */
3396 switch (data->type) {
3399 data->REG_FAN = IT87_REG_FAN;
3400 data->REG_FANX = IT87_REG_FANX;
3401 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3402 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3403 data->REG_PWM = IT87_REG_PWM;
3404 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3405 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3406 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3411 data->REG_FAN = IT87_REG_FAN_8665;
3412 data->REG_FANX = IT87_REG_FANX_8665;
3413 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3414 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3415 data->REG_PWM = IT87_REG_PWM_8665;
3416 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3417 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3418 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3421 data->REG_FAN = IT87_REG_FAN;
3422 data->REG_FANX = IT87_REG_FANX;
3423 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3424 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3425 data->REG_PWM = IT87_REG_PWM_8665;
3426 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3427 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3428 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3431 data->REG_FAN = IT87_REG_FAN;
3432 data->REG_FANX = IT87_REG_FANX;
3433 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3434 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3435 data->REG_PWM = IT87_REG_PWM_8665;
3436 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3437 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3438 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3441 data->REG_FAN = IT87_REG_FAN;
3442 data->REG_FANX = IT87_REG_FANX;
3443 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3444 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3445 data->REG_PWM = IT87_REG_PWM;
3446 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3447 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3448 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3453 /* Called when we have found a new IT87. */
3454 static void it87_init_device(struct platform_device *pdev)
3456 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3457 struct it87_data *data = platform_get_drvdata(pdev);
3461 if (has_new_tempmap(data)) {
3462 data->pwm_temp_map_shift = 3;
3463 data->pwm_temp_map_mask = 0x07;
3465 data->pwm_temp_map_shift = 0;
3466 data->pwm_temp_map_mask = 0x03;
3470 * For each PWM channel:
3471 * - If it is in automatic mode, setting to manual mode should set
3472 * the fan to full speed by default.
3473 * - If it is in manual mode, we need a mapping to temperature
3474 * channels to use when later setting to automatic mode later.
3475 * Map to the first sensor by default (we are clueless.)
3476 * In both cases, the value can (and should) be changed by the user
3477 * prior to switching to a different mode.
3478 * Note that this is no longer needed for the IT8721F and later, as
3479 * these have separate registers for the temperature mapping and the
3480 * manual duty cycle.
3482 for (i = 0; i < NUM_AUTO_PWM; i++) {
3483 data->pwm_temp_map[i] = 0;
3484 data->pwm_duty[i] = 0x7f; /* Full speed */
3485 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
3489 * Some chips seem to have default value 0xff for all limit
3490 * registers. For low voltage limits it makes no sense and triggers
3491 * alarms, so change to 0 instead. For high temperature limits, it
3492 * means -1 degree C, which surprisingly doesn't trigger an alarm,
3493 * but is still confusing, so change to 127 degrees C.
3495 for (i = 0; i < NUM_VIN_LIMIT; i++) {
3496 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3498 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3500 for (i = 0; i < data->num_temp_limit; i++) {
3501 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3503 it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3507 * Temperature channels are not forcibly enabled, as they can be
3508 * set to two different sensor types and we can't guess which one
3509 * is correct for a given system. These channels can be enabled at
3510 * run-time through the temp{1-3}_type sysfs accessors if needed.
3513 /* Check if voltage monitors are reset manually or by some reason */
3514 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3515 if ((tmp & 0xff) == 0) {
3516 /* Enable all voltage monitors */
3517 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3520 /* Check if tachometers are reset manually or by some reason */
3521 mask = 0x70 & ~(sio_data->skip_fan << 4);
3522 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3523 if ((data->fan_main_ctrl & mask) == 0) {
3524 /* Enable all fan tachometers */
3525 data->fan_main_ctrl |= mask;
3526 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3527 data->fan_main_ctrl);
3529 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3531 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3533 /* Set tachometers to 16-bit mode if needed */
3534 if (has_fan16_config(data)) {
3535 if (~tmp & 0x07 & data->has_fan) {
3537 "Setting fan1-3 to 16-bit mode\n");
3538 it87_write_value(data, IT87_REG_FAN_16BIT,
3543 /* Check for additional fans */
3544 if (has_four_fans(data) && (tmp & BIT(4)))
3545 data->has_fan |= BIT(3); /* fan4 enabled */
3546 if (has_five_fans(data) && (tmp & BIT(5)))
3547 data->has_fan |= BIT(4); /* fan5 enabled */
3548 if (has_six_fans(data)) {
3549 switch (data->type) {
3554 data->has_fan |= BIT(5); /* fan6 enabled */
3558 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3560 data->has_fan |= BIT(5); /* fan6 enabled */
3567 /* Fan input pins may be used for alternative functions */
3568 data->has_fan &= ~sio_data->skip_fan;
3570 /* Check if pwm6 is enabled */
3571 if (has_six_pwm(data)) {
3572 switch (data->type) {
3575 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3576 if (!(tmp & BIT(3)))
3577 sio_data->skip_pwm |= BIT(5);
3584 if (has_bank_sel(data)) {
3585 for (i = 0; i < 3; i++)
3587 it87_read_value(data, IT87_REG_TEMP_SRC1[i]);
3588 data->temp_src[3] = it87_read_value(data, IT87_REG_TEMP_SRC2);
3591 /* Start monitoring */
3592 it87_write_value(data, IT87_REG_CONFIG,
3593 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3594 | (update_vbat ? 0x41 : 0x01));
3597 /* Return 1 if and only if the PWM interface is safe to use */
3598 static int it87_check_pwm(struct device *dev)
3600 struct it87_data *data = dev_get_drvdata(dev);
3602 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3603 * and polarity set to active low is sign that this is the case so we
3604 * disable pwm control to protect the user.
3606 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3608 if ((tmp & 0x87) == 0) {
3609 if (fix_pwm_polarity) {
3611 * The user asks us to attempt a chip reconfiguration.
3612 * This means switching to active high polarity and
3613 * inverting all fan speed values.
3618 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3619 pwm[i] = it87_read_value(data,
3623 * If any fan is in automatic pwm mode, the polarity
3624 * might be correct, as suspicious as it seems, so we
3625 * better don't change anything (but still disable the
3628 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3630 "Reconfiguring PWM to active high polarity\n");
3631 it87_write_value(data, IT87_REG_FAN_CTL,
3633 for (i = 0; i < 3; i++)
3634 it87_write_value(data,
3641 "PWM configuration is too broken to be fixed\n");
3645 "Detected broken BIOS defaults, disabling PWM interface\n");
3647 } else if (fix_pwm_polarity) {
3649 "PWM configuration looks sane, won't touch\n");
3655 static int it87_probe(struct platform_device *pdev)
3657 struct it87_data *data;
3658 struct resource *res;
3659 struct device *dev = &pdev->dev;
3660 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3661 int enable_pwm_interface;
3662 struct device *hwmon_dev;
3664 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3665 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3667 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3668 (unsigned long)res->start,
3669 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3673 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3677 data->addr = res->start;
3678 data->type = sio_data->type;
3679 data->features = it87_devices[sio_data->type].features;
3680 data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3681 data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3682 data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3683 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3684 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3687 * IT8705F Datasheet 0.4.1, 3h == Version G.
3688 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3689 * These are the first revisions with 16-bit tachometer support.
3691 switch (data->type) {
3693 if (sio_data->revision >= 0x03) {
3694 data->features &= ~FEAT_OLD_AUTOPWM;
3695 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3699 if (sio_data->revision >= 0x08) {
3700 data->features &= ~FEAT_OLD_AUTOPWM;
3701 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3709 /* Now, we do the remaining detection. */
3710 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3711 it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3714 platform_set_drvdata(pdev, data);
3716 mutex_init(&data->update_lock);
3718 /* Initialize register pointers */
3719 it87_init_regs(pdev);
3721 /* Check PWM configuration */
3722 enable_pwm_interface = it87_check_pwm(dev);
3724 /* Starting with IT8721F, we handle scaling of internal voltages */
3725 if (has_scaling(data)) {
3726 if (sio_data->internal & BIT(0))
3727 data->in_scaled |= BIT(3); /* in3 is AVCC */
3728 if (sio_data->internal & BIT(1))
3729 data->in_scaled |= BIT(7); /* in7 is VSB */
3730 if (sio_data->internal & BIT(2))
3731 data->in_scaled |= BIT(8); /* in8 is Vbat */
3732 if (sio_data->internal & BIT(3))
3733 data->in_scaled |= BIT(9); /* in9 is AVCC */
3734 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3735 sio_data->type == it8783) {
3736 if (sio_data->internal & BIT(0))
3737 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3738 if (sio_data->internal & BIT(1))
3739 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3742 data->has_temp = 0x07;
3743 if (sio_data->skip_temp & BIT(2)) {
3744 if (sio_data->type == it8782 &&
3745 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3746 data->has_temp &= ~BIT(2);
3749 data->in_internal = sio_data->internal;
3750 data->has_in = 0x3ff & ~sio_data->skip_in;
3752 if (has_six_temp(data)) {
3753 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3755 /* Check for additional temperature sensors */
3756 if ((reg & 0x03) >= 0x02)
3757 data->has_temp |= BIT(3);
3758 if (((reg >> 2) & 0x03) >= 0x02)
3759 data->has_temp |= BIT(4);
3760 if (((reg >> 4) & 0x03) >= 0x02)
3761 data->has_temp |= BIT(5);
3763 /* Check for additional voltage sensors */
3764 if ((reg & 0x03) == 0x01)
3765 data->has_in |= BIT(10);
3766 if (((reg >> 2) & 0x03) == 0x01)
3767 data->has_in |= BIT(11);
3768 if (((reg >> 4) & 0x03) == 0x01)
3769 data->has_in |= BIT(12);
3772 data->has_beep = !!sio_data->beep_pin;
3774 /* Initialize the IT87 chip */
3775 it87_init_device(pdev);
3777 if (!sio_data->skip_vid) {
3778 data->has_vid = true;
3779 data->vrm = vid_which_vrm();
3780 /* VID reading from Super-I/O config space if available */
3781 data->vid = sio_data->vid_value;
3784 /* Prepare for sysfs hooks */
3785 data->groups[0] = &it87_group;
3786 data->groups[1] = &it87_group_in;
3787 data->groups[2] = &it87_group_temp;
3788 data->groups[3] = &it87_group_fan;
3790 if (enable_pwm_interface) {
3791 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3792 data->has_pwm &= ~sio_data->skip_pwm;
3794 data->groups[4] = &it87_group_pwm;
3795 if (has_old_autopwm(data) || has_newer_autopwm(data))
3796 data->groups[5] = &it87_group_auto_pwm;
3799 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3800 it87_devices[sio_data->type].name,
3801 data, data->groups);
3802 return PTR_ERR_OR_ZERO(hwmon_dev);
3805 static struct platform_driver it87_driver = {
3809 .probe = it87_probe,
3812 static int __init it87_device_add(int index, unsigned short address,
3813 const struct it87_sio_data *sio_data)
3815 struct platform_device *pdev;
3816 struct resource res = {
3817 .start = address + IT87_EC_OFFSET,
3818 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3820 .flags = IORESOURCE_IO,
3824 err = acpi_check_resource_conflict(&res);
3826 if (!ignore_resource_conflict)
3830 pdev = platform_device_alloc(DRVNAME, address);
3834 err = platform_device_add_resources(pdev, &res, 1);
3836 pr_err("Device resource addition failed (%d)\n", err);
3837 goto exit_device_put;
3840 err = platform_device_add_data(pdev, sio_data,
3841 sizeof(struct it87_sio_data));
3843 pr_err("Platform data allocation failed\n");
3844 goto exit_device_put;
3847 err = platform_device_add(pdev);
3849 pr_err("Device addition failed (%d)\n", err);
3850 goto exit_device_put;
3853 it87_pdev[index] = pdev;
3857 platform_device_put(pdev);
3861 struct it87_dmi_data {
3862 bool sio2_force_config; /* force sio2 into configuration mode */
3863 u8 skip_pwm; /* pwm channels to skip for this board */
3867 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
3868 * (IT8792E) needs to be in configuration mode before accessing the first
3869 * due to a bug in IT8792E which otherwise results in LPC bus access errors.
3870 * This needs to be done before accessing the first Super-IO chip since
3871 * the second chip may have been accessed prior to loading this driver.
3873 * The problem is also reported to affect IT8795E, which is used on X299 boards
3874 * and has the same chip ID as IT8792E (0x8733). It also appears to affect
3875 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
3877 * DMI entries for those systems will be added as they become available and
3878 * as the problem is confirmed to affect those boards.
3880 static struct it87_dmi_data gigabyte_sio2_force = {
3881 .sio2_force_config = true,
3885 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3886 * connected to a fan, but to something else. One user
3887 * has reported instant system power-off when changing
3888 * the PWM2 duty cycle, so we disable it.
3889 * I use the board name string as the trigger in case
3890 * the same board is ever used in other systems.
3892 static struct it87_dmi_data nvidia_fn68pt = {
3896 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3899 DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3900 DMI_MATCH(DMI_BOARD_NAME, "AB350"),
3902 .driver_data = &gigabyte_sio2_force,
3906 DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3907 DMI_MATCH(DMI_BOARD_NAME, "AX370"),
3909 .driver_data = &gigabyte_sio2_force,
3913 DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3914 DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
3916 .driver_data = &gigabyte_sio2_force,
3920 DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3921 DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3923 .driver_data = &nvidia_fn68pt,
3928 static int __init sm_it87_init(void)
3930 const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3931 struct it87_dmi_data *dmi_data = NULL;
3932 int sioaddr[2] = { REG_2E, REG_4E };
3933 struct it87_sio_data sio_data;
3934 unsigned short isa_address;
3938 pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
3941 dmi_data = dmi->driver_data;
3943 err = platform_driver_register(&it87_driver);
3947 if (dmi_data && dmi_data->sio2_force_config)
3948 __superio_enter(REG_4E);
3950 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3951 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3953 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3954 if (err || isa_address == 0)
3958 sio_data.skip_pwm |= dmi_data->skip_pwm;
3959 err = it87_device_add(i, isa_address, &sio_data);
3961 goto exit_dev_unregister;
3967 goto exit_unregister;
3971 exit_dev_unregister:
3972 /* NULL check handled by platform_device_unregister */
3973 platform_device_unregister(it87_pdev[0]);
3975 platform_driver_unregister(&it87_driver);
3979 static void __exit sm_it87_exit(void)
3981 /* NULL check handled by platform_device_unregister */
3982 platform_device_unregister(it87_pdev[1]);
3983 platform_device_unregister(it87_pdev[0]);
3984 platform_driver_unregister(&it87_driver);
3987 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3988 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3989 module_param(update_vbat, bool, 0);
3990 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3991 module_param(fix_pwm_polarity, bool, 0);
3992 MODULE_PARM_DESC(fix_pwm_polarity,
3993 "Force PWM polarity to active high (DANGEROUS)");
3994 MODULE_LICENSE("GPL");
3996 module_init(sm_it87_init);
3997 module_exit(sm_it87_exit);