2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
13 * Supports: IT8603E Super I/O chip w/LPC interface
14 * IT8607E Super I/O chip w/LPC interface
15 * IT8613E Super I/O chip w/LPC interface
16 * IT8620E Super I/O chip w/LPC interface
17 * IT8622E Super I/O chip w/LPC interface
18 * IT8623E Super I/O chip w/LPC interface
19 * IT8625E Super I/O chip w/LPC interface
20 * IT8628E Super I/O chip w/LPC interface
21 * IT8655E Super I/O chip w/LPC interface
22 * IT8665E Super I/O chip w/LPC interface
23 * IT8686E Super I/O chip w/LPC interface
24 * IT8705F Super I/O chip w/LPC interface
25 * IT8712F Super I/O chip w/LPC interface
26 * IT8716F Super I/O chip w/LPC interface
27 * IT8718F Super I/O chip w/LPC interface
28 * IT8720F Super I/O chip w/LPC interface
29 * IT8721F Super I/O chip w/LPC interface
30 * IT8726F Super I/O chip w/LPC interface
31 * IT8728F Super I/O chip w/LPC interface
32 * IT8732F Super I/O chip w/LPC interface
33 * IT8758E Super I/O chip w/LPC interface
34 * IT8771E Super I/O chip w/LPC interface
35 * IT8772E Super I/O chip w/LPC interface
36 * IT8781F Super I/O chip w/LPC interface
37 * IT8782F Super I/O chip w/LPC interface
38 * IT8783E/F Super I/O chip w/LPC interface
39 * IT8786E Super I/O chip w/LPC interface
40 * IT8790E Super I/O chip w/LPC interface
41 * IT8792E Super I/O chip w/LPC interface
42 * Sis950 A clone of the IT8705F
44 * Copyright (C) 2001 Chris Gauthron
45 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
47 * This program is free software; you can redistribute it and/or modify
48 * it under the terms of the GNU General Public License as published by
49 * the Free Software Foundation; either version 2 of the License, or
50 * (at your option) any later version.
52 * This program is distributed in the hope that it will be useful,
53 * but WITHOUT ANY WARRANTY; without even the implied warranty of
54 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
55 * GNU General Public License for more details.
58 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
60 #include <linux/bitops.h>
61 #include <linux/module.h>
62 #include <linux/init.h>
63 #include <linux/slab.h>
64 #include <linux/jiffies.h>
65 #include <linux/platform_device.h>
66 #include <linux/hwmon.h>
67 #include <linux/hwmon-sysfs.h>
68 #include <linux/hwmon-vid.h>
69 #include <linux/err.h>
70 #include <linux/mutex.h>
71 #include <linux/sysfs.h>
72 #include <linux/string.h>
73 #include <linux/dmi.h>
74 #include <linux/acpi.h>
78 #define DRVNAME "it87"
80 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
81 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
82 it8792, it8603, it8607, it8613, it8620, it8622, it8625, it8628,
83 it8655, it8665, it8686 };
85 static unsigned short force_id;
86 module_param(force_id, ushort, 0);
87 MODULE_PARM_DESC(force_id, "Override the detected device ID");
89 static struct platform_device *it87_pdev[2];
91 #define REG_2E 0x2e /* The register to read/write */
92 #define REG_4E 0x4e /* Secondary register to read/write */
94 #define DEV 0x07 /* Register: Logical device select */
95 #define PME 0x04 /* The device with the fan registers in it */
97 /* The device with the IT8718F/IT8720F VID value in it */
100 #define DEVID 0x20 /* Register: Device ID */
101 #define DEVREV 0x22 /* Register: Device Revision */
103 static inline void __superio_enter(int ioreg)
108 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
111 static inline int superio_inb(int ioreg, int reg)
116 val = inb(ioreg + 1);
121 static inline void superio_outb(int ioreg, int reg, int val)
124 outb(val, ioreg + 1);
127 static int superio_inw(int ioreg, int reg)
129 return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
132 static inline void superio_select(int ioreg, int ldn)
135 outb(ldn, ioreg + 1);
138 static inline int superio_enter(int ioreg)
141 * Try to reserve ioreg and ioreg + 1 for exclusive access.
143 if (!request_muxed_region(ioreg, 2, DRVNAME))
146 __superio_enter(ioreg);
153 static inline void superio_exit(int ioreg, bool doexit)
157 outb(0x02, ioreg + 1);
159 release_region(ioreg, 2);
162 /* Logical device 4 registers */
163 #define IT8712F_DEVID 0x8712
164 #define IT8705F_DEVID 0x8705
165 #define IT8716F_DEVID 0x8716
166 #define IT8718F_DEVID 0x8718
167 #define IT8720F_DEVID 0x8720
168 #define IT8721F_DEVID 0x8721
169 #define IT8726F_DEVID 0x8726
170 #define IT8728F_DEVID 0x8728
171 #define IT8732F_DEVID 0x8732
172 #define IT8792E_DEVID 0x8733
173 #define IT8771E_DEVID 0x8771
174 #define IT8772E_DEVID 0x8772
175 #define IT8781F_DEVID 0x8781
176 #define IT8782F_DEVID 0x8782
177 #define IT8783E_DEVID 0x8783
178 #define IT8786E_DEVID 0x8786
179 #define IT8790E_DEVID 0x8790
180 #define IT8603E_DEVID 0x8603
181 #define IT8607E_DEVID 0x8607
182 #define IT8613E_DEVID 0x8613
183 #define IT8620E_DEVID 0x8620
184 #define IT8622E_DEVID 0x8622
185 #define IT8623E_DEVID 0x8623
186 #define IT8625E_DEVID 0x8625
187 #define IT8628E_DEVID 0x8628
188 #define IT8655E_DEVID 0x8655
189 #define IT8665E_DEVID 0x8665
190 #define IT8686E_DEVID 0x8686
191 #define IT87_ACT_REG 0x30
192 #define IT87_BASE_REG 0x60
194 /* Logical device 7 registers (IT8712F and later) */
195 #define IT87_SIO_GPIO1_REG 0x25
196 #define IT87_SIO_GPIO2_REG 0x26
197 #define IT87_SIO_GPIO3_REG 0x27
198 #define IT87_SIO_GPIO4_REG 0x28
199 #define IT87_SIO_GPIO5_REG 0x29
200 #define IT87_SIO_GPIO9_REG 0xd3
201 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
202 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
203 #define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
204 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
205 #define IT87_SIO_VID_REG 0xfc /* VID value */
206 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
208 /* Update battery voltage after every reading if true */
209 static bool update_vbat;
211 /* Not all BIOSes properly configure the PWM registers */
212 static bool fix_pwm_polarity;
214 /* Many IT87 constants specified below */
216 /* Length of ISA address segment */
217 #define IT87_EXTENT 8
219 /* Length of ISA address segment for Environmental Controller */
220 #define IT87_EC_EXTENT 2
222 /* Offset of EC registers from ISA base address */
223 #define IT87_EC_OFFSET 5
225 /* Where are the ISA address/data registers relative to the EC base address */
226 #define IT87_ADDR_REG_OFFSET 0
227 #define IT87_DATA_REG_OFFSET 1
229 /*----- The IT87 registers -----*/
231 #define IT87_REG_CONFIG 0x00
233 #define IT87_REG_ALARM1 0x01
234 #define IT87_REG_ALARM2 0x02
235 #define IT87_REG_ALARM3 0x03
237 #define IT87_REG_BANK 0x06
240 * The IT8718F and IT8720F have the VID value in a different register, in
241 * Super-I/O configuration space.
243 #define IT87_REG_VID 0x0a
245 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
246 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
249 #define IT87_REG_FAN_DIV 0x0b
250 #define IT87_REG_FAN_16BIT 0x0c
254 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
255 * - up to 6 temp (1 to 6)
256 * - up to 6 fan (1 to 6)
259 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
260 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
261 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
262 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
264 static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
265 static const u8 IT87_REG_FAN_MIN_8665[] =
266 { 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
267 static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
268 static const u8 IT87_REG_FANX_MIN_8665[] =
269 { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
271 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
273 static const u8 IT87_REG_TEMP_OFFSET_8686[] = { 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
275 #define IT87_REG_FAN_MAIN_CTRL 0x13
276 #define IT87_REG_FAN_CTL 0x14
278 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
279 static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
281 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
283 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
284 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
286 #define IT87_REG_TEMP(nr) (0x29 + (nr))
288 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
289 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
291 static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
292 static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
294 static const u8 IT87_REG_TEMP_HIGH_8686[] =
295 { 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
296 static const u8 IT87_REG_TEMP_LOW_8686[] =
297 { 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
299 #define IT87_REG_VIN_ENABLE 0x50
300 #define IT87_REG_TEMP_ENABLE 0x51
301 #define IT87_REG_TEMP_EXTRA 0x55
302 #define IT87_REG_BEEP_ENABLE 0x5c
304 #define IT87_REG_CHIPID 0x58
306 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
308 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
309 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
311 #define IT87_REG_TEMP456_ENABLE 0x77
313 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
314 #define IT87_REG_TEMP_SRC2 0x23d
316 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
317 #define NUM_VIN_LIMIT 8
319 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
320 #define NUM_FAN_DIV 3
321 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
322 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
324 struct it87_devices {
326 const char * const suffix;
334 #define FEAT_12MV_ADC BIT(0)
335 #define FEAT_NEWER_AUTOPWM BIT(1)
336 #define FEAT_OLD_AUTOPWM BIT(2)
337 #define FEAT_16BIT_FANS BIT(3)
338 #define FEAT_TEMP_PECI BIT(5)
339 #define FEAT_TEMP_OLD_PECI BIT(6)
340 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
341 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
342 #define FEAT_VID BIT(9) /* Set if chip supports VID */
343 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
344 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
345 #define FEAT_10_9MV_ADC BIT(12)
346 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
347 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
348 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
349 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
350 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
351 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
352 #define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
353 #define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
354 #define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
355 #define FEAT_SCALING BIT(22) /* Internal voltage scaling */
356 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
357 #define FEAT_11MV_ADC BIT(24)
358 #define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
360 static const struct it87_devices it87_devices[] = {
364 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
365 /* may need to overwrite */
367 .num_temp_offset = 0,
372 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
373 /* may need to overwrite */
375 .num_temp_offset = 0,
380 .features = FEAT_16BIT_FANS | FEAT_VID
381 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
384 .num_temp_offset = 3,
389 .features = FEAT_16BIT_FANS | FEAT_VID
390 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
391 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
393 .num_temp_offset = 3,
394 .old_peci_mask = 0x4,
399 .features = FEAT_16BIT_FANS | FEAT_VID
400 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
401 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
403 .num_temp_offset = 3,
404 .old_peci_mask = 0x4,
409 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
410 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
411 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
412 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
414 .num_temp_offset = 3,
416 .old_peci_mask = 0x02, /* Actually reports PCH */
421 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
422 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
423 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
426 .num_temp_offset = 3,
432 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
433 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
434 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
435 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
437 .num_temp_offset = 3,
439 .old_peci_mask = 0x02, /* Actually reports PCH */
444 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
445 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
446 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
447 /* PECI: guesswork */
449 /* 16 bit fans (OHM) */
450 /* three fans, always 16 bit (guesswork) */
452 .num_temp_offset = 3,
458 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
459 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
460 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
461 /* PECI (coreboot) */
462 /* 12mV ADC (HWSensors4, OHM) */
463 /* 16 bit fans (HWSensors4, OHM) */
464 /* three fans, always 16 bit (datasheet) */
466 .num_temp_offset = 3,
472 .features = FEAT_16BIT_FANS
473 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
476 .num_temp_offset = 3,
477 .old_peci_mask = 0x4,
482 .features = FEAT_16BIT_FANS
483 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
486 .num_temp_offset = 3,
487 .old_peci_mask = 0x4,
492 .features = FEAT_16BIT_FANS
493 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
496 .num_temp_offset = 3,
497 .old_peci_mask = 0x4,
502 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
503 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
504 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
506 .num_temp_offset = 3,
512 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
513 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
514 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
516 .num_temp_offset = 3,
522 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
523 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
524 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
526 .num_temp_offset = 3,
532 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
533 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
534 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
536 .num_temp_offset = 3,
542 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
543 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
544 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
547 .num_temp_offset = 3,
553 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
554 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
555 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
556 | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
558 .num_temp_offset = 6,
564 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
565 | FEAT_TEMP_PECI | FEAT_SIX_FANS
566 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
567 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
570 .num_temp_offset = 3,
576 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
577 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
578 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
579 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
581 .num_temp_offset = 3,
587 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
588 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
589 | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
590 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
592 .num_temp_offset = 6,
597 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
598 | FEAT_TEMP_PECI | FEAT_SIX_FANS
599 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
600 | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
603 .num_temp_offset = 3,
609 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
610 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
611 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL,
613 .num_temp_offset = 6,
618 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
619 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
620 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
621 | FEAT_SIX_PWM | FEAT_BANK_SEL,
623 .num_temp_offset = 6,
628 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
629 | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
630 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
631 | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
633 .num_temp_offset = 6,
637 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
638 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
639 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
640 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
641 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
642 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
643 ((data)->peci_mask & BIT(nr)))
644 #define has_temp_old_peci(data, nr) \
645 (((data)->features & FEAT_TEMP_OLD_PECI) && \
646 ((data)->old_peci_mask & BIT(nr)))
647 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
648 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
650 #define has_vid(data) ((data)->features & FEAT_VID)
651 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
652 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
653 #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
654 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
656 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
657 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
658 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
659 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
660 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
663 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
666 #define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
667 #define has_scaling(data) ((data)->features & FEAT_SCALING)
668 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
669 #define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
670 #define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
672 struct it87_sio_data {
674 /* Values read from Super-I/O config space */
678 u8 internal; /* Internal sensors can be labeled */
679 /* Features skipped based on config or DMI */
688 * For each registered chip, we need to keep some data in memory.
689 * The structure is dynamically allocated.
692 const struct attribute_group *groups[7];
701 const u8 *REG_FAN_MIN;
702 const u8 *REG_FANX_MIN;
706 const u8 *REG_TEMP_OFFSET;
707 const u8 *REG_TEMP_LOW;
708 const u8 *REG_TEMP_HIGH;
712 struct mutex update_lock;
713 char valid; /* !=0 if following fields are valid */
714 unsigned long last_updated; /* In jiffies */
716 u16 in_scaled; /* Internal voltage sensors are scaled */
717 u16 in_internal; /* Bitfield, internal sensors (for labels) */
718 u16 has_in; /* Bitfield, voltage sensors enabled */
719 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
720 u8 has_fan; /* Bitfield, fans enabled */
721 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
722 u8 has_temp; /* Bitfield, temp sensors enabled */
723 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
724 u8 num_temp_limit; /* Number of temperature limit registers */
725 u8 num_temp_offset; /* Number of temperature offset registers */
726 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
727 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
728 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
729 bool has_vid; /* True if VID supported */
730 u8 vid; /* Register encoding, combined */
732 u32 alarms; /* Register encoding, combined */
733 bool has_beep; /* true if beep supported */
734 u8 beeps; /* Register encoding */
735 u8 fan_main_ctrl; /* Register value */
736 u8 fan_ctl; /* Register value */
739 * The following 3 arrays correspond to the same registers up to
740 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
741 * 7, and we want to preserve settings on mode changes, so we have
742 * to track all values separately.
743 * Starting with the IT8721F, the manual PWM duty cycles are stored
744 * in separate registers (8-bit values), so the separate tracking
745 * is no longer needed, but it is still done to keep the driver
748 u8 has_pwm; /* Bitfield, pwm control enabled */
749 u8 pwm_ctrl[NUM_PWM]; /* Register value */
750 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
751 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
753 /* Automatic fan speed control registers */
754 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
755 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
758 static int adc_lsb(const struct it87_data *data, int nr)
762 if (has_12mv_adc(data))
764 else if (has_10_9mv_adc(data))
766 else if (has_11mv_adc(data))
770 if (data->in_scaled & BIT(nr))
775 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
777 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
778 return clamp_val(val, 0, 255);
781 static int in_from_reg(const struct it87_data *data, int nr, int val)
783 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
786 static inline u8 FAN_TO_REG(long rpm, int div)
790 rpm = clamp_val(rpm, 1, 1000000);
791 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
794 static inline u16 FAN16_TO_REG(long rpm)
798 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
801 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
802 1350000 / ((val) * (div)))
803 /* The divider is fixed to 2 in 16-bit mode */
804 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
805 1350000 / ((val) * 2))
807 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
808 ((val) + 500) / 1000), -128, 127))
809 #define TEMP_FROM_REG(val) ((val) * 1000)
811 static u8 pwm_to_reg(const struct it87_data *data, long val)
813 if (has_newer_autopwm(data))
819 static int pwm_from_reg(const struct it87_data *data, u8 reg)
821 if (has_newer_autopwm(data))
824 return (reg & 0x7f) << 1;
827 static int DIV_TO_REG(int val)
831 while (answer < 7 && (val >>= 1))
836 #define DIV_FROM_REG(val) BIT(val)
839 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
840 * depending on the chip type, to calculate the actual PWM frequency.
842 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
843 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
844 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
845 * sometimes just one. It is unknown if this is a datasheet error or real,
846 * so this is ignored for now.
848 static const unsigned int pwm_freq[8] = {
859 static int _it87_read_value(struct it87_data *data, u8 reg)
861 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
862 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
865 static void _it87_write_value(struct it87_data *data, u8 reg, u8 value)
867 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
868 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
871 static void it87_set_bank(struct it87_data *data, u8 bank)
873 if (has_bank_sel(data) && bank != data->bank) {
874 u8 breg = _it87_read_value(data, IT87_REG_BANK);
879 _it87_write_value(data, IT87_REG_BANK, breg);
884 * Must be called with data->update_lock held, except during initialization.
885 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
886 * would slow down the IT87 access and should not be necessary.
888 static int it87_read_value(struct it87_data *data, u16 reg)
890 it87_set_bank(data, reg >> 8);
891 return _it87_read_value(data, reg & 0xff);
895 * Must be called with data->update_lock held, except during initialization.
896 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
897 * would slow down the IT87 access and should not be necessary.
899 static void it87_write_value(struct it87_data *data, u16 reg, u8 value)
901 it87_set_bank(data, reg >> 8);
902 _it87_write_value(data, reg & 0xff, value);
905 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
907 data->pwm_ctrl[nr] = it87_read_value(data, data->REG_PWM[nr]);
908 if (has_newer_autopwm(data)) {
909 if (has_new_tempmap(data))
910 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x38;
912 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
913 data->pwm_duty[nr] = it87_read_value(data,
914 IT87_REG_PWM_DUTY[nr]);
916 if (data->pwm_ctrl[nr] & 0x80) /* Automatic mode */
917 data->pwm_temp_map[nr] = data->pwm_ctrl[nr] & 0x03;
918 else /* Manual mode */
919 data->pwm_duty[nr] = data->pwm_ctrl[nr] & 0x7f;
922 if (has_old_autopwm(data)) {
925 for (i = 0; i < 5 ; i++)
926 data->auto_temp[nr][i] = it87_read_value(data,
927 IT87_REG_AUTO_TEMP(nr, i));
928 for (i = 0; i < 3 ; i++)
929 data->auto_pwm[nr][i] = it87_read_value(data,
930 IT87_REG_AUTO_PWM(nr, i));
931 } else if (has_newer_autopwm(data)) {
935 * 0: temperature hysteresis (base + 5)
936 * 1: fan off temperature (base + 0)
937 * 2: fan start temperature (base + 1)
938 * 3: fan max temperature (base + 2)
940 data->auto_temp[nr][0] =
941 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 5));
943 for (i = 0; i < 3 ; i++)
944 data->auto_temp[nr][i + 1] =
945 it87_read_value(data,
946 IT87_REG_AUTO_TEMP(nr, i));
948 * 0: start pwm value (base + 3)
949 * 1: pwm slope (base + 4, 1/8th pwm)
951 data->auto_pwm[nr][0] =
952 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 3));
953 data->auto_pwm[nr][1] =
954 it87_read_value(data, IT87_REG_AUTO_TEMP(nr, 4));
958 static struct it87_data *it87_update_device(struct device *dev)
960 struct it87_data *data = dev_get_drvdata(dev);
963 mutex_lock(&data->update_lock);
965 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
969 * Cleared after each update, so reenable. Value
970 * returned by this read will be previous value
972 it87_write_value(data, IT87_REG_CONFIG,
973 it87_read_value(data, IT87_REG_CONFIG) | 0x40);
975 for (i = 0; i < NUM_VIN; i++) {
976 if (!(data->has_in & BIT(i)))
980 it87_read_value(data, IT87_REG_VIN[i]);
982 /* VBAT and AVCC don't have limit registers */
983 if (i >= NUM_VIN_LIMIT)
987 it87_read_value(data, IT87_REG_VIN_MIN(i));
989 it87_read_value(data, IT87_REG_VIN_MAX(i));
992 for (i = 0; i < NUM_FAN; i++) {
993 /* Skip disabled fans */
994 if (!(data->has_fan & BIT(i)))
998 it87_read_value(data, data->REG_FAN_MIN[i]);
999 data->fan[i][0] = it87_read_value(data,
1001 /* Add high byte if in 16-bit mode */
1002 if (has_16bit_fans(data)) {
1003 data->fan[i][0] |= it87_read_value(data,
1004 data->REG_FANX[i]) << 8;
1005 data->fan[i][1] |= it87_read_value(data,
1006 data->REG_FANX_MIN[i]) << 8;
1009 for (i = 0; i < NUM_TEMP; i++) {
1010 if (!(data->has_temp & BIT(i)))
1013 it87_read_value(data, IT87_REG_TEMP(i));
1015 if (i >= data->num_temp_limit)
1018 if (i < data->num_temp_offset)
1020 it87_read_value(data,
1021 data->REG_TEMP_OFFSET[i]);
1024 it87_read_value(data, data->REG_TEMP_LOW[i]);
1026 it87_read_value(data, data->REG_TEMP_HIGH[i]);
1029 /* Newer chips don't have clock dividers */
1030 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1031 i = it87_read_value(data, IT87_REG_FAN_DIV);
1032 data->fan_div[0] = i & 0x07;
1033 data->fan_div[1] = (i >> 3) & 0x07;
1034 data->fan_div[2] = (i & 0x40) ? 3 : 1;
1038 it87_read_value(data, IT87_REG_ALARM1) |
1039 (it87_read_value(data, IT87_REG_ALARM2) << 8) |
1040 (it87_read_value(data, IT87_REG_ALARM3) << 16);
1041 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1043 data->fan_main_ctrl = it87_read_value(data,
1044 IT87_REG_FAN_MAIN_CTRL);
1045 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL);
1046 for (i = 0; i < NUM_PWM; i++) {
1047 if (!(data->has_pwm & BIT(i)))
1049 it87_update_pwm_ctrl(data, i);
1052 data->sensor = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1053 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1055 * The IT8705F does not have VID capability.
1056 * The IT8718F and later don't use IT87_REG_VID for the
1059 if (data->type == it8712 || data->type == it8716) {
1060 data->vid = it87_read_value(data, IT87_REG_VID);
1062 * The older IT8712F revisions had only 5 VID pins,
1063 * but we assume it is always safe to read 6 bits.
1067 data->last_updated = jiffies;
1071 mutex_unlock(&data->update_lock);
1076 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1079 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1080 struct it87_data *data = it87_update_device(dev);
1081 int index = sattr->index;
1084 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1087 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1088 const char *buf, size_t count)
1090 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1091 struct it87_data *data = dev_get_drvdata(dev);
1092 int index = sattr->index;
1096 if (kstrtoul(buf, 10, &val) < 0)
1099 mutex_lock(&data->update_lock);
1100 data->in[nr][index] = in_to_reg(data, nr, val);
1101 it87_write_value(data,
1102 index == 1 ? IT87_REG_VIN_MIN(nr)
1103 : IT87_REG_VIN_MAX(nr),
1104 data->in[nr][index]);
1105 mutex_unlock(&data->update_lock);
1109 static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, 0);
1110 static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
1112 static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
1115 static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, 0);
1116 static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
1118 static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
1121 static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, 0);
1122 static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
1124 static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
1127 static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, 0);
1128 static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
1130 static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
1133 static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, 0);
1134 static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
1136 static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
1139 static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, 0);
1140 static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
1142 static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
1145 static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO, show_in, NULL, 6, 0);
1146 static SENSOR_DEVICE_ATTR_2(in6_min, S_IRUGO | S_IWUSR, show_in, set_in,
1148 static SENSOR_DEVICE_ATTR_2(in6_max, S_IRUGO | S_IWUSR, show_in, set_in,
1151 static SENSOR_DEVICE_ATTR_2(in7_input, S_IRUGO, show_in, NULL, 7, 0);
1152 static SENSOR_DEVICE_ATTR_2(in7_min, S_IRUGO | S_IWUSR, show_in, set_in,
1154 static SENSOR_DEVICE_ATTR_2(in7_max, S_IRUGO | S_IWUSR, show_in, set_in,
1157 static SENSOR_DEVICE_ATTR_2(in8_input, S_IRUGO, show_in, NULL, 8, 0);
1158 static SENSOR_DEVICE_ATTR_2(in9_input, S_IRUGO, show_in, NULL, 9, 0);
1159 static SENSOR_DEVICE_ATTR_2(in10_input, S_IRUGO, show_in, NULL, 10, 0);
1160 static SENSOR_DEVICE_ATTR_2(in11_input, S_IRUGO, show_in, NULL, 11, 0);
1161 static SENSOR_DEVICE_ATTR_2(in12_input, S_IRUGO, show_in, NULL, 12, 0);
1163 /* Up to 6 temperatures */
1164 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1167 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1169 int index = sattr->index;
1170 struct it87_data *data = it87_update_device(dev);
1172 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1175 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1176 const char *buf, size_t count)
1178 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1180 int index = sattr->index;
1181 struct it87_data *data = dev_get_drvdata(dev);
1185 if (kstrtol(buf, 10, &val) < 0)
1188 mutex_lock(&data->update_lock);
1193 reg = data->REG_TEMP_LOW[nr];
1196 reg = data->REG_TEMP_HIGH[nr];
1199 regval = it87_read_value(data, IT87_REG_BEEP_ENABLE);
1200 if (!(regval & 0x80)) {
1202 it87_write_value(data, IT87_REG_BEEP_ENABLE, regval);
1205 reg = data->REG_TEMP_OFFSET[nr];
1209 data->temp[nr][index] = TEMP_TO_REG(val);
1210 it87_write_value(data, reg, data->temp[nr][index]);
1211 mutex_unlock(&data->update_lock);
1215 static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, 0);
1216 static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1218 static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1220 static SENSOR_DEVICE_ATTR_2(temp1_offset, S_IRUGO | S_IWUSR, show_temp,
1222 static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, 0);
1223 static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1225 static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1227 static SENSOR_DEVICE_ATTR_2(temp2_offset, S_IRUGO | S_IWUSR, show_temp,
1229 static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, 0);
1230 static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1232 static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1234 static SENSOR_DEVICE_ATTR_2(temp3_offset, S_IRUGO | S_IWUSR, show_temp,
1236 static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, 0);
1237 static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1239 static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1241 static SENSOR_DEVICE_ATTR_2(temp4_offset, S_IRUGO | S_IWUSR, show_temp,
1243 static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, 0);
1244 static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1246 static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1248 static SENSOR_DEVICE_ATTR_2(temp5_offset, S_IRUGO | S_IWUSR, show_temp,
1250 static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, 0);
1251 static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
1253 static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
1255 static SENSOR_DEVICE_ATTR_2(temp6_offset, S_IRUGO | S_IWUSR, show_temp,
1258 static int get_temp_type(struct it87_data *data, int index)
1263 if (has_bank_sel(data)) {
1264 int s1reg = IT87_REG_TEMP_SRC1[index/2] >> ((index % 2) * 4);
1267 src1 = (it87_read_value(data, s1reg) >> ((index % 2) * 4)) & 0x0f;
1268 src2 = it87_read_value(data, IT87_REG_TEMP_SRC2);
1270 switch (data->type) {
1278 if (index == 1 || index == 2 ||
1279 index == 4 || index == 5)
1283 if (index == 2 || index == 6)
1301 type = (src2 & BIT(index)) ? 6 : 5;
1304 type = (src2 & BIT(index)) ? 4 : 6;
1307 type = (src2 & BIT(index)) ? 5 : 0;
1320 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1321 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1323 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1324 (has_temp_old_peci(data, index) && (extra & 0x80)))
1325 type = 6; /* Intel PECI */
1326 if (reg & BIT(index))
1327 type = 3; /* thermal diode */
1328 else if (reg & BIT(index + 3))
1329 type = 4; /* thermistor */
1334 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1337 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1338 struct it87_data *data = it87_update_device(dev);
1339 int type = get_temp_type(data, sensor_attr->index);
1341 return sprintf(buf, "%d\n", type);
1344 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1345 const char *buf, size_t count)
1347 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1348 int nr = sensor_attr->index;
1350 struct it87_data *data = dev_get_drvdata(dev);
1354 if (kstrtol(buf, 10, &val) < 0)
1357 reg = it87_read_value(data, IT87_REG_TEMP_ENABLE);
1360 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1362 extra = it87_read_value(data, IT87_REG_TEMP_EXTRA);
1363 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1365 if (val == 2) { /* backwards compatibility */
1367 "Sensor type 2 is deprecated, please use 4 instead\n");
1370 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1375 else if (has_temp_peci(data, nr) && val == 6)
1376 reg |= (nr + 1) << 6;
1377 else if (has_temp_old_peci(data, nr) && val == 6)
1382 mutex_lock(&data->update_lock);
1384 data->extra = extra;
1385 it87_write_value(data, IT87_REG_TEMP_ENABLE, data->sensor);
1386 if (has_temp_old_peci(data, nr))
1387 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1388 data->valid = 0; /* Force cache refresh */
1389 mutex_unlock(&data->update_lock);
1393 static SENSOR_DEVICE_ATTR(temp1_type, S_IRUGO | S_IWUSR, show_temp_type,
1395 static SENSOR_DEVICE_ATTR(temp2_type, S_IRUGO | S_IWUSR, show_temp_type,
1397 static SENSOR_DEVICE_ATTR(temp3_type, S_IRUGO | S_IWUSR, show_temp_type,
1399 static SENSOR_DEVICE_ATTR(temp4_type, S_IRUGO | S_IWUSR, show_temp_type,
1401 static SENSOR_DEVICE_ATTR(temp5_type, S_IRUGO | S_IWUSR, show_temp_type,
1403 static SENSOR_DEVICE_ATTR(temp6_type, S_IRUGO | S_IWUSR, show_temp_type,
1408 static int pwm_mode(const struct it87_data *data, int nr)
1410 if (has_fanctl_onoff(data) && nr < 3 &&
1411 !(data->fan_main_ctrl & BIT(nr)))
1412 return 0; /* Full speed */
1413 if (data->pwm_ctrl[nr] & 0x80)
1414 return 2; /* Automatic mode */
1415 if ((!has_fanctl_onoff(data) || nr >= 3) &&
1416 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1417 return 0; /* Full speed */
1419 return 1; /* Manual mode */
1422 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1425 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1427 int index = sattr->index;
1429 struct it87_data *data = it87_update_device(dev);
1431 speed = has_16bit_fans(data) ?
1432 FAN16_FROM_REG(data->fan[nr][index]) :
1433 FAN_FROM_REG(data->fan[nr][index],
1434 DIV_FROM_REG(data->fan_div[nr]));
1435 return sprintf(buf, "%d\n", speed);
1438 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1441 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1442 struct it87_data *data = it87_update_device(dev);
1443 int nr = sensor_attr->index;
1445 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1448 static ssize_t show_pwm_enable(struct device *dev,
1449 struct device_attribute *attr, char *buf)
1451 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1452 struct it87_data *data = it87_update_device(dev);
1453 int nr = sensor_attr->index;
1455 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1458 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1461 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1462 struct it87_data *data = it87_update_device(dev);
1463 int nr = sensor_attr->index;
1465 return sprintf(buf, "%d\n",
1466 pwm_from_reg(data, data->pwm_duty[nr]));
1469 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1472 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1473 struct it87_data *data = it87_update_device(dev);
1474 int nr = sensor_attr->index;
1478 if (has_pwm_freq2(data) && nr == 1)
1479 index = (data->extra >> 4) & 0x07;
1481 index = (data->fan_ctl >> 4) & 0x07;
1483 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1485 return sprintf(buf, "%u\n", freq);
1488 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1489 const char *buf, size_t count)
1491 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1493 int index = sattr->index;
1495 struct it87_data *data = dev_get_drvdata(dev);
1499 if (kstrtol(buf, 10, &val) < 0)
1502 mutex_lock(&data->update_lock);
1504 if (has_16bit_fans(data)) {
1505 data->fan[nr][index] = FAN16_TO_REG(val);
1506 it87_write_value(data, data->REG_FAN_MIN[nr],
1507 data->fan[nr][index] & 0xff);
1508 it87_write_value(data, data->REG_FANX_MIN[nr],
1509 data->fan[nr][index] >> 8);
1511 reg = it87_read_value(data, IT87_REG_FAN_DIV);
1514 data->fan_div[nr] = reg & 0x07;
1517 data->fan_div[nr] = (reg >> 3) & 0x07;
1520 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1523 data->fan[nr][index] =
1524 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1525 it87_write_value(data, data->REG_FAN_MIN[nr],
1526 data->fan[nr][index]);
1529 mutex_unlock(&data->update_lock);
1533 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1534 const char *buf, size_t count)
1536 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1537 struct it87_data *data = dev_get_drvdata(dev);
1538 int nr = sensor_attr->index;
1543 if (kstrtoul(buf, 10, &val) < 0)
1546 mutex_lock(&data->update_lock);
1547 old = it87_read_value(data, IT87_REG_FAN_DIV);
1549 /* Save fan min limit */
1550 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1555 data->fan_div[nr] = DIV_TO_REG(val);
1559 data->fan_div[nr] = 1;
1561 data->fan_div[nr] = 3;
1564 val |= (data->fan_div[0] & 0x07);
1565 val |= (data->fan_div[1] & 0x07) << 3;
1566 if (data->fan_div[2] == 3)
1568 it87_write_value(data, IT87_REG_FAN_DIV, val);
1570 /* Restore fan min limit */
1571 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1572 it87_write_value(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1574 mutex_unlock(&data->update_lock);
1578 /* Returns 0 if OK, -EINVAL otherwise */
1579 static int check_trip_points(struct device *dev, int nr)
1581 const struct it87_data *data = dev_get_drvdata(dev);
1584 if (has_old_autopwm(data)) {
1585 for (i = 0; i < 3; i++) {
1586 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1589 for (i = 0; i < 2; i++) {
1590 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1593 } else if (has_newer_autopwm(data)) {
1594 for (i = 1; i < 3; i++) {
1595 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1602 "Inconsistent trip points, not switching to automatic mode\n");
1603 dev_err(dev, "Adjust the trip points and try again\n");
1608 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1609 const char *buf, size_t count)
1611 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1612 struct it87_data *data = dev_get_drvdata(dev);
1613 int nr = sensor_attr->index;
1616 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1619 /* Check trip points before switching to automatic mode */
1621 if (check_trip_points(dev, nr) < 0)
1625 mutex_lock(&data->update_lock);
1626 it87_update_pwm_ctrl(data, nr);
1629 if (nr < 3 && has_fanctl_onoff(data)) {
1631 /* make sure the fan is on when in on/off mode */
1632 tmp = it87_read_value(data, IT87_REG_FAN_CTL);
1633 it87_write_value(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1634 /* set on/off mode */
1635 data->fan_main_ctrl &= ~BIT(nr);
1636 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1637 data->fan_main_ctrl);
1641 /* No on/off mode, set maximum pwm value */
1642 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1643 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1644 data->pwm_duty[nr]);
1645 /* and set manual mode */
1646 if (has_newer_autopwm(data)) {
1647 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1648 data->pwm_temp_map[nr];
1650 ctrl = data->pwm_duty[nr];
1652 data->pwm_ctrl[nr] = ctrl;
1653 it87_write_value(data, data->REG_PWM[nr], ctrl);
1658 if (has_newer_autopwm(data)) {
1659 ctrl = (data->pwm_ctrl[nr] & 0x7c) |
1660 data->pwm_temp_map[nr];
1664 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1666 data->pwm_ctrl[nr] = ctrl;
1667 it87_write_value(data, data->REG_PWM[nr], ctrl);
1669 if (has_fanctl_onoff(data) && nr < 3) {
1670 /* set SmartGuardian mode */
1671 data->fan_main_ctrl |= BIT(nr);
1672 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
1673 data->fan_main_ctrl);
1677 mutex_unlock(&data->update_lock);
1681 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1682 const char *buf, size_t count)
1684 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1685 struct it87_data *data = dev_get_drvdata(dev);
1686 int nr = sensor_attr->index;
1689 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1692 mutex_lock(&data->update_lock);
1693 it87_update_pwm_ctrl(data, nr);
1694 if (has_newer_autopwm(data)) {
1696 * If we are in automatic mode, the PWM duty cycle register
1697 * is read-only so we can't write the value.
1699 if (data->pwm_ctrl[nr] & 0x80) {
1700 mutex_unlock(&data->update_lock);
1703 data->pwm_duty[nr] = pwm_to_reg(data, val);
1704 it87_write_value(data, IT87_REG_PWM_DUTY[nr],
1705 data->pwm_duty[nr]);
1707 data->pwm_duty[nr] = pwm_to_reg(data, val);
1709 * If we are in manual mode, write the duty cycle immediately;
1710 * otherwise, just store it for later use.
1712 if (!(data->pwm_ctrl[nr] & 0x80)) {
1713 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1714 it87_write_value(data, data->REG_PWM[nr],
1715 data->pwm_ctrl[nr]);
1718 mutex_unlock(&data->update_lock);
1722 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1723 const char *buf, size_t count)
1725 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1726 struct it87_data *data = dev_get_drvdata(dev);
1727 int nr = sensor_attr->index;
1731 if (kstrtoul(buf, 10, &val) < 0)
1734 val = clamp_val(val, 0, 1000000);
1735 val *= has_newer_autopwm(data) ? 256 : 128;
1737 /* Search for the nearest available frequency */
1738 for (i = 0; i < 7; i++) {
1739 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1743 mutex_lock(&data->update_lock);
1745 data->fan_ctl = it87_read_value(data, IT87_REG_FAN_CTL) & 0x8f;
1746 data->fan_ctl |= i << 4;
1747 it87_write_value(data, IT87_REG_FAN_CTL, data->fan_ctl);
1749 data->extra = it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1750 data->extra |= i << 4;
1751 it87_write_value(data, IT87_REG_TEMP_EXTRA, data->extra);
1753 mutex_unlock(&data->update_lock);
1758 static ssize_t show_pwm_temp_map(struct device *dev,
1759 struct device_attribute *attr, char *buf)
1761 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1762 struct it87_data *data = it87_update_device(dev);
1763 int nr = sensor_attr->index;
1766 map = data->pwm_temp_map[nr];
1767 if (has_new_tempmap(data)) {
1770 map = 0; /* Should never happen */
1773 map = 0; /* Should never happen */
1774 if (nr >= 3) /* pwm channels 3..6 map to temp4..6 */
1778 return sprintf(buf, "%d\n", (int)BIT(map));
1781 static ssize_t set_pwm_temp_map(struct device *dev,
1782 struct device_attribute *attr, const char *buf,
1785 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1786 struct it87_data *data = dev_get_drvdata(dev);
1787 int nr = sensor_attr->index;
1791 if (kstrtol(buf, 10, &val) < 0)
1794 if (nr >= 3 && !has_new_tempmap(data))
1823 if (has_new_tempmap(data))
1825 else if (reg > 0x02)
1828 mutex_lock(&data->update_lock);
1829 it87_update_pwm_ctrl(data, nr);
1830 data->pwm_temp_map[nr] = reg;
1832 * If we are in automatic mode, write the temp mapping immediately;
1833 * otherwise, just store it for later use.
1835 if (data->pwm_ctrl[nr] & 0x80) {
1836 u8 mask = has_new_tempmap(data) ? 0xc7 : 0xfc;
1838 data->pwm_ctrl[nr] = (data->pwm_ctrl[nr] & mask) |
1839 data->pwm_temp_map[nr];
1840 it87_write_value(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
1842 mutex_unlock(&data->update_lock);
1846 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
1849 struct it87_data *data = it87_update_device(dev);
1850 struct sensor_device_attribute_2 *sensor_attr =
1851 to_sensor_dev_attr_2(attr);
1852 int nr = sensor_attr->nr;
1853 int point = sensor_attr->index;
1855 return sprintf(buf, "%d\n",
1856 pwm_from_reg(data, data->auto_pwm[nr][point]));
1859 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
1860 const char *buf, size_t count)
1862 struct it87_data *data = dev_get_drvdata(dev);
1863 struct sensor_device_attribute_2 *sensor_attr =
1864 to_sensor_dev_attr_2(attr);
1865 int nr = sensor_attr->nr;
1866 int point = sensor_attr->index;
1870 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1873 mutex_lock(&data->update_lock);
1874 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
1875 if (has_newer_autopwm(data))
1876 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
1878 regaddr = IT87_REG_AUTO_PWM(nr, point);
1879 it87_write_value(data, regaddr, data->auto_pwm[nr][point]);
1880 mutex_unlock(&data->update_lock);
1884 static ssize_t show_auto_pwm_slope(struct device *dev,
1885 struct device_attribute *attr, char *buf)
1887 struct it87_data *data = it87_update_device(dev);
1888 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1889 int nr = sensor_attr->index;
1891 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
1894 static ssize_t set_auto_pwm_slope(struct device *dev,
1895 struct device_attribute *attr,
1896 const char *buf, size_t count)
1898 struct it87_data *data = dev_get_drvdata(dev);
1899 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1900 int nr = sensor_attr->index;
1903 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
1906 mutex_lock(&data->update_lock);
1907 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
1908 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 4),
1909 data->auto_pwm[nr][1]);
1910 mutex_unlock(&data->update_lock);
1914 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
1917 struct it87_data *data = it87_update_device(dev);
1918 struct sensor_device_attribute_2 *sensor_attr =
1919 to_sensor_dev_attr_2(attr);
1920 int nr = sensor_attr->nr;
1921 int point = sensor_attr->index;
1924 if (has_old_autopwm(data) || point)
1925 reg = data->auto_temp[nr][point];
1927 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
1929 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
1932 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
1933 const char *buf, size_t count)
1935 struct it87_data *data = dev_get_drvdata(dev);
1936 struct sensor_device_attribute_2 *sensor_attr =
1937 to_sensor_dev_attr_2(attr);
1938 int nr = sensor_attr->nr;
1939 int point = sensor_attr->index;
1943 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
1946 mutex_lock(&data->update_lock);
1947 if (has_newer_autopwm(data) && !point) {
1948 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
1949 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
1950 data->auto_temp[nr][0] = reg;
1951 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
1953 reg = TEMP_TO_REG(val);
1954 data->auto_temp[nr][point] = reg;
1955 if (has_newer_autopwm(data))
1957 it87_write_value(data, IT87_REG_AUTO_TEMP(nr, point), reg);
1959 mutex_unlock(&data->update_lock);
1963 static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, 0);
1964 static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1966 static SENSOR_DEVICE_ATTR(fan1_div, S_IRUGO | S_IWUSR, show_fan_div,
1969 static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, 0);
1970 static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1972 static SENSOR_DEVICE_ATTR(fan2_div, S_IRUGO | S_IWUSR, show_fan_div,
1975 static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, 0);
1976 static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1978 static SENSOR_DEVICE_ATTR(fan3_div, S_IRUGO | S_IWUSR, show_fan_div,
1981 static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, 0);
1982 static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1985 static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, 0);
1986 static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1989 static SENSOR_DEVICE_ATTR_2(fan6_input, S_IRUGO, show_fan, NULL, 5, 0);
1990 static SENSOR_DEVICE_ATTR_2(fan6_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
1993 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR,
1994 show_pwm_enable, set_pwm_enable, 0);
1995 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 0);
1996 static SENSOR_DEVICE_ATTR(pwm1_freq, S_IRUGO | S_IWUSR, show_pwm_freq,
1998 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, S_IRUGO,
1999 show_pwm_temp_map, set_pwm_temp_map, 0);
2000 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, S_IRUGO | S_IWUSR,
2001 show_auto_pwm, set_auto_pwm, 0, 0);
2002 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, S_IRUGO | S_IWUSR,
2003 show_auto_pwm, set_auto_pwm, 0, 1);
2004 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, S_IRUGO | S_IWUSR,
2005 show_auto_pwm, set_auto_pwm, 0, 2);
2006 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, S_IRUGO,
2007 show_auto_pwm, NULL, 0, 3);
2008 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, S_IRUGO | S_IWUSR,
2009 show_auto_temp, set_auto_temp, 0, 1);
2010 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2011 show_auto_temp, set_auto_temp, 0, 0);
2012 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, S_IRUGO | S_IWUSR,
2013 show_auto_temp, set_auto_temp, 0, 2);
2014 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, S_IRUGO | S_IWUSR,
2015 show_auto_temp, set_auto_temp, 0, 3);
2016 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, S_IRUGO | S_IWUSR,
2017 show_auto_temp, set_auto_temp, 0, 4);
2018 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, S_IRUGO | S_IWUSR,
2019 show_auto_pwm, set_auto_pwm, 0, 0);
2020 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, S_IRUGO | S_IWUSR,
2021 show_auto_pwm_slope, set_auto_pwm_slope, 0);
2023 static SENSOR_DEVICE_ATTR(pwm2_enable, S_IRUGO | S_IWUSR,
2024 show_pwm_enable, set_pwm_enable, 1);
2025 static SENSOR_DEVICE_ATTR(pwm2, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 1);
2026 static SENSOR_DEVICE_ATTR(pwm2_freq, S_IRUGO, show_pwm_freq, set_pwm_freq, 1);
2027 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, S_IRUGO,
2028 show_pwm_temp_map, set_pwm_temp_map, 1);
2029 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, S_IRUGO | S_IWUSR,
2030 show_auto_pwm, set_auto_pwm, 1, 0);
2031 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, S_IRUGO | S_IWUSR,
2032 show_auto_pwm, set_auto_pwm, 1, 1);
2033 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, S_IRUGO | S_IWUSR,
2034 show_auto_pwm, set_auto_pwm, 1, 2);
2035 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, S_IRUGO,
2036 show_auto_pwm, NULL, 1, 3);
2037 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, S_IRUGO | S_IWUSR,
2038 show_auto_temp, set_auto_temp, 1, 1);
2039 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2040 show_auto_temp, set_auto_temp, 1, 0);
2041 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, S_IRUGO | S_IWUSR,
2042 show_auto_temp, set_auto_temp, 1, 2);
2043 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, S_IRUGO | S_IWUSR,
2044 show_auto_temp, set_auto_temp, 1, 3);
2045 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, S_IRUGO | S_IWUSR,
2046 show_auto_temp, set_auto_temp, 1, 4);
2047 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, S_IRUGO | S_IWUSR,
2048 show_auto_pwm, set_auto_pwm, 1, 0);
2049 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, S_IRUGO | S_IWUSR,
2050 show_auto_pwm_slope, set_auto_pwm_slope, 1);
2052 static SENSOR_DEVICE_ATTR(pwm3_enable, S_IRUGO | S_IWUSR,
2053 show_pwm_enable, set_pwm_enable, 2);
2054 static SENSOR_DEVICE_ATTR(pwm3, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 2);
2055 static SENSOR_DEVICE_ATTR(pwm3_freq, S_IRUGO, show_pwm_freq, NULL, 2);
2056 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, S_IRUGO,
2057 show_pwm_temp_map, set_pwm_temp_map, 2);
2058 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, S_IRUGO | S_IWUSR,
2059 show_auto_pwm, set_auto_pwm, 2, 0);
2060 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, S_IRUGO | S_IWUSR,
2061 show_auto_pwm, set_auto_pwm, 2, 1);
2062 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, S_IRUGO | S_IWUSR,
2063 show_auto_pwm, set_auto_pwm, 2, 2);
2064 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, S_IRUGO,
2065 show_auto_pwm, NULL, 2, 3);
2066 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, S_IRUGO | S_IWUSR,
2067 show_auto_temp, set_auto_temp, 2, 1);
2068 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2069 show_auto_temp, set_auto_temp, 2, 0);
2070 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, S_IRUGO | S_IWUSR,
2071 show_auto_temp, set_auto_temp, 2, 2);
2072 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, S_IRUGO | S_IWUSR,
2073 show_auto_temp, set_auto_temp, 2, 3);
2074 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, S_IRUGO | S_IWUSR,
2075 show_auto_temp, set_auto_temp, 2, 4);
2076 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, S_IRUGO | S_IWUSR,
2077 show_auto_pwm, set_auto_pwm, 2, 0);
2078 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, S_IRUGO | S_IWUSR,
2079 show_auto_pwm_slope, set_auto_pwm_slope, 2);
2081 static SENSOR_DEVICE_ATTR(pwm4_enable, S_IRUGO | S_IWUSR,
2082 show_pwm_enable, set_pwm_enable, 3);
2083 static SENSOR_DEVICE_ATTR(pwm4, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 3);
2084 static SENSOR_DEVICE_ATTR(pwm4_freq, S_IRUGO, show_pwm_freq, NULL, 3);
2085 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, S_IRUGO,
2086 show_pwm_temp_map, set_pwm_temp_map, 3);
2087 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, S_IRUGO | S_IWUSR,
2088 show_auto_temp, set_auto_temp, 2, 1);
2089 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2090 show_auto_temp, set_auto_temp, 2, 0);
2091 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, S_IRUGO | S_IWUSR,
2092 show_auto_temp, set_auto_temp, 2, 2);
2093 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, S_IRUGO | S_IWUSR,
2094 show_auto_temp, set_auto_temp, 2, 3);
2095 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, S_IRUGO | S_IWUSR,
2096 show_auto_pwm, set_auto_pwm, 3, 0);
2097 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, S_IRUGO | S_IWUSR,
2098 show_auto_pwm_slope, set_auto_pwm_slope, 3);
2100 static SENSOR_DEVICE_ATTR(pwm5_enable, S_IRUGO | S_IWUSR,
2101 show_pwm_enable, set_pwm_enable, 4);
2102 static SENSOR_DEVICE_ATTR(pwm5, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 4);
2103 static SENSOR_DEVICE_ATTR(pwm5_freq, S_IRUGO, show_pwm_freq, NULL, 4);
2104 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, S_IRUGO,
2105 show_pwm_temp_map, set_pwm_temp_map, 4);
2106 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, S_IRUGO | S_IWUSR,
2107 show_auto_temp, set_auto_temp, 2, 1);
2108 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2109 show_auto_temp, set_auto_temp, 2, 0);
2110 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, S_IRUGO | S_IWUSR,
2111 show_auto_temp, set_auto_temp, 2, 2);
2112 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, S_IRUGO | S_IWUSR,
2113 show_auto_temp, set_auto_temp, 2, 3);
2114 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, S_IRUGO | S_IWUSR,
2115 show_auto_pwm, set_auto_pwm, 4, 0);
2116 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, S_IRUGO | S_IWUSR,
2117 show_auto_pwm_slope, set_auto_pwm_slope, 4);
2119 static SENSOR_DEVICE_ATTR(pwm6_enable, S_IRUGO | S_IWUSR,
2120 show_pwm_enable, set_pwm_enable, 5);
2121 static SENSOR_DEVICE_ATTR(pwm6, S_IRUGO | S_IWUSR, show_pwm, set_pwm, 5);
2122 static SENSOR_DEVICE_ATTR(pwm6_freq, S_IRUGO, show_pwm_freq, NULL, 5);
2123 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, S_IRUGO,
2124 show_pwm_temp_map, set_pwm_temp_map, 5);
2125 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, S_IRUGO | S_IWUSR,
2126 show_auto_temp, set_auto_temp, 2, 1);
2127 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, S_IRUGO | S_IWUSR,
2128 show_auto_temp, set_auto_temp, 2, 0);
2129 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, S_IRUGO | S_IWUSR,
2130 show_auto_temp, set_auto_temp, 2, 2);
2131 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, S_IRUGO | S_IWUSR,
2132 show_auto_temp, set_auto_temp, 2, 3);
2133 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, S_IRUGO | S_IWUSR,
2134 show_auto_pwm, set_auto_pwm, 5, 0);
2135 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, S_IRUGO | S_IWUSR,
2136 show_auto_pwm_slope, set_auto_pwm_slope, 5);
2139 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2142 struct it87_data *data = it87_update_device(dev);
2144 return sprintf(buf, "%u\n", data->alarms);
2146 static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
2148 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2151 struct it87_data *data = it87_update_device(dev);
2152 int bitnr = to_sensor_dev_attr(attr)->index;
2154 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2157 static ssize_t clear_intrusion(struct device *dev,
2158 struct device_attribute *attr, const char *buf,
2161 struct it87_data *data = dev_get_drvdata(dev);
2165 if (kstrtol(buf, 10, &val) < 0 || val != 0)
2168 mutex_lock(&data->update_lock);
2169 config = it87_read_value(data, IT87_REG_CONFIG);
2174 it87_write_value(data, IT87_REG_CONFIG, config);
2175 /* Invalidate cache to force re-read */
2178 mutex_unlock(&data->update_lock);
2183 static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, show_alarm, NULL, 8);
2184 static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, show_alarm, NULL, 9);
2185 static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, show_alarm, NULL, 10);
2186 static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, show_alarm, NULL, 11);
2187 static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, show_alarm, NULL, 12);
2188 static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, show_alarm, NULL, 13);
2189 static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, show_alarm, NULL, 14);
2190 static SENSOR_DEVICE_ATTR(in7_alarm, S_IRUGO, show_alarm, NULL, 15);
2191 static SENSOR_DEVICE_ATTR(fan1_alarm, S_IRUGO, show_alarm, NULL, 0);
2192 static SENSOR_DEVICE_ATTR(fan2_alarm, S_IRUGO, show_alarm, NULL, 1);
2193 static SENSOR_DEVICE_ATTR(fan3_alarm, S_IRUGO, show_alarm, NULL, 2);
2194 static SENSOR_DEVICE_ATTR(fan4_alarm, S_IRUGO, show_alarm, NULL, 3);
2195 static SENSOR_DEVICE_ATTR(fan5_alarm, S_IRUGO, show_alarm, NULL, 6);
2196 static SENSOR_DEVICE_ATTR(fan6_alarm, S_IRUGO, show_alarm, NULL, 7);
2197 static SENSOR_DEVICE_ATTR(temp1_alarm, S_IRUGO, show_alarm, NULL, 16);
2198 static SENSOR_DEVICE_ATTR(temp2_alarm, S_IRUGO, show_alarm, NULL, 17);
2199 static SENSOR_DEVICE_ATTR(temp3_alarm, S_IRUGO, show_alarm, NULL, 18);
2200 static SENSOR_DEVICE_ATTR(temp4_alarm, S_IRUGO, show_alarm, NULL, 19);
2201 static SENSOR_DEVICE_ATTR(temp5_alarm, S_IRUGO, show_alarm, NULL, 20);
2202 static SENSOR_DEVICE_ATTR(temp6_alarm, S_IRUGO, show_alarm, NULL, 21);
2203 static SENSOR_DEVICE_ATTR(intrusion0_alarm, S_IRUGO | S_IWUSR,
2204 show_alarm, clear_intrusion, 4);
2206 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2209 struct it87_data *data = it87_update_device(dev);
2210 int bitnr = to_sensor_dev_attr(attr)->index;
2212 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2215 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2216 const char *buf, size_t count)
2218 int bitnr = to_sensor_dev_attr(attr)->index;
2219 struct it87_data *data = dev_get_drvdata(dev);
2222 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2225 mutex_lock(&data->update_lock);
2226 data->beeps = it87_read_value(data, IT87_REG_BEEP_ENABLE);
2228 data->beeps |= BIT(bitnr);
2230 data->beeps &= ~BIT(bitnr);
2231 it87_write_value(data, IT87_REG_BEEP_ENABLE, data->beeps);
2232 mutex_unlock(&data->update_lock);
2236 static SENSOR_DEVICE_ATTR(in0_beep, S_IRUGO | S_IWUSR,
2237 show_beep, set_beep, 1);
2238 static SENSOR_DEVICE_ATTR(in1_beep, S_IRUGO, show_beep, NULL, 1);
2239 static SENSOR_DEVICE_ATTR(in2_beep, S_IRUGO, show_beep, NULL, 1);
2240 static SENSOR_DEVICE_ATTR(in3_beep, S_IRUGO, show_beep, NULL, 1);
2241 static SENSOR_DEVICE_ATTR(in4_beep, S_IRUGO, show_beep, NULL, 1);
2242 static SENSOR_DEVICE_ATTR(in5_beep, S_IRUGO, show_beep, NULL, 1);
2243 static SENSOR_DEVICE_ATTR(in6_beep, S_IRUGO, show_beep, NULL, 1);
2244 static SENSOR_DEVICE_ATTR(in7_beep, S_IRUGO, show_beep, NULL, 1);
2245 /* fanX_beep writability is set later */
2246 static SENSOR_DEVICE_ATTR(fan1_beep, S_IRUGO, show_beep, set_beep, 0);
2247 static SENSOR_DEVICE_ATTR(fan2_beep, S_IRUGO, show_beep, set_beep, 0);
2248 static SENSOR_DEVICE_ATTR(fan3_beep, S_IRUGO, show_beep, set_beep, 0);
2249 static SENSOR_DEVICE_ATTR(fan4_beep, S_IRUGO, show_beep, set_beep, 0);
2250 static SENSOR_DEVICE_ATTR(fan5_beep, S_IRUGO, show_beep, set_beep, 0);
2251 static SENSOR_DEVICE_ATTR(fan6_beep, S_IRUGO, show_beep, set_beep, 0);
2252 static SENSOR_DEVICE_ATTR(temp1_beep, S_IRUGO | S_IWUSR,
2253 show_beep, set_beep, 2);
2254 static SENSOR_DEVICE_ATTR(temp2_beep, S_IRUGO, show_beep, NULL, 2);
2255 static SENSOR_DEVICE_ATTR(temp3_beep, S_IRUGO, show_beep, NULL, 2);
2256 static SENSOR_DEVICE_ATTR(temp4_beep, S_IRUGO, show_beep, NULL, 2);
2257 static SENSOR_DEVICE_ATTR(temp5_beep, S_IRUGO, show_beep, NULL, 2);
2258 static SENSOR_DEVICE_ATTR(temp6_beep, S_IRUGO, show_beep, NULL, 2);
2260 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2263 struct it87_data *data = dev_get_drvdata(dev);
2265 return sprintf(buf, "%u\n", data->vrm);
2268 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2269 const char *buf, size_t count)
2271 struct it87_data *data = dev_get_drvdata(dev);
2274 if (kstrtoul(buf, 10, &val) < 0)
2281 static DEVICE_ATTR(vrm, S_IRUGO | S_IWUSR, show_vrm_reg, store_vrm_reg);
2283 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2286 struct it87_data *data = it87_update_device(dev);
2288 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2290 static DEVICE_ATTR(cpu0_vid, S_IRUGO, show_vid_reg, NULL);
2292 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2295 static const char * const labels[] = {
2301 static const char * const labels_it8721[] = {
2307 struct it87_data *data = dev_get_drvdata(dev);
2308 int nr = to_sensor_dev_attr(attr)->index;
2311 if (has_vin3_5v(data) && nr == 0)
2313 else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2315 label = labels_it8721[nr];
2319 return sprintf(buf, "%s\n", label);
2321 static SENSOR_DEVICE_ATTR(in3_label, S_IRUGO, show_label, NULL, 0);
2322 static SENSOR_DEVICE_ATTR(in7_label, S_IRUGO, show_label, NULL, 1);
2323 static SENSOR_DEVICE_ATTR(in8_label, S_IRUGO, show_label, NULL, 2);
2325 static SENSOR_DEVICE_ATTR(in9_label, S_IRUGO, show_label, NULL, 3);
2327 static umode_t it87_in_is_visible(struct kobject *kobj,
2328 struct attribute *attr, int index)
2330 struct device *dev = container_of(kobj, struct device, kobj);
2331 struct it87_data *data = dev_get_drvdata(dev);
2332 int i = index / 5; /* voltage index */
2333 int a = index % 5; /* attribute index */
2335 if (index >= 40) { /* in8 and higher only have input attributes */
2340 if (!(data->has_in & BIT(i)))
2343 if (a == 4 && !data->has_beep)
2349 static struct attribute *it87_attributes_in[] = {
2350 &sensor_dev_attr_in0_input.dev_attr.attr,
2351 &sensor_dev_attr_in0_min.dev_attr.attr,
2352 &sensor_dev_attr_in0_max.dev_attr.attr,
2353 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2354 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2356 &sensor_dev_attr_in1_input.dev_attr.attr,
2357 &sensor_dev_attr_in1_min.dev_attr.attr,
2358 &sensor_dev_attr_in1_max.dev_attr.attr,
2359 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2360 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2362 &sensor_dev_attr_in2_input.dev_attr.attr,
2363 &sensor_dev_attr_in2_min.dev_attr.attr,
2364 &sensor_dev_attr_in2_max.dev_attr.attr,
2365 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2366 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2368 &sensor_dev_attr_in3_input.dev_attr.attr,
2369 &sensor_dev_attr_in3_min.dev_attr.attr,
2370 &sensor_dev_attr_in3_max.dev_attr.attr,
2371 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2372 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2374 &sensor_dev_attr_in4_input.dev_attr.attr,
2375 &sensor_dev_attr_in4_min.dev_attr.attr,
2376 &sensor_dev_attr_in4_max.dev_attr.attr,
2377 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2378 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2380 &sensor_dev_attr_in5_input.dev_attr.attr,
2381 &sensor_dev_attr_in5_min.dev_attr.attr,
2382 &sensor_dev_attr_in5_max.dev_attr.attr,
2383 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2384 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2386 &sensor_dev_attr_in6_input.dev_attr.attr,
2387 &sensor_dev_attr_in6_min.dev_attr.attr,
2388 &sensor_dev_attr_in6_max.dev_attr.attr,
2389 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2390 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2392 &sensor_dev_attr_in7_input.dev_attr.attr,
2393 &sensor_dev_attr_in7_min.dev_attr.attr,
2394 &sensor_dev_attr_in7_max.dev_attr.attr,
2395 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2396 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2398 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2399 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
2400 &sensor_dev_attr_in10_input.dev_attr.attr, /* 42 */
2401 &sensor_dev_attr_in11_input.dev_attr.attr, /* 43 */
2402 &sensor_dev_attr_in12_input.dev_attr.attr, /* 44 */
2406 static const struct attribute_group it87_group_in = {
2407 .attrs = it87_attributes_in,
2408 .is_visible = it87_in_is_visible,
2411 static umode_t it87_temp_is_visible(struct kobject *kobj,
2412 struct attribute *attr, int index)
2414 struct device *dev = container_of(kobj, struct device, kobj);
2415 struct it87_data *data = dev_get_drvdata(dev);
2416 int i = index / 7; /* temperature index */
2417 int a = index % 7; /* attribute index */
2419 if (!(data->has_temp & BIT(i)))
2422 if (a && i >= data->num_temp_limit)
2426 int type = get_temp_type(data, i);
2430 if (has_bank_sel(data))
2435 if (a == 5 && i >= data->num_temp_offset)
2438 if (a == 6 && !data->has_beep)
2444 static struct attribute *it87_attributes_temp[] = {
2445 &sensor_dev_attr_temp1_input.dev_attr.attr,
2446 &sensor_dev_attr_temp1_max.dev_attr.attr,
2447 &sensor_dev_attr_temp1_min.dev_attr.attr,
2448 &sensor_dev_attr_temp1_type.dev_attr.attr, /* 3 */
2449 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2450 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2451 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2453 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2454 &sensor_dev_attr_temp2_max.dev_attr.attr,
2455 &sensor_dev_attr_temp2_min.dev_attr.attr,
2456 &sensor_dev_attr_temp2_type.dev_attr.attr,
2457 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2458 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2459 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2461 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2462 &sensor_dev_attr_temp3_max.dev_attr.attr,
2463 &sensor_dev_attr_temp3_min.dev_attr.attr,
2464 &sensor_dev_attr_temp3_type.dev_attr.attr,
2465 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2466 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2467 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2469 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2470 &sensor_dev_attr_temp4_max.dev_attr.attr,
2471 &sensor_dev_attr_temp4_min.dev_attr.attr,
2472 &sensor_dev_attr_temp4_type.dev_attr.attr,
2473 &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2474 &sensor_dev_attr_temp4_offset.dev_attr.attr,
2475 &sensor_dev_attr_temp4_beep.dev_attr.attr,
2477 &sensor_dev_attr_temp5_input.dev_attr.attr,
2478 &sensor_dev_attr_temp5_max.dev_attr.attr,
2479 &sensor_dev_attr_temp5_min.dev_attr.attr,
2480 &sensor_dev_attr_temp5_type.dev_attr.attr,
2481 &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2482 &sensor_dev_attr_temp5_offset.dev_attr.attr,
2483 &sensor_dev_attr_temp5_beep.dev_attr.attr,
2485 &sensor_dev_attr_temp6_input.dev_attr.attr,
2486 &sensor_dev_attr_temp6_max.dev_attr.attr,
2487 &sensor_dev_attr_temp6_min.dev_attr.attr,
2488 &sensor_dev_attr_temp6_type.dev_attr.attr,
2489 &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2490 &sensor_dev_attr_temp6_offset.dev_attr.attr,
2491 &sensor_dev_attr_temp6_beep.dev_attr.attr,
2495 static const struct attribute_group it87_group_temp = {
2496 .attrs = it87_attributes_temp,
2497 .is_visible = it87_temp_is_visible,
2500 static umode_t it87_is_visible(struct kobject *kobj,
2501 struct attribute *attr, int index)
2503 struct device *dev = container_of(kobj, struct device, kobj);
2504 struct it87_data *data = dev_get_drvdata(dev);
2506 if ((index == 2 || index == 3) && !data->has_vid)
2509 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2515 static struct attribute *it87_attributes[] = {
2516 &dev_attr_alarms.attr,
2517 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2518 &dev_attr_vrm.attr, /* 2 */
2519 &dev_attr_cpu0_vid.attr, /* 3 */
2520 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2521 &sensor_dev_attr_in7_label.dev_attr.attr,
2522 &sensor_dev_attr_in8_label.dev_attr.attr,
2523 &sensor_dev_attr_in9_label.dev_attr.attr,
2527 static const struct attribute_group it87_group = {
2528 .attrs = it87_attributes,
2529 .is_visible = it87_is_visible,
2532 static umode_t it87_fan_is_visible(struct kobject *kobj,
2533 struct attribute *attr, int index)
2535 struct device *dev = container_of(kobj, struct device, kobj);
2536 struct it87_data *data = dev_get_drvdata(dev);
2537 int i = index / 5; /* fan index */
2538 int a = index % 5; /* attribute index */
2540 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2541 i = (index - 15) / 4 + 3;
2542 a = (index - 15) % 4;
2545 if (!(data->has_fan & BIT(i)))
2548 if (a == 3) { /* beep */
2549 if (!data->has_beep)
2551 /* first fan beep attribute is writable */
2552 if (i == __ffs(data->has_fan))
2553 return attr->mode | S_IWUSR;
2556 if (a == 4 && has_16bit_fans(data)) /* divisor */
2562 static struct attribute *it87_attributes_fan[] = {
2563 &sensor_dev_attr_fan1_input.dev_attr.attr,
2564 &sensor_dev_attr_fan1_min.dev_attr.attr,
2565 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2566 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2567 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2569 &sensor_dev_attr_fan2_input.dev_attr.attr,
2570 &sensor_dev_attr_fan2_min.dev_attr.attr,
2571 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2572 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2573 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2575 &sensor_dev_attr_fan3_input.dev_attr.attr,
2576 &sensor_dev_attr_fan3_min.dev_attr.attr,
2577 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2578 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2579 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2581 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2582 &sensor_dev_attr_fan4_min.dev_attr.attr,
2583 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2584 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2586 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2587 &sensor_dev_attr_fan5_min.dev_attr.attr,
2588 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2589 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2591 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2592 &sensor_dev_attr_fan6_min.dev_attr.attr,
2593 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2594 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2598 static const struct attribute_group it87_group_fan = {
2599 .attrs = it87_attributes_fan,
2600 .is_visible = it87_fan_is_visible,
2603 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2604 struct attribute *attr, int index)
2606 struct device *dev = container_of(kobj, struct device, kobj);
2607 struct it87_data *data = dev_get_drvdata(dev);
2608 int i = index / 4; /* pwm index */
2609 int a = index % 4; /* attribute index */
2611 if (!(data->has_pwm & BIT(i)))
2614 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2615 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2616 return attr->mode | S_IWUSR;
2618 /* pwm2_freq is writable if there are two pwm frequency selects */
2619 if (has_pwm_freq2(data) && i == 1 && a == 2)
2620 return attr->mode | S_IWUSR;
2625 static struct attribute *it87_attributes_pwm[] = {
2626 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2627 &sensor_dev_attr_pwm1.dev_attr.attr,
2628 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2629 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2631 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2632 &sensor_dev_attr_pwm2.dev_attr.attr,
2633 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2634 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2636 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2637 &sensor_dev_attr_pwm3.dev_attr.attr,
2638 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2639 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2641 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2642 &sensor_dev_attr_pwm4.dev_attr.attr,
2643 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2644 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2646 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2647 &sensor_dev_attr_pwm5.dev_attr.attr,
2648 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2649 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2651 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2652 &sensor_dev_attr_pwm6.dev_attr.attr,
2653 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2654 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2659 static const struct attribute_group it87_group_pwm = {
2660 .attrs = it87_attributes_pwm,
2661 .is_visible = it87_pwm_is_visible,
2664 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2665 struct attribute *attr, int index)
2667 struct device *dev = container_of(kobj, struct device, kobj);
2668 struct it87_data *data = dev_get_drvdata(dev);
2669 int i = index / 11; /* pwm index */
2670 int a = index % 11; /* attribute index */
2672 if (index >= 33) { /* pwm 4..6 */
2673 i = (index - 33) / 6 + 3;
2674 a = (index - 33) % 6 + 4;
2677 if (!(data->has_pwm & BIT(i)))
2680 if (has_newer_autopwm(data)) {
2681 if (a < 4) /* no auto point pwm */
2683 if (a == 8) /* no auto_point4 */
2686 if (has_old_autopwm(data)) {
2687 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2694 static struct attribute *it87_attributes_auto_pwm[] = {
2695 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2696 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2697 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2698 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2699 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2700 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2701 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2702 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2703 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2704 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2705 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2707 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2708 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2709 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2710 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2711 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2712 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2713 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2714 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2715 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2716 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2717 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2719 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2720 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2721 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2722 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2723 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2724 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2725 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2726 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2727 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2728 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2729 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2731 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2732 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2733 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2734 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2735 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2736 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2738 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2739 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2740 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2741 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2742 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2743 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2745 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2746 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2747 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2748 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2749 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2750 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2755 static const struct attribute_group it87_group_auto_pwm = {
2756 .attrs = it87_attributes_auto_pwm,
2757 .is_visible = it87_auto_pwm_is_visible,
2760 /* SuperIO detection - will change isa_address if a chip is found */
2761 static int __init it87_find(int sioaddr, unsigned short *address,
2762 struct it87_sio_data *sio_data)
2764 const struct it87_devices *config;
2769 err = superio_enter(sioaddr);
2774 chip_type = superio_inw(sioaddr, DEVID);
2775 if (chip_type == 0xffff)
2779 chip_type = force_id;
2781 switch (chip_type) {
2783 sio_data->type = it87;
2786 sio_data->type = it8712;
2790 sio_data->type = it8716;
2793 sio_data->type = it8718;
2796 sio_data->type = it8720;
2799 sio_data->type = it8721;
2802 sio_data->type = it8728;
2805 sio_data->type = it8732;
2808 sio_data->type = it8792;
2810 * Disabling configuration mode on IT8792E can result in system
2811 * hang-ups and access failures to the Super-IO chip at the
2812 * second SIO address. Never exit configuration mode on this
2813 * chip to avoid the problem.
2818 sio_data->type = it8771;
2821 sio_data->type = it8772;
2824 sio_data->type = it8781;
2827 sio_data->type = it8782;
2830 sio_data->type = it8783;
2833 sio_data->type = it8786;
2836 sio_data->type = it8790;
2837 doexit = false; /* See IT8792E comment above */
2841 sio_data->type = it8603;
2844 sio_data->type = it8607;
2847 sio_data->type = it8613;
2850 sio_data->type = it8620;
2853 sio_data->type = it8622;
2856 sio_data->type = it8625;
2859 sio_data->type = it8628;
2862 sio_data->type = it8655;
2865 sio_data->type = it8665;
2868 sio_data->type = it8686;
2870 case 0xffff: /* No device at all */
2873 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
2877 superio_select(sioaddr, PME);
2878 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
2879 pr_info("Device not activated, skipping\n");
2883 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
2884 if (*address == 0) {
2885 pr_info("Base address not set, skipping\n");
2890 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
2891 pr_info("Found IT%04x%s chip at 0x%x, revision %d\n", chip_type,
2892 it87_devices[sio_data->type].suffix,
2893 *address, sio_data->revision);
2895 config = &it87_devices[sio_data->type];
2897 /* in7 (VSB or VCCH5V) is always internal on some chips */
2898 if (has_in7_internal(config))
2899 sio_data->internal |= BIT(1);
2901 /* in8 (Vbat) is always internal */
2902 sio_data->internal |= BIT(2);
2904 /* in9 (AVCC3), always internal if supported */
2905 if (has_avcc3(config))
2906 sio_data->internal |= BIT(3); /* in9 is AVCC */
2908 sio_data->skip_in |= BIT(9);
2910 if (!has_four_pwm(config))
2911 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
2912 else if (!has_five_pwm(config))
2913 sio_data->skip_pwm |= BIT(4) | BIT(5);
2914 else if (!has_six_pwm(config))
2915 sio_data->skip_pwm |= BIT(5);
2917 if (!has_vid(config))
2918 sio_data->skip_vid = 1;
2920 /* Read GPIO config and VID value from LDN 7 (GPIO) */
2921 if (sio_data->type == it87) {
2922 /* The IT8705F has a different LD number for GPIO */
2923 superio_select(sioaddr, 5);
2924 sio_data->beep_pin = superio_inb(sioaddr,
2925 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2926 } else if (sio_data->type == it8783) {
2927 int reg25, reg27, reg2a, reg2c, regef;
2929 superio_select(sioaddr, GPIO);
2931 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
2932 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
2933 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
2934 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
2935 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
2937 /* Check if fan3 is there or not */
2938 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
2939 sio_data->skip_fan |= BIT(2);
2940 if ((reg25 & BIT(4)) ||
2941 (!(reg2a & BIT(1)) && (regef & BIT(0))))
2942 sio_data->skip_pwm |= BIT(2);
2944 /* Check if fan2 is there or not */
2946 sio_data->skip_fan |= BIT(1);
2948 sio_data->skip_pwm |= BIT(1);
2951 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
2952 sio_data->skip_in |= BIT(5); /* No VIN5 */
2956 sio_data->skip_in |= BIT(6); /* No VIN6 */
2960 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
2962 if (reg27 & BIT(2)) {
2964 * The data sheet is a bit unclear regarding the
2965 * internal voltage divider for VCCH5V. It says
2966 * "This bit enables and switches VIN7 (pin 91) to the
2967 * internal voltage divider for VCCH5V".
2968 * This is different to other chips, where the internal
2969 * voltage divider would connect VIN7 to an internal
2970 * voltage source. Maybe that is the case here as well.
2972 * Since we don't know for sure, re-route it if that is
2973 * not the case, and ask the user to report if the
2974 * resulting voltage is sane.
2976 if (!(reg2c & BIT(1))) {
2978 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
2980 pr_notice("Routing internal VCCH5V to in7.\n");
2982 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
2983 pr_notice("Please report if it displays a reasonable voltage.\n");
2987 sio_data->internal |= BIT(0);
2989 sio_data->internal |= BIT(1);
2991 sio_data->beep_pin = superio_inb(sioaddr,
2992 IT87_SIO_BEEP_PIN_REG) & 0x3f;
2993 } else if (sio_data->type == it8603 || sio_data->type == it8607) {
2996 superio_select(sioaddr, GPIO);
2998 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3000 /* Check if fan3 is there or not */
3002 sio_data->skip_pwm |= BIT(2);
3004 sio_data->skip_fan |= BIT(2);
3006 /* Check if fan2 is there or not */
3007 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3009 sio_data->skip_pwm |= BIT(1);
3011 sio_data->skip_fan |= BIT(1);
3013 switch (sio_data->type) {
3015 sio_data->skip_in |= BIT(5); /* No VIN5 */
3016 sio_data->skip_in |= BIT(6); /* No VIN6 */
3019 sio_data->skip_pwm |= BIT(0);/* No fan1 */
3020 sio_data->skip_fan |= BIT(0);
3025 sio_data->beep_pin = superio_inb(sioaddr,
3026 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3027 } else if (sio_data->type == it8613) {
3028 int reg27, reg29, reg2a;
3030 superio_select(sioaddr, GPIO);
3032 /* Check for pwm3, fan3, pwm5, fan5 */
3033 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3035 sio_data->skip_fan |= BIT(4);
3037 sio_data->skip_pwm |= BIT(4);
3039 sio_data->skip_pwm |= BIT(2);
3041 sio_data->skip_fan |= BIT(2);
3043 /* Check for pwm2, fan2 */
3044 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3046 sio_data->skip_pwm |= BIT(1);
3048 sio_data->skip_fan |= BIT(1);
3050 /* Check for pwm4, fan4 */
3051 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3052 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3053 sio_data->skip_fan |= BIT(3);
3054 sio_data->skip_pwm |= BIT(3);
3057 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3058 sio_data->skip_fan |= BIT(0); /* No fan1 */
3059 sio_data->skip_in |= BIT(3); /* No VIN3 */
3060 sio_data->skip_in |= BIT(6); /* No VIN6 */
3062 sio_data->beep_pin = superio_inb(sioaddr,
3063 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3064 } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3065 sio_data->type == it8686) {
3068 superio_select(sioaddr, GPIO);
3070 /* Check for pwm5 */
3071 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3073 sio_data->skip_pwm |= BIT(4);
3075 /* Check for fan4, fan5 */
3076 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3077 if (!(reg & BIT(5)))
3078 sio_data->skip_fan |= BIT(3);
3079 if (!(reg & BIT(4)))
3080 sio_data->skip_fan |= BIT(4);
3082 /* Check for pwm3, fan3 */
3083 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3085 sio_data->skip_pwm |= BIT(2);
3087 sio_data->skip_fan |= BIT(2);
3089 /* Check for pwm4 */
3090 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3092 sio_data->skip_pwm |= BIT(3);
3094 /* Check for pwm2, fan2 */
3095 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3097 sio_data->skip_pwm |= BIT(1);
3099 sio_data->skip_fan |= BIT(1);
3100 /* Check for pwm6, fan6 */
3101 if (!(reg & BIT(7))) {
3102 sio_data->skip_pwm |= BIT(5);
3103 sio_data->skip_fan |= BIT(5);
3106 /* Check if AVCC is on VIN3 */
3107 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3109 /* For it8686, the bit just enables AVCC3 */
3110 if (sio_data->type != it8686)
3111 sio_data->internal |= BIT(0);
3113 sio_data->internal &= ~BIT(3);
3114 sio_data->skip_in |= BIT(9);
3117 sio_data->beep_pin = superio_inb(sioaddr,
3118 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3119 } else if (sio_data->type == it8622) {
3122 superio_select(sioaddr, GPIO);
3124 /* Check for pwm4, fan4 */
3125 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3127 sio_data->skip_fan |= BIT(3);
3129 sio_data->skip_pwm |= BIT(3);
3131 /* Check for pwm3, fan3, pwm5, fan5 */
3132 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3134 sio_data->skip_pwm |= BIT(2);
3136 sio_data->skip_fan |= BIT(2);
3138 sio_data->skip_pwm |= BIT(4);
3140 sio_data->skip_fan |= BIT(4);
3142 /* Check for pwm2, fan2 */
3143 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3145 sio_data->skip_pwm |= BIT(1);
3147 sio_data->skip_fan |= BIT(1);
3149 /* Check for AVCC */
3150 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3151 if (!(reg & BIT(0)))
3152 sio_data->skip_in |= BIT(9);
3154 sio_data->beep_pin = superio_inb(sioaddr,
3155 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3156 } else if (sio_data->type == it8732) {
3159 superio_select(sioaddr, GPIO);
3161 /* Check for pwm2, fan2 */
3162 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3164 sio_data->skip_pwm |= BIT(1);
3166 sio_data->skip_fan |= BIT(1);
3168 /* Check for pwm3, fan3, fan4 */
3169 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3171 sio_data->skip_pwm |= BIT(2);
3173 sio_data->skip_fan |= BIT(2);
3175 sio_data->skip_fan |= BIT(3);
3177 /* Check if AVCC is on VIN3 */
3178 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3180 sio_data->internal |= BIT(0);
3182 sio_data->beep_pin = superio_inb(sioaddr,
3183 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3184 } else if (sio_data->type == it8655) {
3187 superio_select(sioaddr, GPIO);
3189 /* Check for pwm2 */
3190 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3192 sio_data->skip_pwm |= BIT(1);
3194 /* Check for fan2 */
3195 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3197 sio_data->skip_fan |= BIT(1);
3199 /* Check for pwm3, fan3 */
3200 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3202 sio_data->skip_pwm |= BIT(2);
3204 sio_data->skip_fan |= BIT(2);
3206 sio_data->beep_pin = superio_inb(sioaddr,
3207 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3208 } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3209 int reg27, reg29, reg2d, regd3;
3211 superio_select(sioaddr, GPIO);
3213 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3214 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3215 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3216 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3218 /* Check for pwm2, fan2 */
3220 sio_data->skip_pwm |= BIT(1);
3222 sio_data->skip_fan |= BIT(1);
3224 /* Check for pwm3, fan3 */
3226 sio_data->skip_pwm |= BIT(2);
3228 sio_data->skip_fan |= BIT(2);
3230 /* Check for pwm4, fan4, pwm5, fan5 */
3231 if (sio_data->type == it8625) {
3232 int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3235 sio_data->skip_fan |= BIT(3);
3237 sio_data->skip_pwm |= BIT(3);
3239 sio_data->skip_pwm |= BIT(4);
3241 sio_data->skip_fan |= BIT(4);
3243 int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3246 sio_data->skip_pwm |= BIT(3);
3248 sio_data->skip_fan |= BIT(3);
3250 sio_data->skip_pwm |= BIT(4);
3251 if (!(reg26 & BIT(4)))
3252 sio_data->skip_fan |= BIT(4);
3255 /* Check for pwm6, fan6 */
3257 sio_data->skip_pwm |= BIT(5);
3259 sio_data->skip_fan |= BIT(5);
3261 sio_data->beep_pin = superio_inb(sioaddr,
3262 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3267 superio_select(sioaddr, GPIO);
3269 /* Check for fan4, fan5 */
3270 if (has_five_fans(config)) {
3271 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3272 switch (sio_data->type) {
3275 sio_data->skip_fan |= BIT(3);
3277 sio_data->skip_fan |= BIT(4);
3282 if (!(reg & BIT(5)))
3283 sio_data->skip_fan |= BIT(3);
3284 if (!(reg & BIT(4)))
3285 sio_data->skip_fan |= BIT(4);
3292 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3293 if (!sio_data->skip_vid) {
3294 /* We need at least 4 VID pins */
3296 pr_info("VID is disabled (pins used for GPIO)\n");
3297 sio_data->skip_vid = 1;
3301 /* Check if fan3 is there or not */
3303 sio_data->skip_pwm |= BIT(2);
3305 sio_data->skip_fan |= BIT(2);
3307 /* Check if fan2 is there or not */
3308 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3310 sio_data->skip_pwm |= BIT(1);
3312 sio_data->skip_fan |= BIT(1);
3314 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3315 !(sio_data->skip_vid))
3316 sio_data->vid_value = superio_inb(sioaddr,
3319 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3321 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3324 * The IT8720F has no VIN7 pin, so VCCH should always be
3325 * routed internally to VIN7 with an internal divider.
3326 * Curiously, there still is a configuration bit to control
3327 * this, which means it can be set incorrectly. And even
3328 * more curiously, many boards out there are improperly
3329 * configured, even though the IT8720F datasheet claims
3330 * that the internal routing of VCCH to VIN7 is the default
3331 * setting. So we force the internal routing in this case.
3333 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3334 * If UART6 is enabled, re-route VIN7 to the internal divider
3335 * if that is not already the case.
3337 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3339 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3340 pr_notice("Routing internal VCCH to in7\n");
3343 sio_data->internal |= BIT(0);
3345 sio_data->internal |= BIT(1);
3348 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3349 * While VIN7 can be routed to the internal voltage divider,
3350 * VIN5 and VIN6 are not available if UART6 is enabled.
3352 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3353 * is the temperature source. Since we can not read the
3354 * temperature source here, skip_temp is preliminary.
3357 sio_data->skip_in |= BIT(5) | BIT(6);
3358 sio_data->skip_temp |= BIT(2);
3361 sio_data->beep_pin = superio_inb(sioaddr,
3362 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3364 if (sio_data->beep_pin)
3365 pr_info("Beeping is supported\n");
3368 superio_exit(sioaddr, doexit);
3372 static void it87_init_regs(struct platform_device *pdev)
3374 struct it87_data *data = platform_get_drvdata(pdev);
3376 /* Initialize chip specific register pointers */
3377 switch (data->type) {
3380 data->REG_FAN = IT87_REG_FAN;
3381 data->REG_FANX = IT87_REG_FANX;
3382 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3383 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3384 data->REG_PWM = IT87_REG_PWM;
3385 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3386 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3387 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3392 data->REG_FAN = IT87_REG_FAN_8665;
3393 data->REG_FANX = IT87_REG_FANX_8665;
3394 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3395 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3396 data->REG_PWM = IT87_REG_PWM_8665;
3397 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3398 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3399 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3402 data->REG_FAN = IT87_REG_FAN;
3403 data->REG_FANX = IT87_REG_FANX;
3404 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3405 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3406 data->REG_PWM = IT87_REG_PWM_8665;
3407 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3408 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3409 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3412 data->REG_FAN = IT87_REG_FAN;
3413 data->REG_FANX = IT87_REG_FANX;
3414 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3415 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3416 data->REG_PWM = IT87_REG_PWM_8665;
3417 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3418 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3419 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3422 data->REG_FAN = IT87_REG_FAN;
3423 data->REG_FANX = IT87_REG_FANX;
3424 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3425 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3426 data->REG_PWM = IT87_REG_PWM;
3427 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3428 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3429 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3434 /* Called when we have found a new IT87. */
3435 static void it87_init_device(struct platform_device *pdev)
3437 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3438 struct it87_data *data = platform_get_drvdata(pdev);
3443 * For each PWM channel:
3444 * - If it is in automatic mode, setting to manual mode should set
3445 * the fan to full speed by default.
3446 * - If it is in manual mode, we need a mapping to temperature
3447 * channels to use when later setting to automatic mode later.
3448 * Use a 1:1 mapping by default (we are clueless.)
3449 * In both cases, the value can (and should) be changed by the user
3450 * prior to switching to a different mode.
3451 * Note that this is no longer needed for the IT8721F and later, as
3452 * these have separate registers for the temperature mapping and the
3453 * manual duty cycle.
3455 for (i = 0; i < NUM_AUTO_PWM; i++) {
3456 data->pwm_temp_map[i] = i;
3457 data->pwm_duty[i] = 0x7f; /* Full speed */
3458 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
3462 * Some chips seem to have default value 0xff for all limit
3463 * registers. For low voltage limits it makes no sense and triggers
3464 * alarms, so change to 0 instead. For high temperature limits, it
3465 * means -1 degree C, which surprisingly doesn't trigger an alarm,
3466 * but is still confusing, so change to 127 degrees C.
3468 for (i = 0; i < NUM_VIN_LIMIT; i++) {
3469 tmp = it87_read_value(data, IT87_REG_VIN_MIN(i));
3471 it87_write_value(data, IT87_REG_VIN_MIN(i), 0);
3473 for (i = 0; i < data->num_temp_limit; i++) {
3474 tmp = it87_read_value(data, data->REG_TEMP_HIGH[i]);
3476 it87_write_value(data, data->REG_TEMP_HIGH[i], 127);
3480 * Temperature channels are not forcibly enabled, as they can be
3481 * set to two different sensor types and we can't guess which one
3482 * is correct for a given system. These channels can be enabled at
3483 * run-time through the temp{1-3}_type sysfs accessors if needed.
3486 /* Check if voltage monitors are reset manually or by some reason */
3487 tmp = it87_read_value(data, IT87_REG_VIN_ENABLE);
3488 if ((tmp & 0xff) == 0) {
3489 /* Enable all voltage monitors */
3490 it87_write_value(data, IT87_REG_VIN_ENABLE, 0xff);
3493 /* Check if tachometers are reset manually or by some reason */
3494 mask = 0x70 & ~(sio_data->skip_fan << 4);
3495 data->fan_main_ctrl = it87_read_value(data, IT87_REG_FAN_MAIN_CTRL);
3496 if ((data->fan_main_ctrl & mask) == 0) {
3497 /* Enable all fan tachometers */
3498 data->fan_main_ctrl |= mask;
3499 it87_write_value(data, IT87_REG_FAN_MAIN_CTRL,
3500 data->fan_main_ctrl);
3502 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3504 tmp = it87_read_value(data, IT87_REG_FAN_16BIT);
3506 /* Set tachometers to 16-bit mode if needed */
3507 if (has_fan16_config(data)) {
3508 if (~tmp & 0x07 & data->has_fan) {
3510 "Setting fan1-3 to 16-bit mode\n");
3511 it87_write_value(data, IT87_REG_FAN_16BIT,
3516 /* Check for additional fans */
3517 if (has_four_fans(data) && (tmp & BIT(4)))
3518 data->has_fan |= BIT(3); /* fan4 enabled */
3519 if (has_five_fans(data) && (tmp & BIT(5)))
3520 data->has_fan |= BIT(4); /* fan5 enabled */
3521 if (has_six_fans(data)) {
3522 switch (data->type) {
3527 data->has_fan |= BIT(5); /* fan6 enabled */
3531 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3533 data->has_fan |= BIT(5); /* fan6 enabled */
3540 /* Fan input pins may be used for alternative functions */
3541 data->has_fan &= ~sio_data->skip_fan;
3543 /* Check if pwm6 is enabled */
3544 if (has_six_pwm(data)) {
3545 switch (data->type) {
3548 tmp = it87_read_value(data, IT87_REG_FAN_DIV);
3549 if (!(tmp & BIT(3)))
3550 sio_data->skip_pwm |= BIT(5);
3557 /* Start monitoring */
3558 it87_write_value(data, IT87_REG_CONFIG,
3559 (it87_read_value(data, IT87_REG_CONFIG) & 0x3e)
3560 | (update_vbat ? 0x41 : 0x01));
3563 /* Return 1 if and only if the PWM interface is safe to use */
3564 static int it87_check_pwm(struct device *dev)
3566 struct it87_data *data = dev_get_drvdata(dev);
3568 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3569 * and polarity set to active low is sign that this is the case so we
3570 * disable pwm control to protect the user.
3572 int tmp = it87_read_value(data, IT87_REG_FAN_CTL);
3574 if ((tmp & 0x87) == 0) {
3575 if (fix_pwm_polarity) {
3577 * The user asks us to attempt a chip reconfiguration.
3578 * This means switching to active high polarity and
3579 * inverting all fan speed values.
3584 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3585 pwm[i] = it87_read_value(data,
3589 * If any fan is in automatic pwm mode, the polarity
3590 * might be correct, as suspicious as it seems, so we
3591 * better don't change anything (but still disable the
3594 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3596 "Reconfiguring PWM to active high polarity\n");
3597 it87_write_value(data, IT87_REG_FAN_CTL,
3599 for (i = 0; i < 3; i++)
3600 it87_write_value(data,
3607 "PWM configuration is too broken to be fixed\n");
3611 "Detected broken BIOS defaults, disabling PWM interface\n");
3613 } else if (fix_pwm_polarity) {
3615 "PWM configuration looks sane, won't touch\n");
3621 static int it87_probe(struct platform_device *pdev)
3623 struct it87_data *data;
3624 struct resource *res;
3625 struct device *dev = &pdev->dev;
3626 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3627 int enable_pwm_interface;
3628 struct device *hwmon_dev;
3630 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3631 if (!devm_request_region(&pdev->dev, res->start, IT87_EC_EXTENT,
3633 dev_err(dev, "Failed to request region 0x%lx-0x%lx\n",
3634 (unsigned long)res->start,
3635 (unsigned long)(res->start + IT87_EC_EXTENT - 1));
3639 data = devm_kzalloc(&pdev->dev, sizeof(struct it87_data), GFP_KERNEL);
3643 data->addr = res->start;
3644 data->type = sio_data->type;
3645 data->features = it87_devices[sio_data->type].features;
3646 data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3647 data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3648 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3649 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3653 * IT8705F Datasheet 0.4.1, 3h == Version G.
3654 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3655 * These are the first revisions with 16-bit tachometer support.
3657 switch (data->type) {
3659 if (sio_data->revision >= 0x03) {
3660 data->features &= ~FEAT_OLD_AUTOPWM;
3661 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3665 if (sio_data->revision >= 0x08) {
3666 data->features &= ~FEAT_OLD_AUTOPWM;
3667 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3675 /* Now, we do the remaining detection. */
3676 if ((it87_read_value(data, IT87_REG_CONFIG) & 0x80) ||
3677 it87_read_value(data, IT87_REG_CHIPID) != 0x90)
3680 platform_set_drvdata(pdev, data);
3682 mutex_init(&data->update_lock);
3684 /* Initialize register pointers */
3685 it87_init_regs(pdev);
3687 /* Check PWM configuration */
3688 enable_pwm_interface = it87_check_pwm(dev);
3690 /* Starting with IT8721F, we handle scaling of internal voltages */
3691 if (has_scaling(data)) {
3692 if (sio_data->internal & BIT(0))
3693 data->in_scaled |= BIT(3); /* in3 is AVCC */
3694 if (sio_data->internal & BIT(1))
3695 data->in_scaled |= BIT(7); /* in7 is VSB */
3696 if (sio_data->internal & BIT(2))
3697 data->in_scaled |= BIT(8); /* in8 is Vbat */
3698 if (sio_data->internal & BIT(3))
3699 data->in_scaled |= BIT(9); /* in9 is AVCC */
3700 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3701 sio_data->type == it8783) {
3702 if (sio_data->internal & BIT(0))
3703 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3704 if (sio_data->internal & BIT(1))
3705 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3708 data->has_temp = 0x07;
3709 if (sio_data->skip_temp & BIT(2)) {
3710 if (sio_data->type == it8782 &&
3711 !(it87_read_value(data, IT87_REG_TEMP_EXTRA) & 0x80))
3712 data->has_temp &= ~BIT(2);
3715 data->in_internal = sio_data->internal;
3716 data->has_in = 0x3ff & ~sio_data->skip_in;
3718 if (has_six_temp(data)) {
3719 u8 reg = it87_read_value(data, IT87_REG_TEMP456_ENABLE);
3721 /* Check for additional temperature sensors */
3722 if ((reg & 0x03) >= 0x02)
3723 data->has_temp |= BIT(3);
3724 if (((reg >> 2) & 0x03) >= 0x02)
3725 data->has_temp |= BIT(4);
3726 if (((reg >> 4) & 0x03) >= 0x02)
3727 data->has_temp |= BIT(5);
3729 /* Check for additional voltage sensors */
3730 if ((reg & 0x03) == 0x01)
3731 data->has_in |= BIT(10);
3732 if (((reg >> 2) & 0x03) == 0x01)
3733 data->has_in |= BIT(11);
3734 if (((reg >> 4) & 0x03) == 0x01)
3735 data->has_in |= BIT(12);
3738 data->has_beep = !!sio_data->beep_pin;
3740 /* Initialize the IT87 chip */
3741 it87_init_device(pdev);
3743 if (!sio_data->skip_vid) {
3744 data->has_vid = true;
3745 data->vrm = vid_which_vrm();
3746 /* VID reading from Super-I/O config space if available */
3747 data->vid = sio_data->vid_value;
3750 /* Prepare for sysfs hooks */
3751 data->groups[0] = &it87_group;
3752 data->groups[1] = &it87_group_in;
3753 data->groups[2] = &it87_group_temp;
3754 data->groups[3] = &it87_group_fan;
3756 if (enable_pwm_interface) {
3757 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
3758 data->has_pwm &= ~sio_data->skip_pwm;
3760 data->groups[4] = &it87_group_pwm;
3761 if (has_old_autopwm(data) || has_newer_autopwm(data))
3762 data->groups[5] = &it87_group_auto_pwm;
3765 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
3766 it87_devices[sio_data->type].name,
3767 data, data->groups);
3768 return PTR_ERR_OR_ZERO(hwmon_dev);
3771 static struct platform_driver it87_driver = {
3775 .probe = it87_probe,
3778 static int __init it87_device_add(int index, unsigned short address,
3779 const struct it87_sio_data *sio_data)
3781 struct platform_device *pdev;
3782 struct resource res = {
3783 .start = address + IT87_EC_OFFSET,
3784 .end = address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1,
3786 .flags = IORESOURCE_IO,
3790 err = acpi_check_resource_conflict(&res);
3794 pdev = platform_device_alloc(DRVNAME, address);
3798 err = platform_device_add_resources(pdev, &res, 1);
3800 pr_err("Device resource addition failed (%d)\n", err);
3801 goto exit_device_put;
3804 err = platform_device_add_data(pdev, sio_data,
3805 sizeof(struct it87_sio_data));
3807 pr_err("Platform data allocation failed\n");
3808 goto exit_device_put;
3811 err = platform_device_add(pdev);
3813 pr_err("Device addition failed (%d)\n", err);
3814 goto exit_device_put;
3817 it87_pdev[index] = pdev;
3821 platform_device_put(pdev);
3825 struct it87_dmi_data {
3826 bool sio2_force_config; /* force sio2 into configuration mode */
3827 u8 skip_pwm; /* pwm channels to skip for this board */
3831 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
3832 * (IT8792E) needs to be in configuration mode before accessing the first
3833 * due to a bug in IT8792E which otherwise results in LPC bus access errors.
3834 * This needs to be done before accessing the first Super-IO chip since
3835 * the second chip may have been accessed prior to loading this driver.
3837 * The problem is also reported to affect IT8795E, which is used on X299 boards
3838 * and has the same chip ID as IT9792E (0x8733). It also appears to affect
3839 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
3841 * DMI entries for those systems will be added as they become available and
3842 * as the problem is confirmed to affect those boards.
3844 static struct it87_dmi_data gigabyte_sio2_force = {
3845 .sio2_force_config = true,
3849 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
3850 * connected to a fan, but to something else. One user
3851 * has reported instant system power-off when changing
3852 * the PWM2 duty cycle, so we disable it.
3853 * I use the board name string as the trigger in case
3854 * the same board is ever used in other systems.
3856 static struct it87_dmi_data nvidia_fn68pt = {
3860 static const struct dmi_system_id it87_dmi_table[] __initconst = {
3863 DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3864 DMI_MATCH(DMI_BOARD_NAME, "AB350"),
3866 .driver_data = &gigabyte_sio2_force,
3870 DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3871 DMI_MATCH(DMI_BOARD_NAME, "AX370"),
3873 .driver_data = &gigabyte_sio2_force,
3877 DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3878 DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
3880 .driver_data = &gigabyte_sio2_force,
3884 DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
3885 DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
3887 .driver_data = &nvidia_fn68pt,
3892 static int __init sm_it87_init(void)
3894 const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
3895 struct it87_dmi_data *dmi_data = NULL;
3896 int sioaddr[2] = { REG_2E, REG_4E };
3897 struct it87_sio_data sio_data;
3898 unsigned short isa_address;
3903 dmi_data = dmi->driver_data;
3905 err = platform_driver_register(&it87_driver);
3909 if (dmi_data && dmi_data->sio2_force_config)
3910 __superio_enter(REG_4E);
3912 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
3913 memset(&sio_data, 0, sizeof(struct it87_sio_data));
3915 err = it87_find(sioaddr[i], &isa_address, &sio_data);
3916 if (err || isa_address == 0)
3920 sio_data.skip_pwm |= dmi_data->skip_pwm;
3921 err = it87_device_add(i, isa_address, &sio_data);
3923 goto exit_dev_unregister;
3929 goto exit_unregister;
3933 exit_dev_unregister:
3934 /* NULL check handled by platform_device_unregister */
3935 platform_device_unregister(it87_pdev[0]);
3937 platform_driver_unregister(&it87_driver);
3941 static void __exit sm_it87_exit(void)
3943 /* NULL check handled by platform_device_unregister */
3944 platform_device_unregister(it87_pdev[1]);
3945 platform_device_unregister(it87_pdev[0]);
3946 platform_driver_unregister(&it87_driver);
3949 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
3950 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
3951 module_param(update_vbat, bool, 0);
3952 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
3953 module_param(fix_pwm_polarity, bool, 0);
3954 MODULE_PARM_DESC(fix_pwm_polarity,
3955 "Force PWM polarity to active high (DANGEROUS)");
3956 MODULE_LICENSE("GPL");
3958 module_init(sm_it87_init);
3959 module_exit(sm_it87_exit);