2 * it87.c - Part of lm_sensors, Linux kernel modules for hardware
5 * The IT8705F is an LPC-based Super I/O part that contains UARTs, a
6 * parallel port, an IR port, a MIDI port, a floppy controller, etc., in
7 * addition to an Environment Controller (Enhanced Hardware Monitor and
10 * This driver supports only the Environment Controller in the IT8705F and
11 * similar parts. The other devices are supported by different drivers.
13 * Supports: IT8603E Super I/O chip w/LPC interface
14 * IT8606E Super I/O chip w/LPC interface
15 * IT8607E Super I/O chip w/LPC interface
16 * IT8613E Super I/O chip w/LPC interface
17 * IT8620E Super I/O chip w/LPC interface
18 * IT8622E Super I/O chip w/LPC interface
19 * IT8623E Super I/O chip w/LPC interface
20 * IT8625E Super I/O chip w/LPC interface
21 * IT8628E Super I/O chip w/LPC interface
22 * IT8655E Super I/O chip w/LPC interface
23 * IT8665E Super I/O chip w/LPC interface
24 * IT8686E Super I/O chip w/LPC interface
25 * IT8705F Super I/O chip w/LPC interface
26 * IT8712F Super I/O chip w/LPC interface
27 * IT8716F Super I/O chip w/LPC interface
28 * IT8718F Super I/O chip w/LPC interface
29 * IT8720F Super I/O chip w/LPC interface
30 * IT8721F Super I/O chip w/LPC interface
31 * IT8726F Super I/O chip w/LPC interface
32 * IT8728F Super I/O chip w/LPC interface
33 * IT8732F Super I/O chip w/LPC interface
34 * IT8758E Super I/O chip w/LPC interface
35 * IT8771E Super I/O chip w/LPC interface
36 * IT8772E Super I/O chip w/LPC interface
37 * IT8781F Super I/O chip w/LPC interface
38 * IT8782F Super I/O chip w/LPC interface
39 * IT8783E/F Super I/O chip w/LPC interface
40 * IT8786E Super I/O chip w/LPC interface
41 * IT8790E Super I/O chip w/LPC interface
42 * IT8792E Super I/O chip w/LPC interface
43 * Sis950 A clone of the IT8705F
45 * Copyright (C) 2001 Chris Gauthron
46 * Copyright (C) 2005-2010 Jean Delvare <jdelvare@suse.de>
48 * This program is free software; you can redistribute it and/or modify
49 * it under the terms of the GNU General Public License as published by
50 * the Free Software Foundation; either version 2 of the License, or
51 * (at your option) any later version.
53 * This program is distributed in the hope that it will be useful,
54 * but WITHOUT ANY WARRANTY; without even the implied warranty of
55 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56 * GNU General Public License for more details.
59 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
61 #include <linux/bitops.h>
62 #include <linux/module.h>
63 #include <linux/init.h>
64 #include <linux/slab.h>
65 #include <linux/jiffies.h>
66 #include <linux/platform_device.h>
67 #include <linux/hwmon.h>
68 #include <linux/hwmon-sysfs.h>
69 #include <linux/hwmon-vid.h>
70 #include <linux/err.h>
71 #include <linux/mutex.h>
72 #include <linux/sysfs.h>
73 #include <linux/string.h>
74 #include <linux/dmi.h>
75 #include <linux/acpi.h>
79 #ifndef IT87_DRIVER_VERSION
80 #define IT87_DRIVER_VERSION "<not provided>"
83 #define DRVNAME "it87"
85 enum chips { it87, it8712, it8716, it8718, it8720, it8721, it8728, it8732,
86 it8771, it8772, it8781, it8782, it8783, it8786, it8790,
87 it8792, it8603, it8606, it8607, it8613, it8620, it8622, it8625,
88 it8628, it8655, it8665, it8686 };
90 static unsigned short force_id;
91 module_param(force_id, ushort, 0000);
92 MODULE_PARM_DESC(force_id, "Override the detected device ID");
94 static bool ignore_resource_conflict;
95 module_param(ignore_resource_conflict, bool, 0000);
96 MODULE_PARM_DESC(ignore_resource_conflict, "Ignore ACPI resource conflict");
99 module_param(mmio, bool, 0000);
100 MODULE_PARM_DESC(mmio, "Use MMIO if available");
102 static struct platform_device *it87_pdev[2];
104 #define REG_2E 0x2e /* The register to read/write */
105 #define REG_4E 0x4e /* Secondary register to read/write */
107 #define DEV 0x07 /* Register: Logical device select */
108 #define PME 0x04 /* The device with the fan registers in it */
110 /* The device with the IT8718F/IT8720F VID value in it */
113 #define DEVID 0x20 /* Register: Device ID */
114 #define DEVREV 0x22 /* Register: Device Revision */
116 static inline void __superio_enter(int ioreg)
121 outb(ioreg == REG_4E ? 0xaa : 0x55, ioreg);
124 static inline int superio_inb(int ioreg, int reg)
129 val = inb(ioreg + 1);
134 static inline void superio_outb(int ioreg, int reg, int val)
137 outb(val, ioreg + 1);
140 static int superio_inw(int ioreg, int reg)
142 return (superio_inb(ioreg, reg) << 8) | superio_inb(ioreg, reg + 1);
145 static inline void superio_select(int ioreg, int ldn)
148 outb(ldn, ioreg + 1);
151 static inline int superio_enter(int ioreg)
154 * Try to reserve ioreg and ioreg + 1 for exclusive access.
156 if (!request_muxed_region(ioreg, 2, DRVNAME))
159 __superio_enter(ioreg);
163 static inline void superio_exit(int ioreg, bool doexit)
167 outb(0x02, ioreg + 1);
169 release_region(ioreg, 2);
172 /* Logical device 4 registers */
173 #define IT8712F_DEVID 0x8712
174 #define IT8705F_DEVID 0x8705
175 #define IT8716F_DEVID 0x8716
176 #define IT8718F_DEVID 0x8718
177 #define IT8720F_DEVID 0x8720
178 #define IT8721F_DEVID 0x8721
179 #define IT8726F_DEVID 0x8726
180 #define IT8728F_DEVID 0x8728
181 #define IT8732F_DEVID 0x8732
182 #define IT8792E_DEVID 0x8733
183 #define IT8771E_DEVID 0x8771
184 #define IT8772E_DEVID 0x8772
185 #define IT8781F_DEVID 0x8781
186 #define IT8782F_DEVID 0x8782
187 #define IT8783E_DEVID 0x8783
188 #define IT8786E_DEVID 0x8786
189 #define IT8790E_DEVID 0x8790
190 #define IT8603E_DEVID 0x8603
191 #define IT8606E_DEVID 0x8606
192 #define IT8607E_DEVID 0x8607
193 #define IT8613E_DEVID 0x8613
194 #define IT8620E_DEVID 0x8620
195 #define IT8622E_DEVID 0x8622
196 #define IT8623E_DEVID 0x8623
197 #define IT8625E_DEVID 0x8625
198 #define IT8628E_DEVID 0x8628
199 #define IT8655E_DEVID 0x8655
200 #define IT8665E_DEVID 0x8665
201 #define IT8686E_DEVID 0x8686
203 /* Logical device 4 (Environmental Monitor) registers */
204 #define IT87_ACT_REG 0x30
205 #define IT87_BASE_REG 0x60
206 #define IT87_SPECIAL_CFG_REG 0xf3 /* special configuration register */
208 /* Global configuration registers (IT8712F and later) */
209 #define IT87_EC_HWM_MIO_REG 0x24 /* MMIO configuration register */
210 #define IT87_SIO_GPIO1_REG 0x25
211 #define IT87_SIO_GPIO2_REG 0x26
212 #define IT87_SIO_GPIO3_REG 0x27
213 #define IT87_SIO_GPIO4_REG 0x28
214 #define IT87_SIO_GPIO5_REG 0x29
215 #define IT87_SIO_GPIO9_REG 0xd3
216 #define IT87_SIO_PINX1_REG 0x2a /* Pin selection */
217 #define IT87_SIO_PINX2_REG 0x2c /* Pin selection */
218 #define IT87_SIO_PINX4_REG 0x2d /* Pin selection */
220 /* Logical device 7 (GPIO) registers (IT8712F and later) */
221 #define IT87_SIO_SPI_REG 0xef /* SPI function pin select */
222 #define IT87_SIO_VID_REG 0xfc /* VID value */
223 #define IT87_SIO_BEEP_PIN_REG 0xf6 /* Beep pin mapping */
225 /* Update battery voltage after every reading if true */
226 static bool update_vbat;
228 /* Not all BIOSes properly configure the PWM registers */
229 static bool fix_pwm_polarity;
231 /* Many IT87 constants specified below */
233 /* Length of ISA address segment */
234 #define IT87_EXTENT 8
236 /* Length of ISA address segment for Environmental Controller */
237 #define IT87_EC_EXTENT 2
239 /* Offset of EC registers from ISA base address */
240 #define IT87_EC_OFFSET 5
242 /* Where are the ISA address/data registers relative to the EC base address */
243 #define IT87_ADDR_REG_OFFSET 0
244 #define IT87_DATA_REG_OFFSET 1
246 /*----- The IT87 registers -----*/
248 #define IT87_REG_CONFIG 0x00
250 #define IT87_REG_ALARM1 0x01
251 #define IT87_REG_ALARM2 0x02
252 #define IT87_REG_ALARM3 0x03
254 #define IT87_REG_BANK 0x06
257 * The IT8718F and IT8720F have the VID value in a different register, in
258 * Super-I/O configuration space.
260 #define IT87_REG_VID 0x0a
262 /* Interface Selection register on other chips */
263 #define IT87_REG_IFSEL 0x0a
266 * The IT8705F and IT8712F earlier than revision 0x08 use register 0x0b
267 * for fan divisors. Later IT8712F revisions must use 16-bit tachometer
270 #define IT87_REG_FAN_DIV 0x0b
271 #define IT87_REG_FAN_16BIT 0x0c
275 * - up to 13 voltage (0 to 7, battery, avcc, 10 to 12)
276 * - up to 6 temp (1 to 6)
277 * - up to 6 fan (1 to 6)
280 static const u8 IT87_REG_FAN[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x4c };
281 static const u8 IT87_REG_FAN_MIN[] = { 0x10, 0x11, 0x12, 0x84, 0x86, 0x4e };
282 static const u8 IT87_REG_FANX[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x4d };
283 static const u8 IT87_REG_FANX_MIN[] = { 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0x4f };
285 static const u8 IT87_REG_FAN_8665[] = { 0x0d, 0x0e, 0x0f, 0x80, 0x82, 0x93 };
286 static const u8 IT87_REG_FAN_MIN_8665[] = {
287 0x10, 0x11, 0x12, 0x84, 0x86, 0xb2 };
288 static const u8 IT87_REG_FANX_8665[] = { 0x18, 0x19, 0x1a, 0x81, 0x83, 0x94 };
289 static const u8 IT87_REG_FANX_MIN_8665[] = {
290 0x1b, 0x1c, 0x1d, 0x85, 0x87, 0xb3 };
292 static const u8 IT87_REG_TEMP_OFFSET[] = { 0x56, 0x57, 0x59, 0x5a, 0x90, 0x91 };
294 static const u8 IT87_REG_TEMP_OFFSET_8686[] = {
295 0x56, 0x57, 0x59, 0x90, 0x91, 0x92 };
297 #define IT87_REG_FAN_MAIN_CTRL 0x13
298 #define IT87_REG_FAN_CTL 0x14
300 static const u8 IT87_REG_PWM[] = { 0x15, 0x16, 0x17, 0x7f, 0xa7, 0xaf };
301 static const u8 IT87_REG_PWM_8665[] = { 0x15, 0x16, 0x17, 0x1e, 0x1f, 0x92 };
303 static const u8 IT87_REG_PWM_DUTY[] = { 0x63, 0x6b, 0x73, 0x7b, 0xa3, 0xab };
305 static const u8 IT87_REG_VIN[] = { 0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26,
306 0x27, 0x28, 0x2f, 0x2c, 0x2d, 0x2e };
308 #define IT87_REG_TEMP(nr) (0x29 + (nr))
310 #define IT87_REG_VIN_MAX(nr) (0x30 + (nr) * 2)
311 #define IT87_REG_VIN_MIN(nr) (0x31 + (nr) * 2)
313 static const u8 IT87_REG_TEMP_HIGH[] = { 0x40, 0x42, 0x44, 0x46, 0xb4, 0xb6 };
314 static const u8 IT87_REG_TEMP_LOW[] = { 0x41, 0x43, 0x45, 0x47, 0xb5, 0xb7 };
316 static const u8 IT87_REG_TEMP_HIGH_8686[] = {
317 0x40, 0x42, 0x44, 0xb4, 0xb6, 0xb8 };
318 static const u8 IT87_REG_TEMP_LOW_8686[] = {
319 0x41, 0x43, 0x45, 0xb5, 0xb7, 0xb9 };
321 #define IT87_REG_VIN_ENABLE 0x50
322 #define IT87_REG_TEMP_ENABLE 0x51
323 #define IT87_REG_TEMP_EXTRA 0x55
324 #define IT87_REG_BEEP_ENABLE 0x5c
326 #define IT87_REG_CHIPID 0x58
328 static const u8 IT87_REG_AUTO_BASE[] = { 0x60, 0x68, 0x70, 0x78, 0xa0, 0xa8 };
330 #define IT87_REG_AUTO_TEMP(nr, i) (IT87_REG_AUTO_BASE[nr] + (i))
331 #define IT87_REG_AUTO_PWM(nr, i) (IT87_REG_AUTO_BASE[nr] + 5 + (i))
333 #define IT87_REG_TEMP456_ENABLE 0x77
335 static const u16 IT87_REG_TEMP_SRC1[] = { 0x21d, 0x21e, 0x21f };
336 #define IT87_REG_TEMP_SRC2 0x23d
338 #define NUM_VIN ARRAY_SIZE(IT87_REG_VIN)
339 #define NUM_VIN_LIMIT 8
341 #define NUM_FAN ARRAY_SIZE(IT87_REG_FAN)
342 #define NUM_FAN_DIV 3
343 #define NUM_PWM ARRAY_SIZE(IT87_REG_PWM)
344 #define NUM_AUTO_PWM ARRAY_SIZE(IT87_REG_PWM)
346 struct it87_devices {
348 const char * const model;
352 u8 num_temp_map; /* Number of temperature sources for pwm */
355 u8 smbus_bitmap; /* SMBus enable bits in extra config register */
356 u8 ec_special_config;
359 #define FEAT_12MV_ADC BIT(0)
360 #define FEAT_NEWER_AUTOPWM BIT(1)
361 #define FEAT_OLD_AUTOPWM BIT(2)
362 #define FEAT_16BIT_FANS BIT(3)
363 #define FEAT_TEMP_PECI BIT(5)
364 #define FEAT_TEMP_OLD_PECI BIT(6)
365 #define FEAT_FAN16_CONFIG BIT(7) /* Need to enable 16-bit fans */
366 #define FEAT_FIVE_FANS BIT(8) /* Supports five fans */
367 #define FEAT_VID BIT(9) /* Set if chip supports VID */
368 #define FEAT_IN7_INTERNAL BIT(10) /* Set if in7 is internal */
369 #define FEAT_SIX_FANS BIT(11) /* Supports six fans */
370 #define FEAT_10_9MV_ADC BIT(12)
371 #define FEAT_AVCC3 BIT(13) /* Chip supports in9/AVCC3 */
372 #define FEAT_FIVE_PWM BIT(14) /* Chip supports 5 pwm chn */
373 #define FEAT_SIX_PWM BIT(15) /* Chip supports 6 pwm chn */
374 #define FEAT_PWM_FREQ2 BIT(16) /* Separate pwm freq 2 */
375 #define FEAT_SIX_TEMP BIT(17) /* Up to 6 temp sensors */
376 #define FEAT_VIN3_5V BIT(18) /* VIN3 connected to +5V */
377 #define FEAT_FOUR_FANS BIT(19) /* Supports four fans */
378 #define FEAT_FOUR_PWM BIT(20) /* Supports four fan controls */
379 #define FEAT_BANK_SEL BIT(21) /* Chip has multi-bank support */
380 #define FEAT_SCALING BIT(22) /* Internal voltage scaling */
381 #define FEAT_FANCTL_ONOFF BIT(23) /* chip has FAN_CTL ON/OFF */
382 #define FEAT_11MV_ADC BIT(24)
383 #define FEAT_NEW_TEMPMAP BIT(25) /* new temp input selection */
384 #define FEAT_MMIO BIT(26) /* Chip supports MMIO */
385 #define FEAT_FOUR_TEMP BIT(27)
387 static const struct it87_devices it87_devices[] = {
391 .features = FEAT_OLD_AUTOPWM | FEAT_FANCTL_ONOFF,
392 /* may need to overwrite */
394 .num_temp_offset = 0,
400 .features = FEAT_OLD_AUTOPWM | FEAT_VID | FEAT_FANCTL_ONOFF,
401 /* may need to overwrite */
403 .num_temp_offset = 0,
409 .features = FEAT_16BIT_FANS | FEAT_VID
410 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_PWM_FREQ2
413 .num_temp_offset = 3,
419 .features = FEAT_16BIT_FANS | FEAT_VID
420 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
421 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
423 .num_temp_offset = 3,
425 .old_peci_mask = 0x4,
430 .features = FEAT_16BIT_FANS | FEAT_VID
431 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS
432 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
434 .num_temp_offset = 3,
436 .old_peci_mask = 0x4,
441 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
442 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
443 | FEAT_FAN16_CONFIG | FEAT_FIVE_FANS | FEAT_IN7_INTERNAL
444 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
446 .num_temp_offset = 3,
449 .old_peci_mask = 0x02, /* Actually reports PCH */
454 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
455 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
456 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_SCALING
459 .num_temp_offset = 3,
466 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
467 | FEAT_TEMP_OLD_PECI | FEAT_TEMP_PECI
468 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_FOUR_FANS
469 | FEAT_FOUR_PWM | FEAT_FANCTL_ONOFF,
471 .num_temp_offset = 3,
474 .old_peci_mask = 0x02, /* Actually reports PCH */
479 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
480 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
481 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
482 /* PECI: guesswork */
484 /* 16 bit fans (OHM) */
485 /* three fans, always 16 bit (guesswork) */
487 .num_temp_offset = 3,
494 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
495 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
496 | FEAT_PWM_FREQ2 | FEAT_SCALING | FEAT_FANCTL_ONOFF,
497 /* PECI (coreboot) */
498 /* 12mV ADC (HWSensors4, OHM) */
499 /* 16 bit fans (HWSensors4, OHM) */
500 /* three fans, always 16 bit (datasheet) */
502 .num_temp_offset = 3,
509 .features = FEAT_16BIT_FANS
510 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
513 .num_temp_offset = 3,
515 .old_peci_mask = 0x4,
520 .features = FEAT_16BIT_FANS
521 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
524 .num_temp_offset = 3,
526 .old_peci_mask = 0x4,
530 .model = "IT8783E/F",
531 .features = FEAT_16BIT_FANS
532 | FEAT_TEMP_OLD_PECI | FEAT_FAN16_CONFIG | FEAT_PWM_FREQ2
535 .num_temp_offset = 3,
537 .old_peci_mask = 0x4,
542 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
543 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
544 | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
546 .num_temp_offset = 3,
553 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
554 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
555 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
557 .num_temp_offset = 3,
563 .model = "IT8792E/IT8795E",
564 .features = FEAT_NEWER_AUTOPWM | FEAT_10_9MV_ADC | FEAT_SCALING
565 | FEAT_16BIT_FANS | FEAT_TEMP_PECI
566 | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2 | FEAT_FANCTL_ONOFF,
568 .num_temp_offset = 3,
575 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
576 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
577 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
579 .num_temp_offset = 3,
586 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
587 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL
588 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING,
590 .num_temp_offset = 3,
597 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
598 | FEAT_TEMP_PECI | FEAT_IN7_INTERNAL | FEAT_NEW_TEMPMAP
599 | FEAT_AVCC3 | FEAT_PWM_FREQ2 | FEAT_SCALING
602 .num_temp_offset = 3,
609 .features = FEAT_NEWER_AUTOPWM | FEAT_11MV_ADC | FEAT_16BIT_FANS
610 | FEAT_TEMP_PECI | FEAT_FIVE_FANS
611 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
612 | FEAT_AVCC3 | FEAT_SCALING | FEAT_NEW_TEMPMAP,
614 .num_temp_offset = 6,
621 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
622 | FEAT_TEMP_PECI | FEAT_SIX_FANS
623 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
624 | FEAT_SIX_TEMP | FEAT_VIN3_5V | FEAT_SCALING
627 .num_temp_offset = 3,
634 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
635 | FEAT_TEMP_PECI | FEAT_FIVE_FANS | FEAT_FOUR_TEMP
636 | FEAT_FIVE_PWM | FEAT_IN7_INTERNAL | FEAT_PWM_FREQ2
637 | FEAT_AVCC3 | FEAT_VIN3_5V | FEAT_SCALING,
639 .num_temp_offset = 3,
642 .smbus_bitmap = BIT(1) | BIT(2),
647 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
648 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP
649 | FEAT_11MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
650 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_SCALING,
652 .num_temp_offset = 6,
654 .smbus_bitmap = BIT(1) | BIT(2),
659 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
660 | FEAT_TEMP_PECI | FEAT_SIX_FANS
661 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
662 | FEAT_SIX_TEMP | FEAT_SCALING | FEAT_AVCC3
665 .num_temp_offset = 3,
672 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
673 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
674 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_BANK_SEL
677 .num_temp_offset = 6,
679 .smbus_bitmap = BIT(2),
684 .features = FEAT_NEWER_AUTOPWM | FEAT_16BIT_FANS
685 | FEAT_AVCC3 | FEAT_NEW_TEMPMAP | FEAT_SCALING
686 | FEAT_10_9MV_ADC | FEAT_IN7_INTERNAL | FEAT_SIX_FANS
687 | FEAT_SIX_PWM | FEAT_BANK_SEL | FEAT_MMIO,
689 .num_temp_offset = 6,
691 .smbus_bitmap = BIT(2),
696 .features = FEAT_NEWER_AUTOPWM | FEAT_12MV_ADC | FEAT_16BIT_FANS
697 | FEAT_SIX_FANS | FEAT_NEW_TEMPMAP
698 | FEAT_IN7_INTERNAL | FEAT_SIX_PWM | FEAT_PWM_FREQ2
699 | FEAT_SIX_TEMP | FEAT_BANK_SEL | FEAT_SCALING | FEAT_AVCC3,
701 .num_temp_offset = 6,
703 .smbus_bitmap = BIT(1) | BIT(2),
707 #define has_16bit_fans(data) ((data)->features & FEAT_16BIT_FANS)
708 #define has_12mv_adc(data) ((data)->features & FEAT_12MV_ADC)
709 #define has_10_9mv_adc(data) ((data)->features & FEAT_10_9MV_ADC)
710 #define has_newer_autopwm(data) ((data)->features & FEAT_NEWER_AUTOPWM)
711 #define has_old_autopwm(data) ((data)->features & FEAT_OLD_AUTOPWM)
712 #define has_temp_peci(data, nr) (((data)->features & FEAT_TEMP_PECI) && \
713 ((data)->peci_mask & BIT(nr)))
714 #define has_temp_old_peci(data, nr) \
715 (((data)->features & FEAT_TEMP_OLD_PECI) && \
716 ((data)->old_peci_mask & BIT(nr)))
717 #define has_fan16_config(data) ((data)->features & FEAT_FAN16_CONFIG)
718 #define has_five_fans(data) ((data)->features & (FEAT_FIVE_FANS | \
720 #define has_vid(data) ((data)->features & FEAT_VID)
721 #define has_in7_internal(data) ((data)->features & FEAT_IN7_INTERNAL)
722 #define has_six_fans(data) ((data)->features & FEAT_SIX_FANS)
723 #define has_avcc3(data) ((data)->features & FEAT_AVCC3)
724 #define has_five_pwm(data) ((data)->features & (FEAT_FIVE_PWM \
726 #define has_six_pwm(data) ((data)->features & FEAT_SIX_PWM)
727 #define has_pwm_freq2(data) ((data)->features & FEAT_PWM_FREQ2)
728 #define has_six_temp(data) ((data)->features & FEAT_SIX_TEMP)
729 #define has_vin3_5v(data) ((data)->features & FEAT_VIN3_5V)
730 #define has_four_fans(data) ((data)->features & (FEAT_FOUR_FANS | \
733 #define has_four_pwm(data) ((data)->features & (FEAT_FOUR_PWM | \
736 #define has_bank_sel(data) ((data)->features & FEAT_BANK_SEL)
737 #define has_scaling(data) ((data)->features & FEAT_SCALING)
738 #define has_fanctl_onoff(data) ((data)->features & FEAT_FANCTL_ONOFF)
739 #define has_11mv_adc(data) ((data)->features & FEAT_11MV_ADC)
740 #define has_new_tempmap(data) ((data)->features & FEAT_NEW_TEMPMAP)
741 #define has_mmio(data) ((data)->features & FEAT_MMIO)
742 #define has_four_temp(data) ((data)->features & FEAT_FOUR_TEMP)
744 struct it87_sio_data {
748 /* Values read from Super-I/O config space */
752 u8 internal; /* Internal sensors can be labeled */
753 /* Features skipped based on config or DMI */
760 u8 ec_special_config;
764 * For each registered chip, we need to keep some data in memory.
765 * The structure is dynamically allocated.
768 const struct attribute_group *groups[7];
774 u8 smbus_bitmap; /* !=0 if SMBus needs to be disabled */
775 u8 ec_special_config; /* EC special config register restore value */
776 u8 sioaddr; /* SIO port address */
777 bool doexit; /* true if exit from sio config is ok */
779 void __iomem *mmio; /* Remapped MMIO address if available */
780 int (*read)(struct it87_data *, u16);
781 void (*write)(struct it87_data *, u16, u8);
785 const u8 *REG_FAN_MIN;
786 const u8 *REG_FANX_MIN;
790 const u8 *REG_TEMP_OFFSET;
791 const u8 *REG_TEMP_LOW;
792 const u8 *REG_TEMP_HIGH;
795 struct mutex update_lock;
796 char valid; /* !=0 if following fields are valid */
797 unsigned long last_updated; /* In jiffies */
799 u16 in_scaled; /* Internal voltage sensors are scaled */
800 u16 in_internal; /* Bitfield, internal sensors (for labels) */
801 u16 has_in; /* Bitfield, voltage sensors enabled */
802 u8 in[NUM_VIN][3]; /* [nr][0]=in, [1]=min, [2]=max */
803 u8 has_fan; /* Bitfield, fans enabled */
804 u16 fan[NUM_FAN][2]; /* Register values, [nr][0]=fan, [1]=min */
805 u8 has_temp; /* Bitfield, temp sensors enabled */
806 s8 temp[NUM_TEMP][4]; /* [nr][0]=temp, [1]=min, [2]=max, [3]=offset */
807 u8 num_temp_limit; /* Number of temperature limit registers */
808 u8 num_temp_offset; /* Number of temperature offset registers */
809 u8 temp_src[4]; /* Up to 4 temperature source registers */
810 u8 sensor; /* Register value (IT87_REG_TEMP_ENABLE) */
811 u8 extra; /* Register value (IT87_REG_TEMP_EXTRA) */
812 u8 fan_div[NUM_FAN_DIV];/* Register encoding, shifted right */
813 bool has_vid; /* True if VID supported */
814 u8 vid; /* Register encoding, combined */
816 u32 alarms; /* Register encoding, combined */
817 bool has_beep; /* true if beep supported */
818 u8 beeps; /* Register encoding */
819 u8 fan_main_ctrl; /* Register value */
820 u8 fan_ctl; /* Register value */
823 * The following 3 arrays correspond to the same registers up to
824 * the IT8720F. The meaning of bits 6-0 depends on the value of bit
825 * 7, and we want to preserve settings on mode changes, so we have
826 * to track all values separately.
827 * Starting with the IT8721F, the manual PWM duty cycles are stored
828 * in separate registers (8-bit values), so the separate tracking
829 * is no longer needed, but it is still done to keep the driver
832 u8 has_pwm; /* Bitfield, pwm control enabled */
833 u8 pwm_ctrl[NUM_PWM]; /* Register value */
834 u8 pwm_duty[NUM_PWM]; /* Manual PWM value set by user */
835 u8 pwm_temp_map[NUM_PWM];/* PWM to temp. chan. mapping (bits 1-0) */
836 u8 pwm_temp_map_mask; /* 0x03 for old, 0x07 for new temp map */
837 u8 pwm_temp_map_shift; /* 0 for old, 3 for new temp map */
838 u8 pwm_num_temp_map; /* from config data, 3..7 depending on chip */
840 /* Automatic fan speed control registers */
841 u8 auto_pwm[NUM_AUTO_PWM][4]; /* [nr][3] is hard-coded */
842 s8 auto_temp[NUM_AUTO_PWM][5]; /* [nr][0] is point1_temp_hyst */
845 static int adc_lsb(const struct it87_data *data, int nr)
849 if (has_12mv_adc(data))
851 else if (has_10_9mv_adc(data))
853 else if (has_11mv_adc(data))
857 if (data->in_scaled & BIT(nr))
862 static u8 in_to_reg(const struct it87_data *data, int nr, long val)
864 val = DIV_ROUND_CLOSEST(val * 10, adc_lsb(data, nr));
865 return clamp_val(val, 0, 255);
868 static int in_from_reg(const struct it87_data *data, int nr, int val)
870 return DIV_ROUND_CLOSEST(val * adc_lsb(data, nr), 10);
873 static inline u8 FAN_TO_REG(long rpm, int div)
877 rpm = clamp_val(rpm, 1, 1000000);
878 return clamp_val((1350000 + rpm * div / 2) / (rpm * div), 1, 254);
881 static inline u16 FAN16_TO_REG(long rpm)
885 return clamp_val((1350000 + rpm) / (rpm * 2), 1, 0xfffe);
888 #define FAN_FROM_REG(val, div) ((val) == 0 ? -1 : (val) == 255 ? 0 : \
889 1350000 / ((val) * (div)))
890 /* The divider is fixed to 2 in 16-bit mode */
891 #define FAN16_FROM_REG(val) ((val) == 0 ? -1 : (val) == 0xffff ? 0 : \
892 1350000 / ((val) * 2))
894 #define TEMP_TO_REG(val) (clamp_val(((val) < 0 ? (((val) - 500) / 1000) : \
895 ((val) + 500) / 1000), -128, 127))
896 #define TEMP_FROM_REG(val) ((val) * 1000)
898 static u8 pwm_to_reg(const struct it87_data *data, long val)
900 if (has_newer_autopwm(data))
906 static int pwm_from_reg(const struct it87_data *data, u8 reg)
908 if (has_newer_autopwm(data))
911 return (reg & 0x7f) << 1;
914 static int DIV_TO_REG(int val)
918 while (answer < 7 && (val >>= 1))
923 #define DIV_FROM_REG(val) BIT(val)
925 static u8 temp_map_from_reg(const struct it87_data *data, u8 reg)
929 map = (reg >> data->pwm_temp_map_shift) & data->pwm_temp_map_mask;
930 if (map >= data->pwm_num_temp_map) /* map is 0-based */
936 static u8 temp_map_to_reg(const struct it87_data *data, int nr, u8 map)
938 u8 ctrl = data->pwm_ctrl[nr];
940 return (ctrl & ~(data->pwm_temp_map_mask << data->pwm_temp_map_shift)) |
941 (map << data->pwm_temp_map_shift);
945 * PWM base frequencies. The frequency has to be divided by either 128 or 256,
946 * depending on the chip type, to calculate the actual PWM frequency.
948 * Some of the chip datasheets suggest a base frequency of 51 kHz instead
949 * of 750 kHz for the slowest base frequency, resulting in a PWM frequency
950 * of 200 Hz. Sometimes both PWM frequency select registers are affected,
951 * sometimes just one. It is unknown if this is a datasheet error or real,
952 * so this is ignored for now.
954 static const unsigned int pwm_freq[8] = {
965 static int smbus_disable(struct it87_data *data)
969 if (data->smbus_bitmap) {
970 err = superio_enter(data->sioaddr);
973 superio_select(data->sioaddr, PME);
974 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
975 data->ec_special_config & ~data->smbus_bitmap);
976 superio_exit(data->sioaddr, data->doexit);
981 static int smbus_enable(struct it87_data *data)
985 if (data->smbus_bitmap) {
986 err = superio_enter(data->sioaddr);
990 superio_select(data->sioaddr, PME);
991 superio_outb(data->sioaddr, IT87_SPECIAL_CFG_REG,
992 data->ec_special_config);
993 superio_exit(data->sioaddr, data->doexit);
998 static int _it87_io_read(struct it87_data *data, u16 reg)
1000 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1001 return inb_p(data->addr + IT87_DATA_REG_OFFSET);
1004 static void _it87_io_write(struct it87_data *data, u16 reg, u8 value)
1006 outb_p(reg, data->addr + IT87_ADDR_REG_OFFSET);
1007 outb_p(value, data->addr + IT87_DATA_REG_OFFSET);
1010 static u8 it87_io_set_bank(struct it87_data *data, u8 bank)
1014 if (has_bank_sel(data)) {
1015 u8 breg = _it87_io_read(data, IT87_REG_BANK);
1018 if (bank != _bank) {
1020 breg |= (bank << 5);
1021 _it87_io_write(data, IT87_REG_BANK, breg);
1028 * Must be called with data->update_lock held, except during initialization.
1029 * Must be called with SMBus accesses disabled.
1030 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1031 * would slow down the IT87 access and should not be necessary.
1033 static int it87_io_read(struct it87_data *data, u16 reg)
1038 bank = it87_io_set_bank(data, reg >> 8);
1039 val = _it87_io_read(data, reg & 0xff);
1040 it87_io_set_bank(data, bank);
1046 * Must be called with data->update_lock held, except during initialization.
1047 * Must be called with SMBus accesses disabled
1048 * We ignore the IT87 BUSY flag at this moment - it could lead to deadlocks,
1049 * would slow down the IT87 access and should not be necessary.
1051 static void it87_io_write(struct it87_data *data, u16 reg, u8 value)
1055 bank = it87_io_set_bank(data, reg >> 8);
1056 _it87_io_write(data, reg & 0xff, value);
1057 it87_io_set_bank(data, bank);
1060 static int it87_mmio_read(struct it87_data *data, u16 reg)
1062 return readb(data->mmio + reg);
1065 static void it87_mmio_write(struct it87_data *data, u16 reg, u8 value)
1067 writeb(value, data->mmio + reg);
1070 static void it87_update_pwm_ctrl(struct it87_data *data, int nr)
1074 ctrl = data->read(data, data->REG_PWM[nr]);
1075 data->pwm_ctrl[nr] = ctrl;
1076 if (has_newer_autopwm(data)) {
1077 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1078 data->pwm_duty[nr] = data->read(data, IT87_REG_PWM_DUTY[nr]);
1080 if (ctrl & 0x80) /* Automatic mode */
1081 data->pwm_temp_map[nr] = temp_map_from_reg(data, ctrl);
1082 else /* Manual mode */
1083 data->pwm_duty[nr] = ctrl & 0x7f;
1086 if (has_old_autopwm(data)) {
1089 for (i = 0; i < 5 ; i++)
1090 data->auto_temp[nr][i] = data->read(data,
1091 IT87_REG_AUTO_TEMP(nr, i));
1092 for (i = 0; i < 3 ; i++)
1093 data->auto_pwm[nr][i] = data->read(data,
1094 IT87_REG_AUTO_PWM(nr, i));
1095 } else if (has_newer_autopwm(data)) {
1099 * 0: temperature hysteresis (base + 5)
1100 * 1: fan off temperature (base + 0)
1101 * 2: fan start temperature (base + 1)
1102 * 3: fan max temperature (base + 2)
1104 data->auto_temp[nr][0] =
1105 data->read(data, IT87_REG_AUTO_TEMP(nr, 5));
1107 for (i = 0; i < 3 ; i++)
1108 data->auto_temp[nr][i + 1] =
1109 data->read(data, IT87_REG_AUTO_TEMP(nr, i));
1111 * 0: start pwm value (base + 3)
1112 * 1: pwm slope (base + 4, 1/8th pwm)
1114 data->auto_pwm[nr][0] =
1115 data->read(data, IT87_REG_AUTO_TEMP(nr, 3));
1116 data->auto_pwm[nr][1] =
1117 data->read(data, IT87_REG_AUTO_TEMP(nr, 4));
1121 static int it87_lock(struct it87_data *data)
1125 mutex_lock(&data->update_lock);
1126 err = smbus_disable(data);
1128 mutex_unlock(&data->update_lock);
1132 static void it87_unlock(struct it87_data *data)
1135 mutex_unlock(&data->update_lock);
1138 static struct it87_data *it87_update_device(struct device *dev)
1140 struct it87_data *data = dev_get_drvdata(dev);
1141 struct it87_data *ret = data;
1145 mutex_lock(&data->update_lock);
1147 if (time_after(jiffies, data->last_updated + HZ + HZ / 2) ||
1149 err = smbus_disable(data);
1156 * Cleared after each update, so reenable. Value
1157 * returned by this read will be previous value
1159 data->write(data, IT87_REG_CONFIG,
1160 data->read(data, IT87_REG_CONFIG) | 0x40);
1162 for (i = 0; i < NUM_VIN; i++) {
1163 if (!(data->has_in & BIT(i)))
1166 data->in[i][0] = data->read(data, IT87_REG_VIN[i]);
1168 /* VBAT and AVCC don't have limit registers */
1169 if (i >= NUM_VIN_LIMIT)
1172 data->in[i][1] = data->read(data, IT87_REG_VIN_MIN(i));
1173 data->in[i][2] = data->read(data, IT87_REG_VIN_MAX(i));
1176 for (i = 0; i < NUM_FAN; i++) {
1177 /* Skip disabled fans */
1178 if (!(data->has_fan & BIT(i)))
1181 data->fan[i][1] = data->read(data,
1182 data->REG_FAN_MIN[i]);
1183 data->fan[i][0] = data->read(data, data->REG_FAN[i]);
1184 /* Add high byte if in 16-bit mode */
1185 if (has_16bit_fans(data)) {
1186 data->fan[i][0] |= data->read(data,
1187 data->REG_FANX[i]) << 8;
1188 data->fan[i][1] |= data->read(data,
1189 data->REG_FANX_MIN[i]) << 8;
1192 for (i = 0; i < NUM_TEMP; i++) {
1193 if (!(data->has_temp & BIT(i)))
1196 data->read(data, IT87_REG_TEMP(i));
1198 if (i >= data->num_temp_limit)
1201 if (i < data->num_temp_offset)
1203 data->read(data, data->REG_TEMP_OFFSET[i]);
1206 data->read(data, data->REG_TEMP_LOW[i]);
1208 data->read(data, data->REG_TEMP_HIGH[i]);
1211 /* Newer chips don't have clock dividers */
1212 if ((data->has_fan & 0x07) && !has_16bit_fans(data)) {
1213 i = data->read(data, IT87_REG_FAN_DIV);
1214 data->fan_div[0] = i & 0x07;
1215 data->fan_div[1] = (i >> 3) & 0x07;
1216 data->fan_div[2] = (i & 0x40) ? 3 : 1;
1220 data->read(data, IT87_REG_ALARM1) |
1221 (data->read(data, IT87_REG_ALARM2) << 8) |
1222 (data->read(data, IT87_REG_ALARM3) << 16);
1223 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
1225 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
1226 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL);
1227 for (i = 0; i < NUM_PWM; i++) {
1228 if (!(data->has_pwm & BIT(i)))
1230 it87_update_pwm_ctrl(data, i);
1233 data->sensor = data->read(data, IT87_REG_TEMP_ENABLE);
1234 data->extra = data->read(data, IT87_REG_TEMP_EXTRA);
1236 * The IT8705F does not have VID capability.
1237 * The IT8718F and later don't use IT87_REG_VID for the
1240 if (data->type == it8712 || data->type == it8716) {
1241 data->vid = data->read(data, IT87_REG_VID);
1243 * The older IT8712F revisions had only 5 VID pins,
1244 * but we assume it is always safe to read 6 bits.
1248 data->last_updated = jiffies;
1253 mutex_unlock(&data->update_lock);
1257 static ssize_t show_in(struct device *dev, struct device_attribute *attr,
1260 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1261 struct it87_data *data = it87_update_device(dev);
1262 int index = sattr->index;
1266 return PTR_ERR(data);
1268 return sprintf(buf, "%d\n", in_from_reg(data, nr, data->in[nr][index]));
1271 static ssize_t set_in(struct device *dev, struct device_attribute *attr,
1272 const char *buf, size_t count)
1274 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1275 struct it87_data *data = dev_get_drvdata(dev);
1276 int index = sattr->index;
1281 if (kstrtoul(buf, 10, &val) < 0)
1284 err = it87_lock(data);
1288 data->in[nr][index] = in_to_reg(data, nr, val);
1289 data->write(data, index == 1 ? IT87_REG_VIN_MIN(nr)
1290 : IT87_REG_VIN_MAX(nr),
1291 data->in[nr][index]);
1296 static SENSOR_DEVICE_ATTR_2(in0_input, 0444, show_in, NULL, 0, 0);
1297 static SENSOR_DEVICE_ATTR_2(in0_min, 0644, show_in, set_in, 0, 1);
1298 static SENSOR_DEVICE_ATTR_2(in0_max, 0644, show_in, set_in, 0, 2);
1300 static SENSOR_DEVICE_ATTR_2(in1_input, 0444, show_in, NULL, 1, 0);
1301 static SENSOR_DEVICE_ATTR_2(in1_min, 0644, show_in, set_in, 1, 1);
1302 static SENSOR_DEVICE_ATTR_2(in1_max, 0644, show_in, set_in, 1, 2);
1304 static SENSOR_DEVICE_ATTR_2(in2_input, 0444, show_in, NULL, 2, 0);
1305 static SENSOR_DEVICE_ATTR_2(in2_min, 0644, show_in, set_in, 2, 1);
1306 static SENSOR_DEVICE_ATTR_2(in2_max, 0644, show_in, set_in, 2, 2);
1308 static SENSOR_DEVICE_ATTR_2(in3_input, 0444, show_in, NULL, 3, 0);
1309 static SENSOR_DEVICE_ATTR_2(in3_min, 0644, show_in, set_in, 3, 1);
1310 static SENSOR_DEVICE_ATTR_2(in3_max, 0644, show_in, set_in, 3, 2);
1312 static SENSOR_DEVICE_ATTR_2(in4_input, 0444, show_in, NULL, 4, 0);
1313 static SENSOR_DEVICE_ATTR_2(in4_min, 0644, show_in, set_in, 4, 1);
1314 static SENSOR_DEVICE_ATTR_2(in4_max, 0644, show_in, set_in, 4, 2);
1316 static SENSOR_DEVICE_ATTR_2(in5_input, 0444, show_in, NULL, 5, 0);
1317 static SENSOR_DEVICE_ATTR_2(in5_min, 0644, show_in, set_in, 5, 1);
1318 static SENSOR_DEVICE_ATTR_2(in5_max, 0644, show_in, set_in, 5, 2);
1320 static SENSOR_DEVICE_ATTR_2(in6_input, 0444, show_in, NULL, 6, 0);
1321 static SENSOR_DEVICE_ATTR_2(in6_min, 0644, show_in, set_in, 6, 1);
1322 static SENSOR_DEVICE_ATTR_2(in6_max, 0644, show_in, set_in, 6, 2);
1324 static SENSOR_DEVICE_ATTR_2(in7_input, 0444, show_in, NULL, 7, 0);
1325 static SENSOR_DEVICE_ATTR_2(in7_min, 0644, show_in, set_in, 7, 1);
1326 static SENSOR_DEVICE_ATTR_2(in7_max, 0644, show_in, set_in, 7, 2);
1328 static SENSOR_DEVICE_ATTR_2(in8_input, 0444, show_in, NULL, 8, 0);
1329 static SENSOR_DEVICE_ATTR_2(in9_input, 0444, show_in, NULL, 9, 0);
1330 static SENSOR_DEVICE_ATTR_2(in10_input, 0444, show_in, NULL, 10, 0);
1331 static SENSOR_DEVICE_ATTR_2(in11_input, 0444, show_in, NULL, 11, 0);
1332 static SENSOR_DEVICE_ATTR_2(in12_input, 0444, show_in, NULL, 12, 0);
1334 /* Up to 6 temperatures */
1335 static ssize_t show_temp(struct device *dev, struct device_attribute *attr,
1338 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1340 int index = sattr->index;
1341 struct it87_data *data = it87_update_device(dev);
1344 return PTR_ERR(data);
1346 return sprintf(buf, "%d\n", TEMP_FROM_REG(data->temp[nr][index]));
1349 static ssize_t set_temp(struct device *dev, struct device_attribute *attr,
1350 const char *buf, size_t count)
1352 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1354 int index = sattr->index;
1355 struct it87_data *data = dev_get_drvdata(dev);
1360 if (kstrtol(buf, 10, &val) < 0)
1363 err = it87_lock(data);
1370 reg = data->REG_TEMP_LOW[nr];
1373 reg = data->REG_TEMP_HIGH[nr];
1376 regval = data->read(data, IT87_REG_BEEP_ENABLE);
1377 if (!(regval & 0x80)) {
1379 data->write(data, IT87_REG_BEEP_ENABLE, regval);
1382 reg = data->REG_TEMP_OFFSET[nr];
1386 data->temp[nr][index] = TEMP_TO_REG(val);
1387 data->write(data, reg, data->temp[nr][index]);
1392 static SENSOR_DEVICE_ATTR_2(temp1_input, 0444, show_temp, NULL, 0, 0);
1393 static SENSOR_DEVICE_ATTR_2(temp1_min, 0644, show_temp, set_temp, 0, 1);
1394 static SENSOR_DEVICE_ATTR_2(temp1_max, 0644, show_temp, set_temp, 0, 2);
1395 static SENSOR_DEVICE_ATTR_2(temp1_offset, 0644, show_temp, set_temp, 0, 3);
1396 static SENSOR_DEVICE_ATTR_2(temp2_input, 0444, show_temp, NULL, 1, 0);
1397 static SENSOR_DEVICE_ATTR_2(temp2_min, 0644, show_temp, set_temp, 1, 1);
1398 static SENSOR_DEVICE_ATTR_2(temp2_max, 0644, show_temp, set_temp, 1, 2);
1399 static SENSOR_DEVICE_ATTR_2(temp2_offset, 0644, show_temp, set_temp, 1, 3);
1400 static SENSOR_DEVICE_ATTR_2(temp3_input, 0444, show_temp, NULL, 2, 0);
1401 static SENSOR_DEVICE_ATTR_2(temp3_min, 0644, show_temp, set_temp, 2, 1);
1402 static SENSOR_DEVICE_ATTR_2(temp3_max, 0644, show_temp, set_temp, 2, 2);
1403 static SENSOR_DEVICE_ATTR_2(temp3_offset, 0644, show_temp, set_temp, 2, 3);
1404 static SENSOR_DEVICE_ATTR_2(temp4_input, 0444, show_temp, NULL, 3, 0);
1405 static SENSOR_DEVICE_ATTR_2(temp4_min, 0644, show_temp, set_temp, 3, 1);
1406 static SENSOR_DEVICE_ATTR_2(temp4_max, 0644, show_temp, set_temp, 3, 2);
1407 static SENSOR_DEVICE_ATTR_2(temp4_offset, 0644, show_temp, set_temp, 3, 3);
1408 static SENSOR_DEVICE_ATTR_2(temp5_input, 0444, show_temp, NULL, 4, 0);
1409 static SENSOR_DEVICE_ATTR_2(temp5_min, 0644, show_temp, set_temp, 4, 1);
1410 static SENSOR_DEVICE_ATTR_2(temp5_max, 0644, show_temp, set_temp, 4, 2);
1411 static SENSOR_DEVICE_ATTR_2(temp5_offset, 0644, show_temp, set_temp, 4, 3);
1412 static SENSOR_DEVICE_ATTR_2(temp6_input, 0444, show_temp, NULL, 5, 0);
1413 static SENSOR_DEVICE_ATTR_2(temp6_min, 0644, show_temp, set_temp, 5, 1);
1414 static SENSOR_DEVICE_ATTR_2(temp6_max, 0644, show_temp, set_temp, 5, 2);
1415 static SENSOR_DEVICE_ATTR_2(temp6_offset, 0644, show_temp, set_temp, 5, 3);
1417 static const u8 temp_types_8686[NUM_TEMP][9] = {
1418 { 0, 8, 8, 8, 8, 8, 8, 8, 7 },
1419 { 0, 6, 8, 8, 6, 0, 0, 0, 7 },
1420 { 0, 6, 5, 8, 6, 0, 0, 0, 7 },
1421 { 4, 8, 8, 8, 8, 8, 8, 8, 7 },
1422 { 4, 6, 8, 8, 6, 0, 0, 0, 7 },
1423 { 4, 6, 5, 8, 6, 0, 0, 0, 7 },
1426 static int get_temp_type(struct it87_data *data, int index)
1429 int ttype, type = 0;
1431 if (has_bank_sel(data)) {
1434 src1 = (data->temp_src[index / 2] >> ((index % 2) * 4)) & 0x0f;
1436 switch (data->type) {
1439 type = temp_types_8686[index][src1];
1450 src2 = data->temp_src[3];
1453 type = (src2 & BIT(index)) ? 6 : 5;
1456 type = (src2 & BIT(index)) ? 4 : 6;
1459 type = (src2 & BIT(index)) ? 5 : 0;
1472 /* Dectect PECI vs. AMDTSI */
1474 if ((has_temp_peci(data, index)) || data->type == it8721 ||
1475 data->type == it8720) {
1476 extra = data->read(data, IT87_REG_IFSEL);
1477 if ((extra & 0x70) == 0x40)
1481 reg = data->read(data, IT87_REG_TEMP_ENABLE);
1483 /* Per chip special detection */
1484 switch (data->type) {
1486 if (!(reg & 0xc0) && index == 3)
1493 if (type || index >= 3)
1496 extra = data->read(data, IT87_REG_TEMP_EXTRA);
1498 if ((has_temp_peci(data, index) && (reg >> 6 == index + 1)) ||
1499 (has_temp_old_peci(data, index) && (extra & 0x80)))
1500 type = ttype; /* Intel PECI or AMDTSI */
1501 if (reg & BIT(index))
1502 type = 3; /* thermal diode */
1503 else if (reg & BIT(index + 3))
1504 type = 4; /* thermistor */
1509 static ssize_t show_temp_type(struct device *dev, struct device_attribute *attr,
1512 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1513 struct it87_data *data = it87_update_device(dev);
1517 return PTR_ERR(data);
1519 type = get_temp_type(data, sensor_attr->index);
1520 return sprintf(buf, "%d\n", type);
1523 static ssize_t set_temp_type(struct device *dev, struct device_attribute *attr,
1524 const char *buf, size_t count)
1526 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1527 int nr = sensor_attr->index;
1529 struct it87_data *data = dev_get_drvdata(dev);
1534 if (kstrtol(buf, 10, &val) < 0)
1537 err = it87_lock(data);
1541 reg = data->read(data, IT87_REG_TEMP_ENABLE);
1544 if (has_temp_peci(data, nr) && (reg >> 6 == nr + 1 || val == 6))
1546 extra = data->read(data, IT87_REG_TEMP_EXTRA);
1547 if (has_temp_old_peci(data, nr) && ((extra & 0x80) || val == 6))
1549 if (val == 2) { /* backwards compatibility */
1551 "Sensor type 2 is deprecated, please use 4 instead\n");
1554 /* 3 = thermal diode; 4 = thermistor; 6 = Intel PECI; 0 = disabled */
1559 else if (has_temp_peci(data, nr) && val == 6)
1560 reg |= (nr + 1) << 6;
1561 else if (has_temp_old_peci(data, nr) && val == 6)
1563 else if (val != 0) {
1569 data->extra = extra;
1570 data->write(data, IT87_REG_TEMP_ENABLE, data->sensor);
1571 if (has_temp_old_peci(data, nr))
1572 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1573 data->valid = 0; /* Force cache refresh */
1579 static SENSOR_DEVICE_ATTR(temp1_type, 0644, show_temp_type, set_temp_type, 0);
1580 static SENSOR_DEVICE_ATTR(temp2_type, 0644, show_temp_type, set_temp_type, 1);
1581 static SENSOR_DEVICE_ATTR(temp3_type, 0644, show_temp_type, set_temp_type, 2);
1582 static SENSOR_DEVICE_ATTR(temp4_type, 0644, show_temp_type, set_temp_type, 3);
1583 static SENSOR_DEVICE_ATTR(temp5_type, 0644, show_temp_type, set_temp_type, 4);
1584 static SENSOR_DEVICE_ATTR(temp6_type, 0644, show_temp_type, set_temp_type, 5);
1588 static int pwm_mode(const struct it87_data *data, int nr)
1590 if (has_fanctl_onoff(data) && nr < 3 &&
1591 !(data->fan_main_ctrl & BIT(nr)))
1592 return 0; /* Full speed */
1593 if (data->pwm_ctrl[nr] & 0x80)
1594 return 2; /* Automatic mode */
1595 if ((!has_fanctl_onoff(data) || nr >= 3) &&
1596 data->pwm_duty[nr] == pwm_to_reg(data, 0xff))
1597 return 0; /* Full speed */
1599 return 1; /* Manual mode */
1602 static ssize_t show_fan(struct device *dev, struct device_attribute *attr,
1605 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1607 int index = sattr->index;
1609 struct it87_data *data = it87_update_device(dev);
1612 return PTR_ERR(data);
1614 speed = has_16bit_fans(data) ?
1615 FAN16_FROM_REG(data->fan[nr][index]) :
1616 FAN_FROM_REG(data->fan[nr][index],
1617 DIV_FROM_REG(data->fan_div[nr]));
1618 return sprintf(buf, "%d\n", speed);
1621 static ssize_t show_fan_div(struct device *dev, struct device_attribute *attr,
1624 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1625 struct it87_data *data = it87_update_device(dev);
1626 int nr = sensor_attr->index;
1629 return PTR_ERR(data);
1631 return sprintf(buf, "%lu\n", DIV_FROM_REG(data->fan_div[nr]));
1634 static ssize_t show_pwm_enable(struct device *dev,
1635 struct device_attribute *attr, char *buf)
1637 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1638 struct it87_data *data = it87_update_device(dev);
1639 int nr = sensor_attr->index;
1642 return PTR_ERR(data);
1644 return sprintf(buf, "%d\n", pwm_mode(data, nr));
1647 static ssize_t show_pwm(struct device *dev, struct device_attribute *attr,
1650 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1651 struct it87_data *data = it87_update_device(dev);
1652 int nr = sensor_attr->index;
1655 return PTR_ERR(data);
1657 return sprintf(buf, "%d\n",
1658 pwm_from_reg(data, data->pwm_duty[nr]));
1661 static ssize_t show_pwm_freq(struct device *dev, struct device_attribute *attr,
1664 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1665 struct it87_data *data = it87_update_device(dev);
1666 int nr = sensor_attr->index;
1671 return PTR_ERR(data);
1673 if (has_pwm_freq2(data) && nr == 1)
1674 index = (data->extra >> 4) & 0x07;
1676 index = (data->fan_ctl >> 4) & 0x07;
1678 freq = pwm_freq[index] / (has_newer_autopwm(data) ? 256 : 128);
1680 return sprintf(buf, "%u\n", freq);
1683 static ssize_t set_fan(struct device *dev, struct device_attribute *attr,
1684 const char *buf, size_t count)
1686 struct sensor_device_attribute_2 *sattr = to_sensor_dev_attr_2(attr);
1688 int index = sattr->index;
1690 struct it87_data *data = dev_get_drvdata(dev);
1695 if (kstrtol(buf, 10, &val) < 0)
1698 err = it87_lock(data);
1702 if (has_16bit_fans(data)) {
1703 data->fan[nr][index] = FAN16_TO_REG(val);
1704 data->write(data, data->REG_FAN_MIN[nr],
1705 data->fan[nr][index] & 0xff);
1706 data->write(data, data->REG_FANX_MIN[nr],
1707 data->fan[nr][index] >> 8);
1709 reg = data->read(data, IT87_REG_FAN_DIV);
1712 data->fan_div[nr] = reg & 0x07;
1715 data->fan_div[nr] = (reg >> 3) & 0x07;
1718 data->fan_div[nr] = (reg & 0x40) ? 3 : 1;
1721 data->fan[nr][index] =
1722 FAN_TO_REG(val, DIV_FROM_REG(data->fan_div[nr]));
1723 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][index]);
1729 static ssize_t set_fan_div(struct device *dev, struct device_attribute *attr,
1730 const char *buf, size_t count)
1732 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1733 struct it87_data *data = dev_get_drvdata(dev);
1734 int nr = sensor_attr->index;
1739 if (kstrtoul(buf, 10, &val) < 0)
1742 err = it87_lock(data);
1746 old = data->read(data, IT87_REG_FAN_DIV);
1748 /* Save fan min limit */
1749 min = FAN_FROM_REG(data->fan[nr][1], DIV_FROM_REG(data->fan_div[nr]));
1754 data->fan_div[nr] = DIV_TO_REG(val);
1758 data->fan_div[nr] = 1;
1760 data->fan_div[nr] = 3;
1763 val |= (data->fan_div[0] & 0x07);
1764 val |= (data->fan_div[1] & 0x07) << 3;
1765 if (data->fan_div[2] == 3)
1767 data->write(data, IT87_REG_FAN_DIV, val);
1769 /* Restore fan min limit */
1770 data->fan[nr][1] = FAN_TO_REG(min, DIV_FROM_REG(data->fan_div[nr]));
1771 data->write(data, data->REG_FAN_MIN[nr], data->fan[nr][1]);
1776 /* Returns 0 if OK, -EINVAL otherwise */
1777 static int check_trip_points(struct device *dev, int nr)
1779 const struct it87_data *data = dev_get_drvdata(dev);
1782 if (has_old_autopwm(data)) {
1783 for (i = 0; i < 3; i++) {
1784 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1787 for (i = 0; i < 2; i++) {
1788 if (data->auto_pwm[nr][i] > data->auto_pwm[nr][i + 1])
1791 } else if (has_newer_autopwm(data)) {
1792 for (i = 1; i < 3; i++) {
1793 if (data->auto_temp[nr][i] > data->auto_temp[nr][i + 1])
1800 "Inconsistent trip points, not switching to automatic mode\n");
1801 dev_err(dev, "Adjust the trip points and try again\n");
1806 static ssize_t set_pwm_enable(struct device *dev, struct device_attribute *attr,
1807 const char *buf, size_t count)
1809 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1810 struct it87_data *data = dev_get_drvdata(dev);
1811 int nr = sensor_attr->index;
1815 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 2)
1818 /* Check trip points before switching to automatic mode */
1820 if (check_trip_points(dev, nr) < 0)
1824 err = it87_lock(data);
1828 it87_update_pwm_ctrl(data, nr);
1831 if (nr < 3 && has_fanctl_onoff(data)) {
1833 /* make sure the fan is on when in on/off mode */
1834 tmp = data->read(data, IT87_REG_FAN_CTL);
1835 data->write(data, IT87_REG_FAN_CTL, tmp | BIT(nr));
1836 /* set on/off mode */
1837 data->fan_main_ctrl &= ~BIT(nr);
1838 data->write(data, IT87_REG_FAN_MAIN_CTRL,
1839 data->fan_main_ctrl);
1843 /* No on/off mode, set maximum pwm value */
1844 data->pwm_duty[nr] = pwm_to_reg(data, 0xff);
1845 data->write(data, IT87_REG_PWM_DUTY[nr],
1846 data->pwm_duty[nr]);
1847 /* and set manual mode */
1848 if (has_newer_autopwm(data)) {
1849 ctrl = temp_map_to_reg(data, nr,
1850 data->pwm_temp_map[nr]);
1853 ctrl = data->pwm_duty[nr];
1855 data->pwm_ctrl[nr] = ctrl;
1856 data->write(data, data->REG_PWM[nr], ctrl);
1861 if (has_newer_autopwm(data)) {
1862 ctrl = temp_map_to_reg(data, nr,
1863 data->pwm_temp_map[nr]);
1869 ctrl = (val == 1 ? data->pwm_duty[nr] : 0x80);
1871 data->pwm_ctrl[nr] = ctrl;
1872 data->write(data, data->REG_PWM[nr], ctrl);
1874 if (has_fanctl_onoff(data) && nr < 3) {
1875 /* set SmartGuardian mode */
1876 data->fan_main_ctrl |= BIT(nr);
1877 data->write(data, IT87_REG_FAN_MAIN_CTRL,
1878 data->fan_main_ctrl);
1885 static ssize_t set_pwm(struct device *dev, struct device_attribute *attr,
1886 const char *buf, size_t count)
1888 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1889 struct it87_data *data = dev_get_drvdata(dev);
1890 int nr = sensor_attr->index;
1894 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
1897 err = it87_lock(data);
1901 it87_update_pwm_ctrl(data, nr);
1902 if (has_newer_autopwm(data)) {
1904 * If we are in automatic mode, the PWM duty cycle register
1905 * is read-only so we can't write the value.
1907 if (data->pwm_ctrl[nr] & 0x80) {
1911 data->pwm_duty[nr] = pwm_to_reg(data, val);
1912 data->write(data, IT87_REG_PWM_DUTY[nr],
1913 data->pwm_duty[nr]);
1915 data->pwm_duty[nr] = pwm_to_reg(data, val);
1917 * If we are in manual mode, write the duty cycle immediately;
1918 * otherwise, just store it for later use.
1920 if (!(data->pwm_ctrl[nr] & 0x80)) {
1921 data->pwm_ctrl[nr] = data->pwm_duty[nr];
1922 data->write(data, data->REG_PWM[nr],
1923 data->pwm_ctrl[nr]);
1931 static ssize_t set_pwm_freq(struct device *dev, struct device_attribute *attr,
1932 const char *buf, size_t count)
1934 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1935 struct it87_data *data = dev_get_drvdata(dev);
1936 int nr = sensor_attr->index;
1941 if (kstrtoul(buf, 10, &val) < 0)
1944 val = clamp_val(val, 0, 1000000);
1945 val *= has_newer_autopwm(data) ? 256 : 128;
1947 /* Search for the nearest available frequency */
1948 for (i = 0; i < 7; i++) {
1949 if (val > (pwm_freq[i] + pwm_freq[i + 1]) / 2)
1953 err = it87_lock(data);
1958 data->fan_ctl = data->read(data, IT87_REG_FAN_CTL) & 0x8f;
1959 data->fan_ctl |= i << 4;
1960 data->write(data, IT87_REG_FAN_CTL, data->fan_ctl);
1962 data->extra = data->read(data, IT87_REG_TEMP_EXTRA) & 0x8f;
1963 data->extra |= i << 4;
1964 data->write(data, IT87_REG_TEMP_EXTRA, data->extra);
1970 static ssize_t show_pwm_temp_map(struct device *dev,
1971 struct device_attribute *attr, char *buf)
1973 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1974 struct it87_data *data = it87_update_device(dev);
1975 int nr = sensor_attr->index;
1978 return PTR_ERR(data);
1980 return sprintf(buf, "%d\n", data->pwm_temp_map[nr] + 1);
1983 static ssize_t set_pwm_temp_map(struct device *dev,
1984 struct device_attribute *attr, const char *buf,
1987 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
1988 struct it87_data *data = dev_get_drvdata(dev);
1989 int nr = sensor_attr->index;
1994 if (kstrtoul(buf, 10, &val) < 0)
1997 if (!val || val > data->pwm_num_temp_map)
2002 err = it87_lock(data);
2006 it87_update_pwm_ctrl(data, nr);
2007 data->pwm_temp_map[nr] = map;
2009 * If we are in automatic mode, write the temp mapping immediately;
2010 * otherwise, just store it for later use.
2012 if (data->pwm_ctrl[nr] & 0x80) {
2013 data->pwm_ctrl[nr] = temp_map_to_reg(data, nr, map);
2014 data->write(data, data->REG_PWM[nr], data->pwm_ctrl[nr]);
2020 static ssize_t show_auto_pwm(struct device *dev, struct device_attribute *attr,
2023 struct it87_data *data = it87_update_device(dev);
2024 struct sensor_device_attribute_2 *sensor_attr =
2025 to_sensor_dev_attr_2(attr);
2026 int nr = sensor_attr->nr;
2027 int point = sensor_attr->index;
2030 return PTR_ERR(data);
2032 return sprintf(buf, "%d\n",
2033 pwm_from_reg(data, data->auto_pwm[nr][point]));
2036 static ssize_t set_auto_pwm(struct device *dev, struct device_attribute *attr,
2037 const char *buf, size_t count)
2039 struct it87_data *data = dev_get_drvdata(dev);
2040 struct sensor_device_attribute_2 *sensor_attr =
2041 to_sensor_dev_attr_2(attr);
2042 int nr = sensor_attr->nr;
2043 int point = sensor_attr->index;
2048 if (kstrtol(buf, 10, &val) < 0 || val < 0 || val > 255)
2051 err = it87_lock(data);
2055 data->auto_pwm[nr][point] = pwm_to_reg(data, val);
2056 if (has_newer_autopwm(data))
2057 regaddr = IT87_REG_AUTO_TEMP(nr, 3);
2059 regaddr = IT87_REG_AUTO_PWM(nr, point);
2060 data->write(data, regaddr, data->auto_pwm[nr][point]);
2065 static ssize_t show_auto_pwm_slope(struct device *dev,
2066 struct device_attribute *attr, char *buf)
2068 struct it87_data *data = it87_update_device(dev);
2069 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2070 int nr = sensor_attr->index;
2073 return PTR_ERR(data);
2075 return sprintf(buf, "%d\n", data->auto_pwm[nr][1] & 0x7f);
2078 static ssize_t set_auto_pwm_slope(struct device *dev,
2079 struct device_attribute *attr,
2080 const char *buf, size_t count)
2082 struct it87_data *data = dev_get_drvdata(dev);
2083 struct sensor_device_attribute *sensor_attr = to_sensor_dev_attr(attr);
2084 int nr = sensor_attr->index;
2088 if (kstrtoul(buf, 10, &val) < 0 || val > 127)
2091 err = it87_lock(data);
2095 data->auto_pwm[nr][1] = (data->auto_pwm[nr][1] & 0x80) | val;
2096 data->write(data, IT87_REG_AUTO_TEMP(nr, 4), data->auto_pwm[nr][1]);
2101 static ssize_t show_auto_temp(struct device *dev, struct device_attribute *attr,
2104 struct it87_data *data = it87_update_device(dev);
2105 struct sensor_device_attribute_2 *sensor_attr =
2106 to_sensor_dev_attr_2(attr);
2107 int nr = sensor_attr->nr;
2108 int point = sensor_attr->index;
2112 return PTR_ERR(data);
2114 if (has_old_autopwm(data) || point)
2115 reg = data->auto_temp[nr][point];
2117 reg = data->auto_temp[nr][1] - (data->auto_temp[nr][0] & 0x1f);
2119 return sprintf(buf, "%d\n", TEMP_FROM_REG(reg));
2122 static ssize_t set_auto_temp(struct device *dev, struct device_attribute *attr,
2123 const char *buf, size_t count)
2125 struct it87_data *data = dev_get_drvdata(dev);
2126 struct sensor_device_attribute_2 *sensor_attr =
2127 to_sensor_dev_attr_2(attr);
2128 int nr = sensor_attr->nr;
2129 int point = sensor_attr->index;
2134 if (kstrtol(buf, 10, &val) < 0 || val < -128000 || val > 127000)
2137 err = it87_lock(data);
2141 if (has_newer_autopwm(data) && !point) {
2142 reg = data->auto_temp[nr][1] - TEMP_TO_REG(val);
2143 reg = clamp_val(reg, 0, 0x1f) | (data->auto_temp[nr][0] & 0xe0);
2144 data->auto_temp[nr][0] = reg;
2145 data->write(data, IT87_REG_AUTO_TEMP(nr, 5), reg);
2147 reg = TEMP_TO_REG(val);
2148 data->auto_temp[nr][point] = reg;
2149 if (has_newer_autopwm(data))
2151 data->write(data, IT87_REG_AUTO_TEMP(nr, point), reg);
2157 static SENSOR_DEVICE_ATTR_2(fan1_input, 0444, show_fan, NULL, 0, 0);
2158 static SENSOR_DEVICE_ATTR_2(fan1_min, 0644, show_fan, set_fan, 0, 1);
2159 static SENSOR_DEVICE_ATTR(fan1_div, 0644, show_fan_div, set_fan_div, 0);
2161 static SENSOR_DEVICE_ATTR_2(fan2_input, 0444, show_fan, NULL, 1, 0);
2162 static SENSOR_DEVICE_ATTR_2(fan2_min, 0644, show_fan, set_fan, 1, 1);
2163 static SENSOR_DEVICE_ATTR(fan2_div, 0644, show_fan_div, set_fan_div, 1);
2165 static SENSOR_DEVICE_ATTR_2(fan3_input, 0444, show_fan, NULL, 2, 0);
2166 static SENSOR_DEVICE_ATTR_2(fan3_min, 0644, show_fan, set_fan, 2, 1);
2167 static SENSOR_DEVICE_ATTR(fan3_div, 0644, show_fan_div, set_fan_div, 2);
2169 static SENSOR_DEVICE_ATTR_2(fan4_input, 0444, show_fan, NULL, 3, 0);
2170 static SENSOR_DEVICE_ATTR_2(fan4_min, 0644, show_fan, set_fan, 3, 1);
2172 static SENSOR_DEVICE_ATTR_2(fan5_input, 0444, show_fan, NULL, 4, 0);
2173 static SENSOR_DEVICE_ATTR_2(fan5_min, 0644, show_fan, set_fan, 4, 1);
2175 static SENSOR_DEVICE_ATTR_2(fan6_input, 0444, show_fan, NULL, 5, 0);
2176 static SENSOR_DEVICE_ATTR_2(fan6_min, 0644, show_fan, set_fan, 5, 1);
2178 static SENSOR_DEVICE_ATTR(pwm1_enable, 0644,
2179 show_pwm_enable, set_pwm_enable, 0);
2180 static SENSOR_DEVICE_ATTR(pwm1, 0644, show_pwm, set_pwm, 0);
2181 static SENSOR_DEVICE_ATTR(pwm1_freq, 0644, show_pwm_freq, set_pwm_freq, 0);
2182 static SENSOR_DEVICE_ATTR(pwm1_auto_channels_temp, 0444,
2183 show_pwm_temp_map, set_pwm_temp_map, 0);
2184 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_pwm, 0644,
2185 show_auto_pwm, set_auto_pwm, 0, 0);
2186 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_pwm, 0644,
2187 show_auto_pwm, set_auto_pwm, 0, 1);
2188 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_pwm, 0644,
2189 show_auto_pwm, set_auto_pwm, 0, 2);
2190 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_pwm, 0444,
2191 show_auto_pwm, NULL, 0, 3);
2192 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp, 0644,
2193 show_auto_temp, set_auto_temp, 0, 1);
2194 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point1_temp_hyst, 0644,
2195 show_auto_temp, set_auto_temp, 0, 0);
2196 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point2_temp, 0644,
2197 show_auto_temp, set_auto_temp, 0, 2);
2198 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point3_temp, 0644,
2199 show_auto_temp, set_auto_temp, 0, 3);
2200 static SENSOR_DEVICE_ATTR_2(pwm1_auto_point4_temp, 0644,
2201 show_auto_temp, set_auto_temp, 0, 4);
2202 static SENSOR_DEVICE_ATTR_2(pwm1_auto_start, 0644,
2203 show_auto_pwm, set_auto_pwm, 0, 0);
2204 static SENSOR_DEVICE_ATTR(pwm1_auto_slope, 0644,
2205 show_auto_pwm_slope, set_auto_pwm_slope, 0);
2207 static SENSOR_DEVICE_ATTR(pwm2_enable, 0644,
2208 show_pwm_enable, set_pwm_enable, 1);
2209 static SENSOR_DEVICE_ATTR(pwm2, 0644, show_pwm, set_pwm, 1);
2210 static SENSOR_DEVICE_ATTR(pwm2_freq, 0444, show_pwm_freq, set_pwm_freq, 1);
2211 static SENSOR_DEVICE_ATTR(pwm2_auto_channels_temp, 0444,
2212 show_pwm_temp_map, set_pwm_temp_map, 1);
2213 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_pwm, 0644,
2214 show_auto_pwm, set_auto_pwm, 1, 0);
2215 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_pwm, 0644,
2216 show_auto_pwm, set_auto_pwm, 1, 1);
2217 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_pwm, 0644,
2218 show_auto_pwm, set_auto_pwm, 1, 2);
2219 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_pwm, 0444,
2220 show_auto_pwm, NULL, 1, 3);
2221 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp, 0644,
2222 show_auto_temp, set_auto_temp, 1, 1);
2223 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point1_temp_hyst, 0644,
2224 show_auto_temp, set_auto_temp, 1, 0);
2225 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point2_temp, 0644,
2226 show_auto_temp, set_auto_temp, 1, 2);
2227 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point3_temp, 0644,
2228 show_auto_temp, set_auto_temp, 1, 3);
2229 static SENSOR_DEVICE_ATTR_2(pwm2_auto_point4_temp, 0644,
2230 show_auto_temp, set_auto_temp, 1, 4);
2231 static SENSOR_DEVICE_ATTR_2(pwm2_auto_start, 0644,
2232 show_auto_pwm, set_auto_pwm, 1, 0);
2233 static SENSOR_DEVICE_ATTR(pwm2_auto_slope, 0644,
2234 show_auto_pwm_slope, set_auto_pwm_slope, 1);
2236 static SENSOR_DEVICE_ATTR(pwm3_enable, 0644,
2237 show_pwm_enable, set_pwm_enable, 2);
2238 static SENSOR_DEVICE_ATTR(pwm3, 0644, show_pwm, set_pwm, 2);
2239 static SENSOR_DEVICE_ATTR(pwm3_freq, 0444, show_pwm_freq, NULL, 2);
2240 static SENSOR_DEVICE_ATTR(pwm3_auto_channels_temp, 0444,
2241 show_pwm_temp_map, set_pwm_temp_map, 2);
2242 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_pwm, 0644,
2243 show_auto_pwm, set_auto_pwm, 2, 0);
2244 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_pwm, 0644,
2245 show_auto_pwm, set_auto_pwm, 2, 1);
2246 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_pwm, 0644,
2247 show_auto_pwm, set_auto_pwm, 2, 2);
2248 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_pwm, 0444,
2249 show_auto_pwm, NULL, 2, 3);
2250 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp, 0644,
2251 show_auto_temp, set_auto_temp, 2, 1);
2252 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point1_temp_hyst, 0644,
2253 show_auto_temp, set_auto_temp, 2, 0);
2254 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point2_temp, 0644,
2255 show_auto_temp, set_auto_temp, 2, 2);
2256 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point3_temp, 0644,
2257 show_auto_temp, set_auto_temp, 2, 3);
2258 static SENSOR_DEVICE_ATTR_2(pwm3_auto_point4_temp, 0644,
2259 show_auto_temp, set_auto_temp, 2, 4);
2260 static SENSOR_DEVICE_ATTR_2(pwm3_auto_start, 0644,
2261 show_auto_pwm, set_auto_pwm, 2, 0);
2262 static SENSOR_DEVICE_ATTR(pwm3_auto_slope, 0644,
2263 show_auto_pwm_slope, set_auto_pwm_slope, 2);
2265 static SENSOR_DEVICE_ATTR(pwm4_enable, 0644,
2266 show_pwm_enable, set_pwm_enable, 3);
2267 static SENSOR_DEVICE_ATTR(pwm4, 0644, show_pwm, set_pwm, 3);
2268 static SENSOR_DEVICE_ATTR(pwm4_freq, 0444, show_pwm_freq, NULL, 3);
2269 static SENSOR_DEVICE_ATTR(pwm4_auto_channels_temp, 0444,
2270 show_pwm_temp_map, set_pwm_temp_map, 3);
2271 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp, 0644,
2272 show_auto_temp, set_auto_temp, 2, 1);
2273 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point1_temp_hyst, 0644,
2274 show_auto_temp, set_auto_temp, 2, 0);
2275 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point2_temp, 0644,
2276 show_auto_temp, set_auto_temp, 2, 2);
2277 static SENSOR_DEVICE_ATTR_2(pwm4_auto_point3_temp, 0644,
2278 show_auto_temp, set_auto_temp, 2, 3);
2279 static SENSOR_DEVICE_ATTR_2(pwm4_auto_start, 0644,
2280 show_auto_pwm, set_auto_pwm, 3, 0);
2281 static SENSOR_DEVICE_ATTR(pwm4_auto_slope, 0644,
2282 show_auto_pwm_slope, set_auto_pwm_slope, 3);
2284 static SENSOR_DEVICE_ATTR(pwm5_enable, 0644,
2285 show_pwm_enable, set_pwm_enable, 4);
2286 static SENSOR_DEVICE_ATTR(pwm5, 0644, show_pwm, set_pwm, 4);
2287 static SENSOR_DEVICE_ATTR(pwm5_freq, 0444, show_pwm_freq, NULL, 4);
2288 static SENSOR_DEVICE_ATTR(pwm5_auto_channels_temp, 0444,
2289 show_pwm_temp_map, set_pwm_temp_map, 4);
2290 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp, 0644,
2291 show_auto_temp, set_auto_temp, 2, 1);
2292 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point1_temp_hyst, 0644,
2293 show_auto_temp, set_auto_temp, 2, 0);
2294 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point2_temp, 0644,
2295 show_auto_temp, set_auto_temp, 2, 2);
2296 static SENSOR_DEVICE_ATTR_2(pwm5_auto_point3_temp, 0644,
2297 show_auto_temp, set_auto_temp, 2, 3);
2298 static SENSOR_DEVICE_ATTR_2(pwm5_auto_start, 0644,
2299 show_auto_pwm, set_auto_pwm, 4, 0);
2300 static SENSOR_DEVICE_ATTR(pwm5_auto_slope, 0644,
2301 show_auto_pwm_slope, set_auto_pwm_slope, 4);
2303 static SENSOR_DEVICE_ATTR(pwm6_enable, 0644,
2304 show_pwm_enable, set_pwm_enable, 5);
2305 static SENSOR_DEVICE_ATTR(pwm6, 0644, show_pwm, set_pwm, 5);
2306 static SENSOR_DEVICE_ATTR(pwm6_freq, 0444, show_pwm_freq, NULL, 5);
2307 static SENSOR_DEVICE_ATTR(pwm6_auto_channels_temp, 0444,
2308 show_pwm_temp_map, set_pwm_temp_map, 5);
2309 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp, 0644,
2310 show_auto_temp, set_auto_temp, 2, 1);
2311 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point1_temp_hyst, 0644,
2312 show_auto_temp, set_auto_temp, 2, 0);
2313 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point2_temp, 0644,
2314 show_auto_temp, set_auto_temp, 2, 2);
2315 static SENSOR_DEVICE_ATTR_2(pwm6_auto_point3_temp, 0644,
2316 show_auto_temp, set_auto_temp, 2, 3);
2317 static SENSOR_DEVICE_ATTR_2(pwm6_auto_start, 0644,
2318 show_auto_pwm, set_auto_pwm, 5, 0);
2319 static SENSOR_DEVICE_ATTR(pwm6_auto_slope, 0644,
2320 show_auto_pwm_slope, set_auto_pwm_slope, 5);
2323 static ssize_t show_alarms(struct device *dev, struct device_attribute *attr,
2326 struct it87_data *data = it87_update_device(dev);
2329 return PTR_ERR(data);
2331 return sprintf(buf, "%u\n", data->alarms);
2333 static DEVICE_ATTR(alarms, 0444, show_alarms, NULL);
2335 static ssize_t show_alarm(struct device *dev, struct device_attribute *attr,
2338 struct it87_data *data = it87_update_device(dev);
2339 int bitnr = to_sensor_dev_attr(attr)->index;
2342 return PTR_ERR(data);
2344 return sprintf(buf, "%u\n", (data->alarms >> bitnr) & 1);
2347 static ssize_t clear_intrusion(struct device *dev,
2348 struct device_attribute *attr, const char *buf,
2351 struct it87_data *data = dev_get_drvdata(dev);
2355 if (kstrtol(buf, 10, &val) < 0 || val != 0)
2358 err = it87_lock(data);
2362 config = data->read(data, IT87_REG_CONFIG);
2364 data->write(data, IT87_REG_CONFIG, config);
2365 /* Invalidate cache to force re-read */
2371 static SENSOR_DEVICE_ATTR(in0_alarm, 0444, show_alarm, NULL, 8);
2372 static SENSOR_DEVICE_ATTR(in1_alarm, 0444, show_alarm, NULL, 9);
2373 static SENSOR_DEVICE_ATTR(in2_alarm, 0444, show_alarm, NULL, 10);
2374 static SENSOR_DEVICE_ATTR(in3_alarm, 0444, show_alarm, NULL, 11);
2375 static SENSOR_DEVICE_ATTR(in4_alarm, 0444, show_alarm, NULL, 12);
2376 static SENSOR_DEVICE_ATTR(in5_alarm, 0444, show_alarm, NULL, 13);
2377 static SENSOR_DEVICE_ATTR(in6_alarm, 0444, show_alarm, NULL, 14);
2378 static SENSOR_DEVICE_ATTR(in7_alarm, 0444, show_alarm, NULL, 15);
2379 static SENSOR_DEVICE_ATTR(fan1_alarm, 0444, show_alarm, NULL, 0);
2380 static SENSOR_DEVICE_ATTR(fan2_alarm, 0444, show_alarm, NULL, 1);
2381 static SENSOR_DEVICE_ATTR(fan3_alarm, 0444, show_alarm, NULL, 2);
2382 static SENSOR_DEVICE_ATTR(fan4_alarm, 0444, show_alarm, NULL, 3);
2383 static SENSOR_DEVICE_ATTR(fan5_alarm, 0444, show_alarm, NULL, 6);
2384 static SENSOR_DEVICE_ATTR(fan6_alarm, 0444, show_alarm, NULL, 7);
2385 static SENSOR_DEVICE_ATTR(temp1_alarm, 0444, show_alarm, NULL, 16);
2386 static SENSOR_DEVICE_ATTR(temp2_alarm, 0444, show_alarm, NULL, 17);
2387 static SENSOR_DEVICE_ATTR(temp3_alarm, 0444, show_alarm, NULL, 18);
2388 static SENSOR_DEVICE_ATTR(temp4_alarm, 0444, show_alarm, NULL, 19);
2389 static SENSOR_DEVICE_ATTR(temp5_alarm, 0444, show_alarm, NULL, 20);
2390 static SENSOR_DEVICE_ATTR(temp6_alarm, 0444, show_alarm, NULL, 21);
2391 static SENSOR_DEVICE_ATTR(intrusion0_alarm, 0644,
2392 show_alarm, clear_intrusion, 4);
2394 static ssize_t show_beep(struct device *dev, struct device_attribute *attr,
2397 struct it87_data *data = it87_update_device(dev);
2398 int bitnr = to_sensor_dev_attr(attr)->index;
2401 return PTR_ERR(data);
2403 return sprintf(buf, "%u\n", (data->beeps >> bitnr) & 1);
2406 static ssize_t set_beep(struct device *dev, struct device_attribute *attr,
2407 const char *buf, size_t count)
2409 int bitnr = to_sensor_dev_attr(attr)->index;
2410 struct it87_data *data = dev_get_drvdata(dev);
2414 if (kstrtol(buf, 10, &val) < 0 || (val != 0 && val != 1))
2417 err = it87_lock(data);
2421 data->beeps = data->read(data, IT87_REG_BEEP_ENABLE);
2423 data->beeps |= BIT(bitnr);
2425 data->beeps &= ~BIT(bitnr);
2426 data->write(data, IT87_REG_BEEP_ENABLE, data->beeps);
2431 static SENSOR_DEVICE_ATTR(in0_beep, 0644,
2432 show_beep, set_beep, 1);
2433 static SENSOR_DEVICE_ATTR(in1_beep, 0444, show_beep, NULL, 1);
2434 static SENSOR_DEVICE_ATTR(in2_beep, 0444, show_beep, NULL, 1);
2435 static SENSOR_DEVICE_ATTR(in3_beep, 0444, show_beep, NULL, 1);
2436 static SENSOR_DEVICE_ATTR(in4_beep, 0444, show_beep, NULL, 1);
2437 static SENSOR_DEVICE_ATTR(in5_beep, 0444, show_beep, NULL, 1);
2438 static SENSOR_DEVICE_ATTR(in6_beep, 0444, show_beep, NULL, 1);
2439 static SENSOR_DEVICE_ATTR(in7_beep, 0444, show_beep, NULL, 1);
2440 /* fanX_beep writability is set later */
2441 static SENSOR_DEVICE_ATTR(fan1_beep, 0444, show_beep, set_beep, 0);
2442 static SENSOR_DEVICE_ATTR(fan2_beep, 0444, show_beep, set_beep, 0);
2443 static SENSOR_DEVICE_ATTR(fan3_beep, 0444, show_beep, set_beep, 0);
2444 static SENSOR_DEVICE_ATTR(fan4_beep, 0444, show_beep, set_beep, 0);
2445 static SENSOR_DEVICE_ATTR(fan5_beep, 0444, show_beep, set_beep, 0);
2446 static SENSOR_DEVICE_ATTR(fan6_beep, 0444, show_beep, set_beep, 0);
2447 static SENSOR_DEVICE_ATTR(temp1_beep, 0644,
2448 show_beep, set_beep, 2);
2449 static SENSOR_DEVICE_ATTR(temp2_beep, 0444, show_beep, NULL, 2);
2450 static SENSOR_DEVICE_ATTR(temp3_beep, 0444, show_beep, NULL, 2);
2451 static SENSOR_DEVICE_ATTR(temp4_beep, 0444, show_beep, NULL, 2);
2452 static SENSOR_DEVICE_ATTR(temp5_beep, 0444, show_beep, NULL, 2);
2453 static SENSOR_DEVICE_ATTR(temp6_beep, 0444, show_beep, NULL, 2);
2455 static ssize_t show_vrm_reg(struct device *dev, struct device_attribute *attr,
2458 struct it87_data *data = dev_get_drvdata(dev);
2460 return sprintf(buf, "%u\n", data->vrm);
2463 static ssize_t store_vrm_reg(struct device *dev, struct device_attribute *attr,
2464 const char *buf, size_t count)
2466 struct it87_data *data = dev_get_drvdata(dev);
2469 if (kstrtoul(buf, 10, &val) < 0)
2476 static DEVICE_ATTR(vrm, 0644, show_vrm_reg, store_vrm_reg);
2478 static ssize_t show_vid_reg(struct device *dev, struct device_attribute *attr,
2481 struct it87_data *data = it87_update_device(dev);
2484 return PTR_ERR(data);
2486 return sprintf(buf, "%ld\n", (long)vid_from_reg(data->vid, data->vrm));
2488 static DEVICE_ATTR(cpu0_vid, 0444, show_vid_reg, NULL);
2490 static ssize_t show_label(struct device *dev, struct device_attribute *attr,
2493 static const char * const labels[] = {
2499 static const char * const labels_it8721[] = {
2505 struct it87_data *data = dev_get_drvdata(dev);
2506 int nr = to_sensor_dev_attr(attr)->index;
2509 if (has_vin3_5v(data) && nr == 0)
2511 else if (has_12mv_adc(data) || has_10_9mv_adc(data) ||
2513 label = labels_it8721[nr];
2517 return sprintf(buf, "%s\n", label);
2519 static SENSOR_DEVICE_ATTR(in3_label, 0444, show_label, NULL, 0);
2520 static SENSOR_DEVICE_ATTR(in7_label, 0444, show_label, NULL, 1);
2521 static SENSOR_DEVICE_ATTR(in8_label, 0444, show_label, NULL, 2);
2523 static SENSOR_DEVICE_ATTR(in9_label, 0444, show_label, NULL, 3);
2525 static umode_t it87_in_is_visible(struct kobject *kobj,
2526 struct attribute *attr, int index)
2528 struct device *dev = container_of(kobj, struct device, kobj);
2529 struct it87_data *data = dev_get_drvdata(dev);
2530 int i = index / 5; /* voltage index */
2531 int a = index % 5; /* attribute index */
2533 if (index >= 40) { /* in8 and higher only have input attributes */
2538 if (!(data->has_in & BIT(i)))
2541 if (a == 4 && !data->has_beep)
2547 static struct attribute *it87_attributes_in[] = {
2548 &sensor_dev_attr_in0_input.dev_attr.attr,
2549 &sensor_dev_attr_in0_min.dev_attr.attr,
2550 &sensor_dev_attr_in0_max.dev_attr.attr,
2551 &sensor_dev_attr_in0_alarm.dev_attr.attr,
2552 &sensor_dev_attr_in0_beep.dev_attr.attr, /* 4 */
2554 &sensor_dev_attr_in1_input.dev_attr.attr,
2555 &sensor_dev_attr_in1_min.dev_attr.attr,
2556 &sensor_dev_attr_in1_max.dev_attr.attr,
2557 &sensor_dev_attr_in1_alarm.dev_attr.attr,
2558 &sensor_dev_attr_in1_beep.dev_attr.attr, /* 9 */
2560 &sensor_dev_attr_in2_input.dev_attr.attr,
2561 &sensor_dev_attr_in2_min.dev_attr.attr,
2562 &sensor_dev_attr_in2_max.dev_attr.attr,
2563 &sensor_dev_attr_in2_alarm.dev_attr.attr,
2564 &sensor_dev_attr_in2_beep.dev_attr.attr, /* 14 */
2566 &sensor_dev_attr_in3_input.dev_attr.attr,
2567 &sensor_dev_attr_in3_min.dev_attr.attr,
2568 &sensor_dev_attr_in3_max.dev_attr.attr,
2569 &sensor_dev_attr_in3_alarm.dev_attr.attr,
2570 &sensor_dev_attr_in3_beep.dev_attr.attr, /* 19 */
2572 &sensor_dev_attr_in4_input.dev_attr.attr,
2573 &sensor_dev_attr_in4_min.dev_attr.attr,
2574 &sensor_dev_attr_in4_max.dev_attr.attr,
2575 &sensor_dev_attr_in4_alarm.dev_attr.attr,
2576 &sensor_dev_attr_in4_beep.dev_attr.attr, /* 24 */
2578 &sensor_dev_attr_in5_input.dev_attr.attr,
2579 &sensor_dev_attr_in5_min.dev_attr.attr,
2580 &sensor_dev_attr_in5_max.dev_attr.attr,
2581 &sensor_dev_attr_in5_alarm.dev_attr.attr,
2582 &sensor_dev_attr_in5_beep.dev_attr.attr, /* 29 */
2584 &sensor_dev_attr_in6_input.dev_attr.attr,
2585 &sensor_dev_attr_in6_min.dev_attr.attr,
2586 &sensor_dev_attr_in6_max.dev_attr.attr,
2587 &sensor_dev_attr_in6_alarm.dev_attr.attr,
2588 &sensor_dev_attr_in6_beep.dev_attr.attr, /* 34 */
2590 &sensor_dev_attr_in7_input.dev_attr.attr,
2591 &sensor_dev_attr_in7_min.dev_attr.attr,
2592 &sensor_dev_attr_in7_max.dev_attr.attr,
2593 &sensor_dev_attr_in7_alarm.dev_attr.attr,
2594 &sensor_dev_attr_in7_beep.dev_attr.attr, /* 39 */
2596 &sensor_dev_attr_in8_input.dev_attr.attr, /* 40 */
2597 &sensor_dev_attr_in9_input.dev_attr.attr, /* 41 */
2598 &sensor_dev_attr_in10_input.dev_attr.attr, /* 42 */
2599 &sensor_dev_attr_in11_input.dev_attr.attr, /* 43 */
2600 &sensor_dev_attr_in12_input.dev_attr.attr, /* 44 */
2604 static const struct attribute_group it87_group_in = {
2605 .attrs = it87_attributes_in,
2606 .is_visible = it87_in_is_visible,
2609 static umode_t it87_temp_is_visible(struct kobject *kobj,
2610 struct attribute *attr, int index)
2612 struct device *dev = container_of(kobj, struct device, kobj);
2613 struct it87_data *data = dev_get_drvdata(dev);
2614 int i = index / 7; /* temperature index */
2615 int a = index % 7; /* attribute index */
2617 if (!(data->has_temp & BIT(i)))
2620 if (a && i >= data->num_temp_limit)
2624 int type = get_temp_type(data, i);
2628 if (has_bank_sel(data))
2633 if (a == 5 && i >= data->num_temp_offset)
2636 if (a == 6 && !data->has_beep)
2642 static struct attribute *it87_attributes_temp[] = {
2643 &sensor_dev_attr_temp1_input.dev_attr.attr,
2644 &sensor_dev_attr_temp1_max.dev_attr.attr,
2645 &sensor_dev_attr_temp1_min.dev_attr.attr,
2646 &sensor_dev_attr_temp1_type.dev_attr.attr, /* 3 */
2647 &sensor_dev_attr_temp1_alarm.dev_attr.attr,
2648 &sensor_dev_attr_temp1_offset.dev_attr.attr, /* 5 */
2649 &sensor_dev_attr_temp1_beep.dev_attr.attr, /* 6 */
2651 &sensor_dev_attr_temp2_input.dev_attr.attr, /* 7 */
2652 &sensor_dev_attr_temp2_max.dev_attr.attr,
2653 &sensor_dev_attr_temp2_min.dev_attr.attr,
2654 &sensor_dev_attr_temp2_type.dev_attr.attr,
2655 &sensor_dev_attr_temp2_alarm.dev_attr.attr,
2656 &sensor_dev_attr_temp2_offset.dev_attr.attr,
2657 &sensor_dev_attr_temp2_beep.dev_attr.attr,
2659 &sensor_dev_attr_temp3_input.dev_attr.attr, /* 14 */
2660 &sensor_dev_attr_temp3_max.dev_attr.attr,
2661 &sensor_dev_attr_temp3_min.dev_attr.attr,
2662 &sensor_dev_attr_temp3_type.dev_attr.attr,
2663 &sensor_dev_attr_temp3_alarm.dev_attr.attr,
2664 &sensor_dev_attr_temp3_offset.dev_attr.attr,
2665 &sensor_dev_attr_temp3_beep.dev_attr.attr,
2667 &sensor_dev_attr_temp4_input.dev_attr.attr, /* 21 */
2668 &sensor_dev_attr_temp4_max.dev_attr.attr,
2669 &sensor_dev_attr_temp4_min.dev_attr.attr,
2670 &sensor_dev_attr_temp4_type.dev_attr.attr,
2671 &sensor_dev_attr_temp4_alarm.dev_attr.attr,
2672 &sensor_dev_attr_temp4_offset.dev_attr.attr,
2673 &sensor_dev_attr_temp4_beep.dev_attr.attr,
2675 &sensor_dev_attr_temp5_input.dev_attr.attr,
2676 &sensor_dev_attr_temp5_max.dev_attr.attr,
2677 &sensor_dev_attr_temp5_min.dev_attr.attr,
2678 &sensor_dev_attr_temp5_type.dev_attr.attr,
2679 &sensor_dev_attr_temp5_alarm.dev_attr.attr,
2680 &sensor_dev_attr_temp5_offset.dev_attr.attr,
2681 &sensor_dev_attr_temp5_beep.dev_attr.attr,
2683 &sensor_dev_attr_temp6_input.dev_attr.attr,
2684 &sensor_dev_attr_temp6_max.dev_attr.attr,
2685 &sensor_dev_attr_temp6_min.dev_attr.attr,
2686 &sensor_dev_attr_temp6_type.dev_attr.attr,
2687 &sensor_dev_attr_temp6_alarm.dev_attr.attr,
2688 &sensor_dev_attr_temp6_offset.dev_attr.attr,
2689 &sensor_dev_attr_temp6_beep.dev_attr.attr,
2693 static const struct attribute_group it87_group_temp = {
2694 .attrs = it87_attributes_temp,
2695 .is_visible = it87_temp_is_visible,
2698 static umode_t it87_is_visible(struct kobject *kobj,
2699 struct attribute *attr, int index)
2701 struct device *dev = container_of(kobj, struct device, kobj);
2702 struct it87_data *data = dev_get_drvdata(dev);
2704 if ((index == 2 || index == 3) && !data->has_vid)
2707 if (index > 3 && !(data->in_internal & BIT(index - 4)))
2713 static struct attribute *it87_attributes[] = {
2714 &dev_attr_alarms.attr,
2715 &sensor_dev_attr_intrusion0_alarm.dev_attr.attr,
2716 &dev_attr_vrm.attr, /* 2 */
2717 &dev_attr_cpu0_vid.attr, /* 3 */
2718 &sensor_dev_attr_in3_label.dev_attr.attr, /* 4 .. 7 */
2719 &sensor_dev_attr_in7_label.dev_attr.attr,
2720 &sensor_dev_attr_in8_label.dev_attr.attr,
2721 &sensor_dev_attr_in9_label.dev_attr.attr,
2725 static const struct attribute_group it87_group = {
2726 .attrs = it87_attributes,
2727 .is_visible = it87_is_visible,
2730 static umode_t it87_fan_is_visible(struct kobject *kobj,
2731 struct attribute *attr, int index)
2733 struct device *dev = container_of(kobj, struct device, kobj);
2734 struct it87_data *data = dev_get_drvdata(dev);
2735 int i = index / 5; /* fan index */
2736 int a = index % 5; /* attribute index */
2738 if (index >= 15) { /* fan 4..6 don't have divisor attributes */
2739 i = (index - 15) / 4 + 3;
2740 a = (index - 15) % 4;
2743 if (!(data->has_fan & BIT(i)))
2746 if (a == 3) { /* beep */
2747 if (!data->has_beep)
2749 /* first fan beep attribute is writable */
2750 if (i == __ffs(data->has_fan))
2751 return attr->mode | 0200;
2754 if (a == 4 && has_16bit_fans(data)) /* divisor */
2760 static struct attribute *it87_attributes_fan[] = {
2761 &sensor_dev_attr_fan1_input.dev_attr.attr,
2762 &sensor_dev_attr_fan1_min.dev_attr.attr,
2763 &sensor_dev_attr_fan1_alarm.dev_attr.attr,
2764 &sensor_dev_attr_fan1_beep.dev_attr.attr, /* 3 */
2765 &sensor_dev_attr_fan1_div.dev_attr.attr, /* 4 */
2767 &sensor_dev_attr_fan2_input.dev_attr.attr,
2768 &sensor_dev_attr_fan2_min.dev_attr.attr,
2769 &sensor_dev_attr_fan2_alarm.dev_attr.attr,
2770 &sensor_dev_attr_fan2_beep.dev_attr.attr,
2771 &sensor_dev_attr_fan2_div.dev_attr.attr, /* 9 */
2773 &sensor_dev_attr_fan3_input.dev_attr.attr,
2774 &sensor_dev_attr_fan3_min.dev_attr.attr,
2775 &sensor_dev_attr_fan3_alarm.dev_attr.attr,
2776 &sensor_dev_attr_fan3_beep.dev_attr.attr,
2777 &sensor_dev_attr_fan3_div.dev_attr.attr, /* 14 */
2779 &sensor_dev_attr_fan4_input.dev_attr.attr, /* 15 */
2780 &sensor_dev_attr_fan4_min.dev_attr.attr,
2781 &sensor_dev_attr_fan4_alarm.dev_attr.attr,
2782 &sensor_dev_attr_fan4_beep.dev_attr.attr,
2784 &sensor_dev_attr_fan5_input.dev_attr.attr, /* 19 */
2785 &sensor_dev_attr_fan5_min.dev_attr.attr,
2786 &sensor_dev_attr_fan5_alarm.dev_attr.attr,
2787 &sensor_dev_attr_fan5_beep.dev_attr.attr,
2789 &sensor_dev_attr_fan6_input.dev_attr.attr, /* 23 */
2790 &sensor_dev_attr_fan6_min.dev_attr.attr,
2791 &sensor_dev_attr_fan6_alarm.dev_attr.attr,
2792 &sensor_dev_attr_fan6_beep.dev_attr.attr,
2796 static const struct attribute_group it87_group_fan = {
2797 .attrs = it87_attributes_fan,
2798 .is_visible = it87_fan_is_visible,
2801 static umode_t it87_pwm_is_visible(struct kobject *kobj,
2802 struct attribute *attr, int index)
2804 struct device *dev = container_of(kobj, struct device, kobj);
2805 struct it87_data *data = dev_get_drvdata(dev);
2806 int i = index / 4; /* pwm index */
2807 int a = index % 4; /* attribute index */
2809 if (!(data->has_pwm & BIT(i)))
2812 /* pwmX_auto_channels_temp is only writable if auto pwm is supported */
2813 if (a == 3 && (has_old_autopwm(data) || has_newer_autopwm(data)))
2814 return attr->mode | 0200;
2816 /* pwm2_freq is writable if there are two pwm frequency selects */
2817 if (has_pwm_freq2(data) && i == 1 && a == 2)
2818 return attr->mode | 0200;
2823 static struct attribute *it87_attributes_pwm[] = {
2824 &sensor_dev_attr_pwm1_enable.dev_attr.attr,
2825 &sensor_dev_attr_pwm1.dev_attr.attr,
2826 &sensor_dev_attr_pwm1_freq.dev_attr.attr,
2827 &sensor_dev_attr_pwm1_auto_channels_temp.dev_attr.attr,
2829 &sensor_dev_attr_pwm2_enable.dev_attr.attr,
2830 &sensor_dev_attr_pwm2.dev_attr.attr,
2831 &sensor_dev_attr_pwm2_freq.dev_attr.attr,
2832 &sensor_dev_attr_pwm2_auto_channels_temp.dev_attr.attr,
2834 &sensor_dev_attr_pwm3_enable.dev_attr.attr,
2835 &sensor_dev_attr_pwm3.dev_attr.attr,
2836 &sensor_dev_attr_pwm3_freq.dev_attr.attr,
2837 &sensor_dev_attr_pwm3_auto_channels_temp.dev_attr.attr,
2839 &sensor_dev_attr_pwm4_enable.dev_attr.attr,
2840 &sensor_dev_attr_pwm4.dev_attr.attr,
2841 &sensor_dev_attr_pwm4_freq.dev_attr.attr,
2842 &sensor_dev_attr_pwm4_auto_channels_temp.dev_attr.attr,
2844 &sensor_dev_attr_pwm5_enable.dev_attr.attr,
2845 &sensor_dev_attr_pwm5.dev_attr.attr,
2846 &sensor_dev_attr_pwm5_freq.dev_attr.attr,
2847 &sensor_dev_attr_pwm5_auto_channels_temp.dev_attr.attr,
2849 &sensor_dev_attr_pwm6_enable.dev_attr.attr,
2850 &sensor_dev_attr_pwm6.dev_attr.attr,
2851 &sensor_dev_attr_pwm6_freq.dev_attr.attr,
2852 &sensor_dev_attr_pwm6_auto_channels_temp.dev_attr.attr,
2857 static const struct attribute_group it87_group_pwm = {
2858 .attrs = it87_attributes_pwm,
2859 .is_visible = it87_pwm_is_visible,
2862 static umode_t it87_auto_pwm_is_visible(struct kobject *kobj,
2863 struct attribute *attr, int index)
2865 struct device *dev = container_of(kobj, struct device, kobj);
2866 struct it87_data *data = dev_get_drvdata(dev);
2867 int i = index / 11; /* pwm index */
2868 int a = index % 11; /* attribute index */
2870 if (index >= 33) { /* pwm 4..6 */
2871 i = (index - 33) / 6 + 3;
2872 a = (index - 33) % 6 + 4;
2875 if (!(data->has_pwm & BIT(i)))
2878 if (has_newer_autopwm(data)) {
2879 if (a < 4) /* no auto point pwm */
2881 if (a == 8) /* no auto_point4 */
2884 if (has_old_autopwm(data)) {
2885 if (a >= 9) /* no pwm_auto_start, pwm_auto_slope */
2892 static struct attribute *it87_attributes_auto_pwm[] = {
2893 &sensor_dev_attr_pwm1_auto_point1_pwm.dev_attr.attr,
2894 &sensor_dev_attr_pwm1_auto_point2_pwm.dev_attr.attr,
2895 &sensor_dev_attr_pwm1_auto_point3_pwm.dev_attr.attr,
2896 &sensor_dev_attr_pwm1_auto_point4_pwm.dev_attr.attr,
2897 &sensor_dev_attr_pwm1_auto_point1_temp.dev_attr.attr,
2898 &sensor_dev_attr_pwm1_auto_point1_temp_hyst.dev_attr.attr,
2899 &sensor_dev_attr_pwm1_auto_point2_temp.dev_attr.attr,
2900 &sensor_dev_attr_pwm1_auto_point3_temp.dev_attr.attr,
2901 &sensor_dev_attr_pwm1_auto_point4_temp.dev_attr.attr,
2902 &sensor_dev_attr_pwm1_auto_start.dev_attr.attr,
2903 &sensor_dev_attr_pwm1_auto_slope.dev_attr.attr,
2905 &sensor_dev_attr_pwm2_auto_point1_pwm.dev_attr.attr, /* 11 */
2906 &sensor_dev_attr_pwm2_auto_point2_pwm.dev_attr.attr,
2907 &sensor_dev_attr_pwm2_auto_point3_pwm.dev_attr.attr,
2908 &sensor_dev_attr_pwm2_auto_point4_pwm.dev_attr.attr,
2909 &sensor_dev_attr_pwm2_auto_point1_temp.dev_attr.attr,
2910 &sensor_dev_attr_pwm2_auto_point1_temp_hyst.dev_attr.attr,
2911 &sensor_dev_attr_pwm2_auto_point2_temp.dev_attr.attr,
2912 &sensor_dev_attr_pwm2_auto_point3_temp.dev_attr.attr,
2913 &sensor_dev_attr_pwm2_auto_point4_temp.dev_attr.attr,
2914 &sensor_dev_attr_pwm2_auto_start.dev_attr.attr,
2915 &sensor_dev_attr_pwm2_auto_slope.dev_attr.attr,
2917 &sensor_dev_attr_pwm3_auto_point1_pwm.dev_attr.attr, /* 22 */
2918 &sensor_dev_attr_pwm3_auto_point2_pwm.dev_attr.attr,
2919 &sensor_dev_attr_pwm3_auto_point3_pwm.dev_attr.attr,
2920 &sensor_dev_attr_pwm3_auto_point4_pwm.dev_attr.attr,
2921 &sensor_dev_attr_pwm3_auto_point1_temp.dev_attr.attr,
2922 &sensor_dev_attr_pwm3_auto_point1_temp_hyst.dev_attr.attr,
2923 &sensor_dev_attr_pwm3_auto_point2_temp.dev_attr.attr,
2924 &sensor_dev_attr_pwm3_auto_point3_temp.dev_attr.attr,
2925 &sensor_dev_attr_pwm3_auto_point4_temp.dev_attr.attr,
2926 &sensor_dev_attr_pwm3_auto_start.dev_attr.attr,
2927 &sensor_dev_attr_pwm3_auto_slope.dev_attr.attr,
2929 &sensor_dev_attr_pwm4_auto_point1_temp.dev_attr.attr, /* 33 */
2930 &sensor_dev_attr_pwm4_auto_point1_temp_hyst.dev_attr.attr,
2931 &sensor_dev_attr_pwm4_auto_point2_temp.dev_attr.attr,
2932 &sensor_dev_attr_pwm4_auto_point3_temp.dev_attr.attr,
2933 &sensor_dev_attr_pwm4_auto_start.dev_attr.attr,
2934 &sensor_dev_attr_pwm4_auto_slope.dev_attr.attr,
2936 &sensor_dev_attr_pwm5_auto_point1_temp.dev_attr.attr,
2937 &sensor_dev_attr_pwm5_auto_point1_temp_hyst.dev_attr.attr,
2938 &sensor_dev_attr_pwm5_auto_point2_temp.dev_attr.attr,
2939 &sensor_dev_attr_pwm5_auto_point3_temp.dev_attr.attr,
2940 &sensor_dev_attr_pwm5_auto_start.dev_attr.attr,
2941 &sensor_dev_attr_pwm5_auto_slope.dev_attr.attr,
2943 &sensor_dev_attr_pwm6_auto_point1_temp.dev_attr.attr,
2944 &sensor_dev_attr_pwm6_auto_point1_temp_hyst.dev_attr.attr,
2945 &sensor_dev_attr_pwm6_auto_point2_temp.dev_attr.attr,
2946 &sensor_dev_attr_pwm6_auto_point3_temp.dev_attr.attr,
2947 &sensor_dev_attr_pwm6_auto_start.dev_attr.attr,
2948 &sensor_dev_attr_pwm6_auto_slope.dev_attr.attr,
2953 static const struct attribute_group it87_group_auto_pwm = {
2954 .attrs = it87_attributes_auto_pwm,
2955 .is_visible = it87_auto_pwm_is_visible,
2958 /* SuperIO detection - will change isa_address if a chip is found */
2959 static int __init it87_find(int sioaddr, unsigned short *address,
2960 phys_addr_t *mmio_address,
2961 struct it87_sio_data *sio_data)
2963 const struct it87_devices *config;
2964 phys_addr_t base = 0;
2970 err = superio_enter(sioaddr);
2974 sio_data->sioaddr = sioaddr;
2977 chip_type = superio_inw(sioaddr, DEVID);
2978 if (chip_type == 0xffff)
2982 chip_type = force_id;
2984 switch (chip_type) {
2986 sio_data->type = it87;
2989 sio_data->type = it8712;
2993 sio_data->type = it8716;
2996 sio_data->type = it8718;
2999 sio_data->type = it8720;
3002 sio_data->type = it8721;
3005 sio_data->type = it8728;
3008 sio_data->type = it8732;
3011 sio_data->type = it8792;
3013 * Disabling configuration mode on IT8792E can result in system
3014 * hang-ups and access failures to the Super-IO chip at the
3015 * second SIO address. Never exit configuration mode on this
3016 * chip to avoid the problem.
3021 sio_data->type = it8771;
3024 sio_data->type = it8772;
3027 sio_data->type = it8781;
3030 sio_data->type = it8782;
3033 sio_data->type = it8783;
3036 sio_data->type = it8786;
3039 sio_data->type = it8790;
3040 doexit = false; /* See IT8792E comment above */
3044 sio_data->type = it8603;
3047 sio_data->type = it8606;
3050 sio_data->type = it8607;
3053 sio_data->type = it8613;
3056 sio_data->type = it8620;
3059 sio_data->type = it8622;
3062 sio_data->type = it8625;
3065 sio_data->type = it8628;
3068 sio_data->type = it8655;
3071 sio_data->type = it8665;
3074 sio_data->type = it8686;
3076 case 0xffff: /* No device at all */
3079 pr_debug("Unsupported chip (DEVID=0x%x)\n", chip_type);
3083 superio_select(sioaddr, PME);
3084 if (!(superio_inb(sioaddr, IT87_ACT_REG) & 0x01)) {
3085 pr_info("Device not activated, skipping\n");
3089 *address = superio_inw(sioaddr, IT87_BASE_REG) & ~(IT87_EXTENT - 1);
3090 if (*address == 0) {
3091 pr_info("Base address not set, skipping\n");
3095 sio_data->doexit = doexit;
3098 sio_data->revision = superio_inb(sioaddr, DEVREV) & 0x0f;
3100 config = &it87_devices[sio_data->type];
3102 if (has_mmio(config) && mmio) {
3105 reg = superio_inb(sioaddr, IT87_EC_HWM_MIO_REG);
3107 base = 0xf0000000 + ((reg & 0x0f) << 24);
3108 base += (reg & 0xc0) << 14;
3111 *mmio_address = base;
3115 snprintf(mmio_str, sizeof(mmio_str), " [MMIO at %pa]", &base);
3117 pr_info("Found %s chip at 0x%x%s, revision %d\n",
3118 it87_devices[sio_data->type].model,
3119 *address, mmio_str, sio_data->revision);
3121 /* in7 (VSB or VCCH5V) is always internal on some chips */
3122 if (has_in7_internal(config))
3123 sio_data->internal |= BIT(1);
3125 /* in8 (Vbat) is always internal */
3126 sio_data->internal |= BIT(2);
3128 /* in9 (AVCC3), always internal if supported */
3129 if (has_avcc3(config))
3130 sio_data->internal |= BIT(3); /* in9 is AVCC */
3132 sio_data->skip_in |= BIT(9);
3134 if (!has_four_pwm(config))
3135 sio_data->skip_pwm |= BIT(3) | BIT(4) | BIT(5);
3136 else if (!has_five_pwm(config))
3137 sio_data->skip_pwm |= BIT(4) | BIT(5);
3138 else if (!has_six_pwm(config))
3139 sio_data->skip_pwm |= BIT(5);
3141 if (!has_vid(config))
3142 sio_data->skip_vid = 1;
3144 /* Read GPIO config and VID value from LDN 7 (GPIO) */
3145 if (sio_data->type == it87) {
3146 /* The IT8705F has a different LD number for GPIO */
3147 superio_select(sioaddr, 5);
3148 sio_data->beep_pin = superio_inb(sioaddr,
3149 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3150 } else if (sio_data->type == it8783) {
3151 int reg25, reg27, reg2a, reg2c, regef;
3153 superio_select(sioaddr, GPIO);
3155 reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3156 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3157 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3158 reg2c = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3159 regef = superio_inb(sioaddr, IT87_SIO_SPI_REG);
3161 /* Check if fan3 is there or not */
3162 if ((reg27 & BIT(0)) || !(reg2c & BIT(2)))
3163 sio_data->skip_fan |= BIT(2);
3164 if ((reg25 & BIT(4)) ||
3165 (!(reg2a & BIT(1)) && (regef & BIT(0))))
3166 sio_data->skip_pwm |= BIT(2);
3168 /* Check if fan2 is there or not */
3170 sio_data->skip_fan |= BIT(1);
3172 sio_data->skip_pwm |= BIT(1);
3175 if ((reg27 & BIT(0)) || (reg2c & BIT(2)))
3176 sio_data->skip_in |= BIT(5); /* No VIN5 */
3180 sio_data->skip_in |= BIT(6); /* No VIN6 */
3184 * Does not depend on bit 2 of Reg2C, contrary to datasheet.
3186 if (reg27 & BIT(2)) {
3188 * The data sheet is a bit unclear regarding the
3189 * internal voltage divider for VCCH5V. It says
3190 * "This bit enables and switches VIN7 (pin 91) to the
3191 * internal voltage divider for VCCH5V".
3192 * This is different to other chips, where the internal
3193 * voltage divider would connect VIN7 to an internal
3194 * voltage source. Maybe that is the case here as well.
3196 * Since we don't know for sure, re-route it if that is
3197 * not the case, and ask the user to report if the
3198 * resulting voltage is sane.
3200 if (!(reg2c & BIT(1))) {
3202 superio_outb(sioaddr, IT87_SIO_PINX2_REG,
3204 pr_notice("Routing internal VCCH5V to in7.\n");
3206 pr_notice("in7 routed to internal voltage divider, with external pin disabled.\n");
3207 pr_notice("Please report if it displays a reasonable voltage.\n");
3211 sio_data->internal |= BIT(0);
3213 sio_data->internal |= BIT(1);
3215 sio_data->beep_pin = superio_inb(sioaddr,
3216 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3217 } else if (sio_data->type == it8603 || sio_data->type == it8606 ||
3218 sio_data->type == it8607) {
3221 superio_select(sioaddr, GPIO);
3223 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3225 /* Check if fan3 is there or not */
3227 sio_data->skip_pwm |= BIT(2);
3229 sio_data->skip_fan |= BIT(2);
3231 /* Check if fan2 is there or not */
3232 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3234 sio_data->skip_pwm |= BIT(1);
3236 sio_data->skip_fan |= BIT(1);
3238 switch (sio_data->type) {
3240 sio_data->skip_in |= BIT(5); /* No VIN5 */
3241 sio_data->skip_in |= BIT(6); /* No VIN6 */
3244 sio_data->skip_pwm |= BIT(0);/* No fan1 */
3245 sio_data->skip_fan |= BIT(0);
3250 sio_data->beep_pin = superio_inb(sioaddr,
3251 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3252 } else if (sio_data->type == it8613) {
3253 int reg27, reg29, reg2a;
3255 superio_select(sioaddr, GPIO);
3257 /* Check for pwm3, fan3, pwm5, fan5 */
3258 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3260 sio_data->skip_fan |= BIT(4);
3262 sio_data->skip_pwm |= BIT(4);
3264 sio_data->skip_pwm |= BIT(2);
3266 sio_data->skip_fan |= BIT(2);
3268 /* Check for pwm2, fan2 */
3269 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3271 sio_data->skip_pwm |= BIT(1);
3273 sio_data->skip_fan |= BIT(1);
3275 /* Check for pwm4, fan4 */
3276 reg2a = superio_inb(sioaddr, IT87_SIO_PINX1_REG);
3277 if (!(reg2a & BIT(0)) || (reg29 & BIT(7))) {
3278 sio_data->skip_fan |= BIT(3);
3279 sio_data->skip_pwm |= BIT(3);
3282 sio_data->skip_pwm |= BIT(0); /* No pwm1 */
3283 sio_data->skip_fan |= BIT(0); /* No fan1 */
3284 sio_data->skip_in |= BIT(3); /* No VIN3 */
3285 sio_data->skip_in |= BIT(6); /* No VIN6 */
3287 sio_data->beep_pin = superio_inb(sioaddr,
3288 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3289 } else if (sio_data->type == it8620 || sio_data->type == it8628 ||
3290 sio_data->type == it8686) {
3293 superio_select(sioaddr, GPIO);
3295 /* Check for pwm5 */
3296 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3298 sio_data->skip_pwm |= BIT(4);
3300 /* Check for fan4, fan5 */
3301 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3302 if (!(reg & BIT(5)))
3303 sio_data->skip_fan |= BIT(3);
3304 if (!(reg & BIT(4)))
3305 sio_data->skip_fan |= BIT(4);
3307 /* Check for pwm3, fan3 */
3308 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3310 sio_data->skip_pwm |= BIT(2);
3312 sio_data->skip_fan |= BIT(2);
3314 /* Check for pwm4 */
3315 reg = superio_inb(sioaddr, IT87_SIO_GPIO4_REG);
3317 sio_data->skip_pwm |= BIT(3);
3319 /* Check for pwm2, fan2 */
3320 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3322 sio_data->skip_pwm |= BIT(1);
3324 sio_data->skip_fan |= BIT(1);
3325 /* Check for pwm6, fan6 */
3326 if (!(reg & BIT(7))) {
3327 sio_data->skip_pwm |= BIT(5);
3328 sio_data->skip_fan |= BIT(5);
3331 /* Check if AVCC is on VIN3 */
3332 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3334 /* For it8686, the bit just enables AVCC3 */
3335 if (sio_data->type != it8686)
3336 sio_data->internal |= BIT(0);
3338 sio_data->internal &= ~BIT(3);
3339 sio_data->skip_in |= BIT(9);
3342 sio_data->beep_pin = superio_inb(sioaddr,
3343 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3344 } else if (sio_data->type == it8622) {
3347 superio_select(sioaddr, GPIO);
3349 /* Check for pwm4, fan4 */
3350 reg = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3352 sio_data->skip_fan |= BIT(3);
3354 sio_data->skip_pwm |= BIT(3);
3356 /* Check for pwm3, fan3, pwm5, fan5 */
3357 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3359 sio_data->skip_pwm |= BIT(2);
3361 sio_data->skip_fan |= BIT(2);
3363 sio_data->skip_pwm |= BIT(4);
3365 sio_data->skip_fan |= BIT(4);
3367 /* Check for pwm2, fan2 */
3368 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3370 sio_data->skip_pwm |= BIT(1);
3372 sio_data->skip_fan |= BIT(1);
3374 /* Check for AVCC */
3375 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3376 if (!(reg & BIT(0)))
3377 sio_data->skip_in |= BIT(9);
3379 sio_data->beep_pin = superio_inb(sioaddr,
3380 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3381 } else if (sio_data->type == it8732) {
3384 superio_select(sioaddr, GPIO);
3386 /* Check for pwm2, fan2 */
3387 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3389 sio_data->skip_pwm |= BIT(1);
3391 sio_data->skip_fan |= BIT(1);
3393 /* Check for pwm3, fan3, fan4 */
3394 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3396 sio_data->skip_pwm |= BIT(2);
3398 sio_data->skip_fan |= BIT(2);
3400 sio_data->skip_fan |= BIT(3);
3402 /* Check if AVCC is on VIN3 */
3403 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3405 sio_data->internal |= BIT(0);
3407 sio_data->beep_pin = superio_inb(sioaddr,
3408 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3409 } else if (sio_data->type == it8655) {
3412 superio_select(sioaddr, GPIO);
3414 /* Check for pwm2 */
3415 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3417 sio_data->skip_pwm |= BIT(1);
3419 /* Check for fan2 */
3420 reg = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3422 sio_data->skip_fan |= BIT(1);
3424 /* Check for pwm3, fan3 */
3425 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3427 sio_data->skip_pwm |= BIT(2);
3429 sio_data->skip_fan |= BIT(2);
3431 sio_data->beep_pin = superio_inb(sioaddr,
3432 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3433 } else if (sio_data->type == it8665 || sio_data->type == it8625) {
3434 int reg27, reg29, reg2d, regd3;
3436 superio_select(sioaddr, GPIO);
3438 reg27 = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3439 reg29 = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3440 reg2d = superio_inb(sioaddr, IT87_SIO_PINX4_REG);
3441 regd3 = superio_inb(sioaddr, IT87_SIO_GPIO9_REG);
3443 /* Check for pwm2, fan2 */
3445 sio_data->skip_pwm |= BIT(1);
3447 * Note: Table 6-1 in datasheet claims that FAN_TAC2
3448 * would be enabled with 29h[2]=0.
3451 sio_data->skip_fan |= BIT(1);
3453 /* Check for pwm3, fan3 */
3455 sio_data->skip_pwm |= BIT(2);
3457 sio_data->skip_fan |= BIT(2);
3459 /* Check for pwm4, fan4, pwm5, fan5 */
3460 if (sio_data->type == it8625) {
3461 int reg25 = superio_inb(sioaddr, IT87_SIO_GPIO1_REG);
3464 sio_data->skip_fan |= BIT(3);
3466 sio_data->skip_pwm |= BIT(3);
3468 sio_data->skip_pwm |= BIT(4);
3470 sio_data->skip_fan |= BIT(4);
3472 int reg26 = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3475 sio_data->skip_pwm |= BIT(3);
3477 sio_data->skip_fan |= BIT(3);
3479 sio_data->skip_pwm |= BIT(4);
3481 sio_data->skip_fan |= BIT(4);
3484 /* Check for pwm6, fan6 */
3486 sio_data->skip_pwm |= BIT(5);
3488 sio_data->skip_fan |= BIT(5);
3490 sio_data->beep_pin = superio_inb(sioaddr,
3491 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3496 superio_select(sioaddr, GPIO);
3498 /* Check for fan4, fan5 */
3499 if (has_five_fans(config)) {
3500 reg = superio_inb(sioaddr, IT87_SIO_GPIO2_REG);
3501 switch (sio_data->type) {
3504 sio_data->skip_fan |= BIT(3);
3506 sio_data->skip_fan |= BIT(4);
3511 if (!(reg & BIT(5)))
3512 sio_data->skip_fan |= BIT(3);
3513 if (!(reg & BIT(4)))
3514 sio_data->skip_fan |= BIT(4);
3521 reg = superio_inb(sioaddr, IT87_SIO_GPIO3_REG);
3522 if (!sio_data->skip_vid) {
3523 /* We need at least 4 VID pins */
3525 pr_info("VID is disabled (pins used for GPIO)\n");
3526 sio_data->skip_vid = 1;
3530 /* Check if fan3 is there or not */
3532 sio_data->skip_pwm |= BIT(2);
3534 sio_data->skip_fan |= BIT(2);
3536 /* Check if fan2 is there or not */
3537 reg = superio_inb(sioaddr, IT87_SIO_GPIO5_REG);
3539 sio_data->skip_pwm |= BIT(1);
3541 sio_data->skip_fan |= BIT(1);
3543 if ((sio_data->type == it8718 || sio_data->type == it8720) &&
3544 !(sio_data->skip_vid))
3545 sio_data->vid_value = superio_inb(sioaddr,
3548 reg = superio_inb(sioaddr, IT87_SIO_PINX2_REG);
3550 uart6 = sio_data->type == it8782 && (reg & BIT(2));
3553 * The IT8720F has no VIN7 pin, so VCCH should always be
3554 * routed internally to VIN7 with an internal divider.
3555 * Curiously, there still is a configuration bit to control
3556 * this, which means it can be set incorrectly. And even
3557 * more curiously, many boards out there are improperly
3558 * configured, even though the IT8720F datasheet claims
3559 * that the internal routing of VCCH to VIN7 is the default
3560 * setting. So we force the internal routing in this case.
3562 * On IT8782F, VIN7 is multiplexed with one of the UART6 pins.
3563 * If UART6 is enabled, re-route VIN7 to the internal divider
3564 * if that is not already the case.
3566 if ((sio_data->type == it8720 || uart6) && !(reg & BIT(1))) {
3568 superio_outb(sioaddr, IT87_SIO_PINX2_REG, reg);
3569 pr_notice("Routing internal VCCH to in7\n");
3572 sio_data->internal |= BIT(0);
3574 sio_data->internal |= BIT(1);
3577 * On IT8782F, UART6 pins overlap with VIN5, VIN6, and VIN7.
3578 * While VIN7 can be routed to the internal voltage divider,
3579 * VIN5 and VIN6 are not available if UART6 is enabled.
3581 * Also, temp3 is not available if UART6 is enabled and TEMPIN3
3582 * is the temperature source. Since we can not read the
3583 * temperature source here, skip_temp is preliminary.
3586 sio_data->skip_in |= BIT(5) | BIT(6);
3587 sio_data->skip_temp |= BIT(2);
3590 sio_data->beep_pin = superio_inb(sioaddr,
3591 IT87_SIO_BEEP_PIN_REG) & 0x3f;
3593 if (sio_data->beep_pin)
3594 pr_info("Beeping is supported\n");
3596 if (config->smbus_bitmap && !base) {
3599 superio_select(sioaddr, PME);
3600 reg = superio_inb(sioaddr, IT87_SPECIAL_CFG_REG);
3601 sio_data->ec_special_config = reg;
3602 sio_data->smbus_bitmap = reg & config->smbus_bitmap;
3606 superio_exit(sioaddr, doexit);
3610 static void it87_init_regs(struct platform_device *pdev)
3612 struct it87_data *data = platform_get_drvdata(pdev);
3614 /* Initialize chip specific register pointers */
3615 switch (data->type) {
3618 data->REG_FAN = IT87_REG_FAN;
3619 data->REG_FANX = IT87_REG_FANX;
3620 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3621 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3622 data->REG_PWM = IT87_REG_PWM;
3623 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET_8686;
3624 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW_8686;
3625 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH_8686;
3630 data->REG_FAN = IT87_REG_FAN_8665;
3631 data->REG_FANX = IT87_REG_FANX_8665;
3632 data->REG_FAN_MIN = IT87_REG_FAN_MIN_8665;
3633 data->REG_FANX_MIN = IT87_REG_FANX_MIN_8665;
3634 data->REG_PWM = IT87_REG_PWM_8665;
3635 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3636 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3637 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3640 data->REG_FAN = IT87_REG_FAN;
3641 data->REG_FANX = IT87_REG_FANX;
3642 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3643 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3644 data->REG_PWM = IT87_REG_PWM_8665;
3645 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3646 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3647 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3650 data->REG_FAN = IT87_REG_FAN;
3651 data->REG_FANX = IT87_REG_FANX;
3652 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3653 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3654 data->REG_PWM = IT87_REG_PWM_8665;
3655 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3656 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3657 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3660 data->REG_FAN = IT87_REG_FAN;
3661 data->REG_FANX = IT87_REG_FANX;
3662 data->REG_FAN_MIN = IT87_REG_FAN_MIN;
3663 data->REG_FANX_MIN = IT87_REG_FANX_MIN;
3664 data->REG_PWM = IT87_REG_PWM;
3665 data->REG_TEMP_OFFSET = IT87_REG_TEMP_OFFSET;
3666 data->REG_TEMP_LOW = IT87_REG_TEMP_LOW;
3667 data->REG_TEMP_HIGH = IT87_REG_TEMP_HIGH;
3672 data->read = it87_mmio_read;
3673 data->write = it87_mmio_write;
3674 } else if (has_bank_sel(data)) {
3675 data->read = it87_io_read;
3676 data->write = it87_io_write;
3678 data->read = _it87_io_read;
3679 data->write = _it87_io_write;
3683 /* Called when we have found a new IT87. */
3684 static void it87_init_device(struct platform_device *pdev)
3686 struct it87_sio_data *sio_data = dev_get_platdata(&pdev->dev);
3687 struct it87_data *data = platform_get_drvdata(pdev);
3691 if (has_new_tempmap(data)) {
3692 data->pwm_temp_map_shift = 3;
3693 data->pwm_temp_map_mask = 0x07;
3695 data->pwm_temp_map_shift = 0;
3696 data->pwm_temp_map_mask = 0x03;
3700 * For each PWM channel:
3701 * - If it is in automatic mode, setting to manual mode should set
3702 * the fan to full speed by default.
3703 * - If it is in manual mode, we need a mapping to temperature
3704 * channels to use when later setting to automatic mode later.
3705 * Map to the first sensor by default (we are clueless.)
3706 * In both cases, the value can (and should) be changed by the user
3707 * prior to switching to a different mode.
3708 * Note that this is no longer needed for the IT8721F and later, as
3709 * these have separate registers for the temperature mapping and the
3710 * manual duty cycle.
3712 for (i = 0; i < NUM_AUTO_PWM; i++) {
3713 data->pwm_temp_map[i] = 0;
3714 data->pwm_duty[i] = 0x7f; /* Full speed */
3715 data->auto_pwm[i][3] = 0x7f; /* Full speed, hard-coded */
3719 * Some chips seem to have default value 0xff for all limit
3720 * registers. For low voltage limits it makes no sense and triggers
3721 * alarms, so change to 0 instead. For high temperature limits, it
3722 * means -1 degree C, which surprisingly doesn't trigger an alarm,
3723 * but is still confusing, so change to 127 degrees C.
3725 for (i = 0; i < NUM_VIN_LIMIT; i++) {
3726 tmp = data->read(data, IT87_REG_VIN_MIN(i));
3728 data->write(data, IT87_REG_VIN_MIN(i), 0);
3730 for (i = 0; i < data->num_temp_limit; i++) {
3731 tmp = data->read(data, data->REG_TEMP_HIGH[i]);
3733 data->write(data, data->REG_TEMP_HIGH[i], 127);
3737 * Temperature channels are not forcibly enabled, as they can be
3738 * set to two different sensor types and we can't guess which one
3739 * is correct for a given system. These channels can be enabled at
3740 * run-time through the temp{1-3}_type sysfs accessors if needed.
3743 /* Check if voltage monitors are reset manually or by some reason */
3744 tmp = data->read(data, IT87_REG_VIN_ENABLE);
3745 if ((tmp & 0xff) == 0) {
3746 /* Enable all voltage monitors */
3747 data->write(data, IT87_REG_VIN_ENABLE, 0xff);
3750 /* Check if tachometers are reset manually or by some reason */
3751 mask = 0x70 & ~(sio_data->skip_fan << 4);
3752 data->fan_main_ctrl = data->read(data, IT87_REG_FAN_MAIN_CTRL);
3753 if ((data->fan_main_ctrl & mask) == 0) {
3754 /* Enable all fan tachometers */
3755 data->fan_main_ctrl |= mask;
3756 data->write(data, IT87_REG_FAN_MAIN_CTRL, data->fan_main_ctrl);
3758 data->has_fan = (data->fan_main_ctrl >> 4) & 0x07;
3760 tmp = data->read(data, IT87_REG_FAN_16BIT);
3762 /* Set tachometers to 16-bit mode if needed */
3763 if (has_fan16_config(data)) {
3764 if (~tmp & 0x07 & data->has_fan) {
3766 "Setting fan1-3 to 16-bit mode\n");
3767 data->write(data, IT87_REG_FAN_16BIT, tmp | 0x07);
3771 /* Check for additional fans */
3772 if (has_four_fans(data) && (tmp & BIT(4)))
3773 data->has_fan |= BIT(3); /* fan4 enabled */
3774 if (has_five_fans(data) && (tmp & BIT(5)))
3775 data->has_fan |= BIT(4); /* fan5 enabled */
3776 if (has_six_fans(data)) {
3777 switch (data->type) {
3782 data->has_fan |= BIT(5); /* fan6 enabled */
3786 tmp = data->read(data, IT87_REG_FAN_DIV);
3788 data->has_fan |= BIT(5); /* fan6 enabled */
3795 /* Fan input pins may be used for alternative functions */
3796 data->has_fan &= ~sio_data->skip_fan;
3798 /* Check if pwm6 is enabled */
3799 if (has_six_pwm(data)) {
3800 switch (data->type) {
3803 tmp = data->read(data, IT87_REG_FAN_DIV);
3804 if (!(tmp & BIT(3)))
3805 sio_data->skip_pwm |= BIT(5);
3812 if (has_bank_sel(data)) {
3813 for (i = 0; i < 3; i++)
3815 data->read(data, IT87_REG_TEMP_SRC1[i]);
3816 data->temp_src[3] = data->read(data, IT87_REG_TEMP_SRC2);
3819 /* Start monitoring */
3820 data->write(data, IT87_REG_CONFIG,
3821 (data->read(data, IT87_REG_CONFIG) & 0x3e) |
3822 (update_vbat ? 0x41 : 0x01));
3825 /* Return 1 if and only if the PWM interface is safe to use */
3826 static int it87_check_pwm(struct device *dev)
3828 struct it87_data *data = dev_get_drvdata(dev);
3830 * Some BIOSes fail to correctly configure the IT87 fans. All fans off
3831 * and polarity set to active low is sign that this is the case so we
3832 * disable pwm control to protect the user.
3834 int tmp = data->read(data, IT87_REG_FAN_CTL);
3836 if ((tmp & 0x87) == 0) {
3837 if (fix_pwm_polarity) {
3839 * The user asks us to attempt a chip reconfiguration.
3840 * This means switching to active high polarity and
3841 * inverting all fan speed values.
3846 for (i = 0; i < ARRAY_SIZE(pwm); i++)
3847 pwm[i] = data->read(data,
3851 * If any fan is in automatic pwm mode, the polarity
3852 * might be correct, as suspicious as it seems, so we
3853 * better don't change anything (but still disable the
3856 if (!((pwm[0] | pwm[1] | pwm[2]) & 0x80)) {
3858 "Reconfiguring PWM to active high polarity\n");
3859 data->write(data, IT87_REG_FAN_CTL, tmp | 0x87);
3860 for (i = 0; i < 3; i++)
3861 data->write(data, data->REG_PWM[i],
3867 "PWM configuration is too broken to be fixed\n");
3871 "Detected broken BIOS defaults, disabling PWM interface\n");
3873 } else if (fix_pwm_polarity) {
3875 "PWM configuration looks sane, won't touch\n");
3881 static int it87_probe(struct platform_device *pdev)
3883 struct it87_data *data;
3884 struct resource *res;
3885 struct device *dev = &pdev->dev;
3886 struct it87_sio_data *sio_data = dev_get_platdata(dev);
3887 int enable_pwm_interface;
3888 struct device *hwmon_dev;
3891 data = devm_kzalloc(dev, sizeof(struct it87_data), GFP_KERNEL);
3895 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
3897 if (!devm_request_region(dev, res->start, IT87_EC_EXTENT,
3899 dev_err(dev, "Failed to request region %pR\n", res);
3903 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3904 data->mmio = devm_ioremap_resource(dev, res);
3905 if (IS_ERR(data->mmio))
3906 return PTR_ERR(data->mmio);
3909 data->addr = res->start;
3910 data->type = sio_data->type;
3911 data->sioaddr = sio_data->sioaddr;
3912 data->smbus_bitmap = sio_data->smbus_bitmap;
3913 data->ec_special_config = sio_data->ec_special_config;
3914 data->doexit = sio_data->doexit;
3915 data->features = it87_devices[sio_data->type].features;
3916 data->num_temp_limit = it87_devices[sio_data->type].num_temp_limit;
3917 data->num_temp_offset = it87_devices[sio_data->type].num_temp_offset;
3918 data->pwm_num_temp_map = it87_devices[sio_data->type].num_temp_map;
3919 data->peci_mask = it87_devices[sio_data->type].peci_mask;
3920 data->old_peci_mask = it87_devices[sio_data->type].old_peci_mask;
3923 * IT8705F Datasheet 0.4.1, 3h == Version G.
3924 * IT8712F Datasheet 0.9.1, section 8.3.5 indicates 8h == Version J.
3925 * These are the first revisions with 16-bit tachometer support.
3927 switch (data->type) {
3929 if (sio_data->revision >= 0x03) {
3930 data->features &= ~FEAT_OLD_AUTOPWM;
3931 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS;
3935 if (sio_data->revision >= 0x08) {
3936 data->features &= ~FEAT_OLD_AUTOPWM;
3937 data->features |= FEAT_FAN16_CONFIG | FEAT_16BIT_FANS |
3945 platform_set_drvdata(pdev, data);
3947 mutex_init(&data->update_lock);
3949 /* Initialize register pointers */
3950 it87_init_regs(pdev);
3953 * We need to disable SMBus before we can read any registers in
3954 * the envmon address space, even if it is for chip identification
3955 * purposes. If the chip has SMBus client support, it likely also has
3956 * multi-page envmon registers, so we have to set the page anyway
3957 * before accessing those registers. Kind of a chicken-and-egg
3959 * Fortunately, the chip was already identified through the SIO
3960 * address space, only recent chips are affected, and this is just
3961 * an additional safeguard.
3963 err = smbus_disable(data);
3967 /* Now, we do the remaining detection. */
3968 if ((data->read(data, IT87_REG_CONFIG) & 0x80) ||
3969 data->read(data, IT87_REG_CHIPID) != 0x90) {
3974 /* Check PWM configuration */
3975 enable_pwm_interface = it87_check_pwm(dev);
3977 /* Starting with IT8721F, we handle scaling of internal voltages */
3978 if (has_scaling(data)) {
3979 if (sio_data->internal & BIT(0))
3980 data->in_scaled |= BIT(3); /* in3 is AVCC */
3981 if (sio_data->internal & BIT(1))
3982 data->in_scaled |= BIT(7); /* in7 is VSB */
3983 if (sio_data->internal & BIT(2))
3984 data->in_scaled |= BIT(8); /* in8 is Vbat */
3985 if (sio_data->internal & BIT(3))
3986 data->in_scaled |= BIT(9); /* in9 is AVCC */
3987 } else if (sio_data->type == it8781 || sio_data->type == it8782 ||
3988 sio_data->type == it8783) {
3989 if (sio_data->internal & BIT(0))
3990 data->in_scaled |= BIT(3); /* in3 is VCC5V */
3991 if (sio_data->internal & BIT(1))
3992 data->in_scaled |= BIT(7); /* in7 is VCCH5V */
3995 data->has_temp = 0x07;
3996 if (sio_data->skip_temp & BIT(2)) {
3997 if (sio_data->type == it8782 &&
3998 !(data->read(data, IT87_REG_TEMP_EXTRA) & 0x80))
3999 data->has_temp &= ~BIT(2);
4002 data->in_internal = sio_data->internal;
4003 data->has_in = 0x3ff & ~sio_data->skip_in;
4005 if (has_four_temp(data)) {
4006 data->has_temp |= BIT(3);
4007 } else if (has_six_temp(data)) {
4008 u8 reg = data->read(data, IT87_REG_TEMP456_ENABLE);
4010 /* Check for additional temperature sensors */
4011 if ((reg & 0x03) >= 0x02)
4012 data->has_temp |= BIT(3);
4013 if (((reg >> 2) & 0x03) >= 0x02)
4014 data->has_temp |= BIT(4);
4015 if (((reg >> 4) & 0x03) >= 0x02)
4016 data->has_temp |= BIT(5);
4018 /* Check for additional voltage sensors */
4019 if ((reg & 0x03) == 0x01)
4020 data->has_in |= BIT(10);
4021 if (((reg >> 2) & 0x03) == 0x01)
4022 data->has_in |= BIT(11);
4023 if (((reg >> 4) & 0x03) == 0x01)
4024 data->has_in |= BIT(12);
4027 data->has_beep = !!sio_data->beep_pin;
4029 /* Initialize the IT87 chip */
4030 it87_init_device(pdev);
4034 if (!sio_data->skip_vid) {
4035 data->has_vid = true;
4036 data->vrm = vid_which_vrm();
4037 /* VID reading from Super-I/O config space if available */
4038 data->vid = sio_data->vid_value;
4041 /* Prepare for sysfs hooks */
4042 data->groups[0] = &it87_group;
4043 data->groups[1] = &it87_group_in;
4044 data->groups[2] = &it87_group_temp;
4045 data->groups[3] = &it87_group_fan;
4047 if (enable_pwm_interface) {
4048 data->has_pwm = BIT(ARRAY_SIZE(IT87_REG_PWM)) - 1;
4049 data->has_pwm &= ~sio_data->skip_pwm;
4051 data->groups[4] = &it87_group_pwm;
4052 if (has_old_autopwm(data) || has_newer_autopwm(data))
4053 data->groups[5] = &it87_group_auto_pwm;
4056 hwmon_dev = devm_hwmon_device_register_with_groups(dev,
4057 it87_devices[sio_data->type].name,
4058 data, data->groups);
4059 return PTR_ERR_OR_ZERO(hwmon_dev);
4062 static struct platform_driver it87_driver = {
4066 .probe = it87_probe,
4069 static int __init it87_device_add(int index, unsigned short sio_address,
4070 phys_addr_t mmio_address,
4071 const struct it87_sio_data *sio_data)
4073 struct platform_device *pdev;
4074 struct resource res = {
4080 res.start = mmio_address;
4081 res.end = mmio_address + 0x400 - 1;
4082 res.flags = IORESOURCE_MEM;
4084 res.start = sio_address + IT87_EC_OFFSET;
4085 res.end = sio_address + IT87_EC_OFFSET + IT87_EC_EXTENT - 1;
4086 res.flags = IORESOURCE_IO;
4089 err = acpi_check_resource_conflict(&res);
4091 if (!ignore_resource_conflict)
4095 pdev = platform_device_alloc(DRVNAME, sio_address);
4099 err = platform_device_add_resources(pdev, &res, 1);
4101 pr_err("Device resource addition failed (%d)\n", err);
4102 goto exit_device_put;
4105 err = platform_device_add_data(pdev, sio_data,
4106 sizeof(struct it87_sio_data));
4108 pr_err("Platform data allocation failed\n");
4109 goto exit_device_put;
4112 err = platform_device_add(pdev);
4114 pr_err("Device addition failed (%d)\n", err);
4115 goto exit_device_put;
4118 it87_pdev[index] = pdev;
4122 platform_device_put(pdev);
4126 struct it87_dmi_data {
4127 bool sio2_force_config; /* force sio2 into configuration mode */
4128 u8 skip_pwm; /* pwm channels to skip for this board */
4132 * On various Gigabyte AM4 boards (AB350, AX370), the second Super-IO chip
4133 * (IT8792E) needs to be in configuration mode before accessing the first
4134 * due to a bug in IT8792E which otherwise results in LPC bus access errors.
4135 * This needs to be done before accessing the first Super-IO chip since
4136 * the second chip may have been accessed prior to loading this driver.
4138 * The problem is also reported to affect IT8795E, which is used on X299 boards
4139 * and has the same chip ID as IT8792E (0x8733). It also appears to affect
4140 * systems with IT8790E, which is used on some Z97X-Gaming boards as well as
4142 * DMI entries for those systems will be added as they become available and
4143 * as the problem is confirmed to affect those boards.
4145 static struct it87_dmi_data gigabyte_sio2_force = {
4146 .sio2_force_config = true,
4150 * On the Shuttle SN68PT, FAN_CTL2 is apparently not
4151 * connected to a fan, but to something else. One user
4152 * has reported instant system power-off when changing
4153 * the PWM2 duty cycle, so we disable it.
4154 * I use the board name string as the trigger in case
4155 * the same board is ever used in other systems.
4157 static struct it87_dmi_data nvidia_fn68pt = {
4161 static const struct dmi_system_id it87_dmi_table[] __initconst = {
4164 DMI_MATCH(DMI_SYS_VENDOR,
4165 "Gigabyte Technology Co., Ltd."),
4166 DMI_MATCH(DMI_BOARD_NAME, "AB350"),
4168 .driver_data = &gigabyte_sio2_force,
4172 DMI_MATCH(DMI_SYS_VENDOR,
4173 "Gigabyte Technology Co., Ltd."),
4174 DMI_MATCH(DMI_BOARD_NAME, "AX370"),
4176 .driver_data = &gigabyte_sio2_force,
4180 DMI_MATCH(DMI_SYS_VENDOR,
4181 "Gigabyte Technology Co., Ltd."),
4182 DMI_MATCH(DMI_BOARD_NAME, "Z97X-Gaming G1"),
4184 .driver_data = &gigabyte_sio2_force,
4188 DMI_MATCH(DMI_BOARD_VENDOR, "nVIDIA"),
4189 DMI_MATCH(DMI_BOARD_NAME, "FN68PT"),
4191 .driver_data = &nvidia_fn68pt,
4196 static int __init sm_it87_init(void)
4198 const struct dmi_system_id *dmi = dmi_first_match(it87_dmi_table);
4199 struct it87_dmi_data *dmi_data = NULL;
4200 int sioaddr[2] = { REG_2E, REG_4E };
4201 struct it87_sio_data sio_data;
4202 unsigned short isa_address;
4203 phys_addr_t mmio_address;
4207 pr_info("it87 driver version %s\n", IT87_DRIVER_VERSION);
4210 dmi_data = dmi->driver_data;
4212 err = platform_driver_register(&it87_driver);
4216 if (dmi_data && dmi_data->sio2_force_config)
4217 __superio_enter(REG_4E);
4219 for (i = 0; i < ARRAY_SIZE(sioaddr); i++) {
4220 memset(&sio_data, 0, sizeof(struct it87_sio_data));
4223 err = it87_find(sioaddr[i], &isa_address, &mmio_address,
4225 if (err || isa_address == 0)
4229 sio_data.skip_pwm |= dmi_data->skip_pwm;
4230 err = it87_device_add(i, isa_address, mmio_address, &sio_data);
4232 goto exit_dev_unregister;
4238 goto exit_unregister;
4242 exit_dev_unregister:
4243 /* NULL check handled by platform_device_unregister */
4244 platform_device_unregister(it87_pdev[0]);
4246 platform_driver_unregister(&it87_driver);
4250 static void __exit sm_it87_exit(void)
4252 /* NULL check handled by platform_device_unregister */
4253 platform_device_unregister(it87_pdev[1]);
4254 platform_device_unregister(it87_pdev[0]);
4255 platform_driver_unregister(&it87_driver);
4258 MODULE_AUTHOR("Chris Gauthron, Jean Delvare <jdelvare@suse.de>");
4259 MODULE_DESCRIPTION("IT8705F/IT871xF/IT872xF hardware monitoring driver");
4260 module_param(update_vbat, bool, 0000);
4261 MODULE_PARM_DESC(update_vbat, "Update vbat if set else return powerup value");
4262 module_param(fix_pwm_polarity, bool, 0000);
4263 MODULE_PARM_DESC(fix_pwm_polarity,
4264 "Force PWM polarity to active high (DANGEROUS)");
4265 MODULE_LICENSE("GPL");
4267 module_init(sm_it87_init);
4268 module_exit(sm_it87_exit);