2 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
4 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License; either
9 * version 2 of the License, or (at your option) any later version.
11 * This driver is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 * See the GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
20 #include <linux/err.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <asm/processor.h>
29 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
30 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
31 MODULE_LICENSE("GPL");
34 module_param(force, bool, 0444);
35 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
37 /* Provide lock for writing to NB_SMU_IND_ADDR */
38 static DEFINE_MUTEX(nb_smu_ind_mutex);
40 #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
41 #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
44 #ifndef PCI_DEVICE_ID_AMD_17H_RR_NB
45 #define PCI_DEVICE_ID_AMD_17H_RR_NB 0x15d0
48 /* CPUID function 0x80000001, ebx */
49 #define CPUID_PKGTYPE_MASK 0xf0000000
50 #define CPUID_PKGTYPE_F 0x00000000
51 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
53 /* DRAM controller (PCI function 2) */
54 #define REG_DCT0_CONFIG_HIGH 0x094
55 #define DDR3_MODE 0x00000100
57 /* miscellaneous (PCI function 3) */
58 #define REG_HARDWARE_THERMAL_CONTROL 0x64
59 #define HTC_ENABLE 0x00000001
61 #define REG_REPORTED_TEMPERATURE 0xa4
63 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
64 #define NB_CAP_HTC 0x00000400
67 * For F15h M60h, functionality of REG_HARDWARE_THERMAL_CONTROL
68 * and REG_REPORTED_TEMPERATURE has been moved to
69 * D0F0xBC_xD820_0C64 [Hardware Temperature Control]
70 * D0F0xBC_xD820_0CA4 [Reported Temperature Control]
72 #define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
73 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
75 /* F17h M01h Access througn SMN */
76 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
80 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
81 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
92 static const struct tctl_offset tctl_offset_table[] = {
93 { 0x17, "AMD Ryzen 5 1600X", 20000 },
94 { 0x17, "AMD Ryzen 7 1700X", 20000 },
95 { 0x17, "AMD Ryzen 7 1800X", 20000 },
96 { 0x17, "AMD Ryzen 7 2700X", 10000 },
97 { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
98 { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
99 { 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
100 { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
101 { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
102 { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
105 static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
107 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
110 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
112 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
115 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
116 unsigned int base, int offset, u32 *val)
118 mutex_lock(&nb_smu_ind_mutex);
119 pci_bus_write_config_dword(pdev->bus, devfn,
121 pci_bus_read_config_dword(pdev->bus, devfn,
123 mutex_unlock(&nb_smu_ind_mutex);
126 static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
128 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
129 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
132 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
134 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
135 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
138 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
140 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
141 F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
144 static ssize_t temp1_input_show(struct device *dev,
145 struct device_attribute *attr, char *buf)
147 struct k10temp_data *data = dev_get_drvdata(dev);
151 data->read_tempreg(data->pdev, ®val);
152 temp = (regval >> 21) * 125;
153 if (regval & data->temp_adjust_mask)
155 if (temp > data->temp_offset)
156 temp -= data->temp_offset;
160 return sprintf(buf, "%u\n", temp);
163 static ssize_t temp1_max_show(struct device *dev,
164 struct device_attribute *attr, char *buf)
166 return sprintf(buf, "%d\n", 70 * 1000);
169 static ssize_t show_temp_crit(struct device *dev,
170 struct device_attribute *devattr, char *buf)
172 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
173 struct k10temp_data *data = dev_get_drvdata(dev);
174 int show_hyst = attr->index;
178 pci_read_config_dword(data->pdev,
179 REG_HARDWARE_THERMAL_CONTROL, ®val);
180 value = ((regval >> 16) & 0x7f) * 500 + 52000;
182 value -= ((regval >> 24) & 0xf) * 500;
183 return sprintf(buf, "%d\n", value);
186 static DEVICE_ATTR_RO(temp1_input);
187 static DEVICE_ATTR_RO(temp1_max);
188 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
189 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
191 static umode_t k10temp_is_visible(struct kobject *kobj,
192 struct attribute *attr, int index)
194 struct device *dev = container_of(kobj, struct device, kobj);
195 struct k10temp_data *data = dev_get_drvdata(dev);
196 struct pci_dev *pdev = data->pdev;
201 if (!data->read_htcreg)
204 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
206 if (!(reg & NB_CAP_HTC))
209 data->read_htcreg(data->pdev, ®);
210 if (!(reg & HTC_ENABLE))
216 static struct attribute *k10temp_attrs[] = {
217 &dev_attr_temp1_input.attr,
218 &dev_attr_temp1_max.attr,
219 &sensor_dev_attr_temp1_crit.dev_attr.attr,
220 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
224 static const struct attribute_group k10temp_group = {
225 .attrs = k10temp_attrs,
226 .is_visible = k10temp_is_visible,
228 __ATTRIBUTE_GROUPS(k10temp);
230 static bool has_erratum_319(struct pci_dev *pdev)
232 u32 pkg_type, reg_dram_cfg;
234 if (boot_cpu_data.x86 != 0x10)
238 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
241 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
242 if (pkg_type == CPUID_PKGTYPE_F)
244 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
247 /* DDR3 memory implies socket AM3, which is good */
248 pci_bus_read_config_dword(pdev->bus,
249 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
250 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
251 if (reg_dram_cfg & DDR3_MODE)
255 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
256 * memory. We blacklist all the cores which do exist in socket AM2+
257 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
258 * and AM3 formats, but that's the best we can do.
260 return boot_cpu_data.x86_model < 4 ||
261 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
264 static int k10temp_probe(struct pci_dev *pdev,
265 const struct pci_device_id *id)
267 int unreliable = has_erratum_319(pdev);
268 struct device *dev = &pdev->dev;
269 struct k10temp_data *data;
270 struct device *hwmon_dev;
276 "unreliable CPU thermal sensor; monitoring disabled\n");
280 "unreliable CPU thermal sensor; check erratum 319\n");
283 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
289 if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
290 boot_cpu_data.x86_model == 0x70)) {
291 data->read_htcreg = read_htcreg_nb_f15;
292 data->read_tempreg = read_tempreg_nb_f15;
293 } else if (boot_cpu_data.x86 == 0x17) {
294 data->temp_adjust_mask = 0x80000;
295 data->read_tempreg = read_tempreg_nb_f17;
297 data->read_htcreg = read_htcreg_pci;
298 data->read_tempreg = read_tempreg_pci;
301 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
302 const struct tctl_offset *entry = &tctl_offset_table[i];
304 if (boot_cpu_data.x86 == entry->model &&
305 strstr(boot_cpu_data.x86_model_id, entry->id)) {
306 data->temp_offset = entry->offset;
311 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
313 return PTR_ERR_OR_ZERO(hwmon_dev);
316 static const struct pci_device_id k10temp_id_table[] = {
317 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
318 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
319 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
320 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
321 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
322 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
323 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
324 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
325 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
326 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
327 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_RR_NB) },
330 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
332 static struct pci_driver k10temp_driver = {
334 .id_table = k10temp_id_table,
335 .probe = k10temp_probe,
338 module_pci_driver(k10temp_driver);