2 * k10temp.c - AMD Family 10h/11h/12h/14h/15h/16h processor hardware monitoring
4 * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
7 * This driver is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License; either
9 * version 2 of the License, or (at your option) any later version.
11 * This driver is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
14 * See the GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this driver; if not, see <http://www.gnu.org/licenses/>.
20 #include <linux/err.h>
21 #include <linux/hwmon.h>
22 #include <linux/hwmon-sysfs.h>
23 #include <linux/init.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <asm/processor.h>
29 MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
30 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
31 MODULE_LICENSE("GPL");
34 module_param(force, bool, 0444);
35 MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
37 /* Provide lock for writing to NB_SMU_IND_ADDR */
38 static DEFINE_MUTEX(nb_smu_ind_mutex);
40 #ifndef PCI_DEVICE_ID_AMD_17H_DF_F3
41 #define PCI_DEVICE_ID_AMD_17H_DF_F3 0x1463
44 /* CPUID function 0x80000001, ebx */
45 #define CPUID_PKGTYPE_MASK 0xf0000000
46 #define CPUID_PKGTYPE_F 0x00000000
47 #define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
49 /* DRAM controller (PCI function 2) */
50 #define REG_DCT0_CONFIG_HIGH 0x094
51 #define DDR3_MODE 0x00000100
53 /* miscellaneous (PCI function 3) */
54 #define REG_HARDWARE_THERMAL_CONTROL 0x64
55 #define HTC_ENABLE 0x00000001
57 #define REG_REPORTED_TEMPERATURE 0xa4
59 #define REG_NORTHBRIDGE_CAPABILITIES 0xe8
60 #define NB_CAP_HTC 0x00000400
63 * For F15h M60h, functionality of REG_REPORTED_TEMPERATURE
64 * has been moved to D0F0xBC_xD820_0CA4 [Reported Temperature
67 #define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
69 /* F17h M01h Access througn SMN */
70 #define F17H_M01H_REPORTED_TEMP_CTRL_OFFSET 0x00059800
74 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
84 static const struct tctl_offset tctl_offset_table[] = {
85 { 0x17, "AMD Ryzen 5 1600X", 20000 },
86 { 0x17, "AMD Ryzen 7 1700X", 20000 },
87 { 0x17, "AMD Ryzen 7 1800X", 20000 },
88 { 0x17, "AMD Ryzen 7 2700X", 10000 },
89 { 0x17, "AMD Ryzen Threadripper 1950X", 27000 },
90 { 0x17, "AMD Ryzen Threadripper 1920X", 27000 },
91 { 0x17, "AMD Ryzen Threadripper 1900X", 27000 },
92 { 0x17, "AMD Ryzen Threadripper 1950", 10000 },
93 { 0x17, "AMD Ryzen Threadripper 1920", 10000 },
94 { 0x17, "AMD Ryzen Threadripper 1910", 10000 },
97 static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
99 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
102 static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
103 unsigned int base, int offset, u32 *val)
105 mutex_lock(&nb_smu_ind_mutex);
106 pci_bus_write_config_dword(pdev->bus, devfn,
108 pci_bus_read_config_dword(pdev->bus, devfn,
110 mutex_unlock(&nb_smu_ind_mutex);
113 static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
115 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
116 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
119 static void read_tempreg_nb_f17(struct pci_dev *pdev, u32 *regval)
121 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0x60,
122 F17H_M01H_REPORTED_TEMP_CTRL_OFFSET, regval);
125 static ssize_t temp1_input_show(struct device *dev,
126 struct device_attribute *attr, char *buf)
128 struct k10temp_data *data = dev_get_drvdata(dev);
132 data->read_tempreg(data->pdev, ®val);
133 temp = (regval >> 21) * 125;
134 /* bit 20 indicates an additional temp offset of 49 degrees C */
135 if (regval & 0x80000)
137 if (temp > data->temp_offset)
138 temp -= data->temp_offset;
142 return sprintf(buf, "%u\n", temp);
145 static ssize_t temp1_max_show(struct device *dev,
146 struct device_attribute *attr, char *buf)
148 return sprintf(buf, "%d\n", 70 * 1000);
151 static ssize_t show_temp_crit(struct device *dev,
152 struct device_attribute *devattr, char *buf)
154 struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
155 struct k10temp_data *data = dev_get_drvdata(dev);
156 int show_hyst = attr->index;
160 pci_read_config_dword(data->pdev,
161 REG_HARDWARE_THERMAL_CONTROL, ®val);
162 value = ((regval >> 16) & 0x7f) * 500 + 52000;
164 value -= ((regval >> 24) & 0xf) * 500;
165 return sprintf(buf, "%d\n", value);
168 static DEVICE_ATTR_RO(temp1_input);
169 static DEVICE_ATTR_RO(temp1_max);
170 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp_crit, NULL, 0);
171 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_crit, NULL, 1);
173 static umode_t k10temp_is_visible(struct kobject *kobj,
174 struct attribute *attr, int index)
176 struct device *dev = container_of(kobj, struct device, kobj);
177 struct k10temp_data *data = dev_get_drvdata(dev);
178 struct pci_dev *pdev = data->pdev;
181 u32 reg_caps, reg_htc;
183 pci_read_config_dword(pdev, REG_NORTHBRIDGE_CAPABILITIES,
185 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL,
187 if (!(reg_caps & NB_CAP_HTC) || !(reg_htc & HTC_ENABLE))
193 static struct attribute *k10temp_attrs[] = {
194 &dev_attr_temp1_input.attr,
195 &dev_attr_temp1_max.attr,
196 &sensor_dev_attr_temp1_crit.dev_attr.attr,
197 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
201 static const struct attribute_group k10temp_group = {
202 .attrs = k10temp_attrs,
203 .is_visible = k10temp_is_visible,
205 __ATTRIBUTE_GROUPS(k10temp);
207 static bool has_erratum_319(struct pci_dev *pdev)
209 u32 pkg_type, reg_dram_cfg;
211 if (boot_cpu_data.x86 != 0x10)
215 * Erratum 319: The thermal sensor of Socket F/AM2+ processors
218 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
219 if (pkg_type == CPUID_PKGTYPE_F)
221 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
224 /* DDR3 memory implies socket AM3, which is good */
225 pci_bus_read_config_dword(pdev->bus,
226 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
227 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
228 if (reg_dram_cfg & DDR3_MODE)
232 * Unfortunately it is possible to run a socket AM3 CPU with DDR2
233 * memory. We blacklist all the cores which do exist in socket AM2+
234 * format. It still isn't perfect, as RB-C2 cores exist in both AM2+
235 * and AM3 formats, but that's the best we can do.
237 return boot_cpu_data.x86_model < 4 ||
238 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
241 static int k10temp_probe(struct pci_dev *pdev,
242 const struct pci_device_id *id)
244 int unreliable = has_erratum_319(pdev);
245 struct device *dev = &pdev->dev;
246 struct k10temp_data *data;
247 struct device *hwmon_dev;
253 "unreliable CPU thermal sensor; monitoring disabled\n");
257 "unreliable CPU thermal sensor; check erratum 319\n");
260 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
266 if (boot_cpu_data.x86 == 0x15 && (boot_cpu_data.x86_model == 0x60 ||
267 boot_cpu_data.x86_model == 0x70))
268 data->read_tempreg = read_tempreg_nb_f15;
269 else if (boot_cpu_data.x86 == 0x17)
270 data->read_tempreg = read_tempreg_nb_f17;
272 data->read_tempreg = read_tempreg_pci;
274 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
275 const struct tctl_offset *entry = &tctl_offset_table[i];
277 if (boot_cpu_data.x86 == entry->model &&
278 strstr(boot_cpu_data.x86_model_id, entry->id)) {
279 data->temp_offset = entry->offset;
284 hwmon_dev = devm_hwmon_device_register_with_groups(dev, "k10temp", data,
286 return PTR_ERR_OR_ZERO(hwmon_dev);
289 static const struct pci_device_id k10temp_id_table[] = {
290 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
291 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
292 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
293 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
294 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
295 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
296 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
297 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
298 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
299 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
302 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
304 static struct pci_driver k10temp_driver = {
306 .id_table = k10temp_id_table,
307 .probe = k10temp_probe,
310 module_pci_driver(k10temp_driver);