2 * (C) Copyright 2008-2009
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/ppc4xx.h>
11 #include <asm/processor.h>
14 * This code can configure those two Crucial SODIMM's:
16 * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
17 * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
21 #define TEST_ADDR 0x10000000
22 #define TEST_MAGIC 0x11223344
24 static void wait_init_complete(void)
29 mfsdram(SDRAM_MCSTAT, val);
30 } while (!(val & 0x80000000));
33 static void ddr_start(void)
35 mtsdram(SDRAM_MCOPT2, 0x28000000);
39 static void ddr_init_common(void)
42 * Reset the DDR-SDRAM controller.
44 mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
45 mtsdr(SDR0_SRST, 0x00000000);
48 * These values are cloned from a running NOR booting
49 * Canyonlands with SPD-DDR2 detection and calibration
50 * enabled. This will only work for the same memory
51 * configuration as used here:
54 mtsdram(SDRAM_MCOPT2, 0x00000000);
55 mtsdram(SDRAM_MODT0, 0x01000000);
56 mtsdram(SDRAM_WRDTR, 0x82000823);
57 mtsdram(SDRAM_CLKTR, 0x40000000);
58 mtsdram(SDRAM_MB0CF, 0x00000201);
59 mtsdram(SDRAM_RTR, 0x06180000);
60 mtsdram(SDRAM_SDTR1, 0x80201000);
61 mtsdram(SDRAM_SDTR2, 0x42103243);
62 mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
63 mtsdram(SDRAM_MMODE, 0x00000632);
64 mtsdram(SDRAM_MEMODE, 0x00000040);
65 mtsdram(SDRAM_INITPLR0, 0xB5380000);
66 mtsdram(SDRAM_INITPLR1, 0x82100400);
67 mtsdram(SDRAM_INITPLR2, 0x80820000);
68 mtsdram(SDRAM_INITPLR3, 0x80830000);
69 mtsdram(SDRAM_INITPLR4, 0x80810040);
70 mtsdram(SDRAM_INITPLR5, 0x80800532);
71 mtsdram(SDRAM_INITPLR6, 0x82100400);
72 mtsdram(SDRAM_INITPLR7, 0x8A080000);
73 mtsdram(SDRAM_INITPLR8, 0x8A080000);
74 mtsdram(SDRAM_INITPLR9, 0x8A080000);
75 mtsdram(SDRAM_INITPLR10, 0x8A080000);
76 mtsdram(SDRAM_INITPLR11, 0x80000432);
77 mtsdram(SDRAM_INITPLR12, 0x808103C0);
78 mtsdram(SDRAM_INITPLR13, 0x80810040);
79 mtsdram(SDRAM_RDCC, 0x40000000);
80 mtsdram(SDRAM_RQDC, 0x80000038);
81 mtsdram(SDRAM_RFDC, 0x00000257);
83 mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
86 phys_size_t initdram(int board_type)
89 * First try init for this module:
91 * Crucial CT6464AC667.8FB - 512MB SO-DIMM (dual rank)
97 * Crucial CT6464AC667.8FB - 512MB SO-DIMM
99 mtdcr(SDRAM_R0BAS, 0x0000F800);
100 mtdcr(SDRAM_R1BAS, 0x0400F800);
101 mtsdram(SDRAM_MCOPT1, 0x05122000);
102 mtsdram(SDRAM_CODT, 0x02800021);
103 mtsdram(SDRAM_MB1CF, 0x00000201);
108 * Now test if the dual-ranked module is really installed
109 * by checking an address in the upper 256MByte region
111 out_be32((void *)TEST_ADDR, TEST_MAGIC);
112 if (in_be32((void *)TEST_ADDR) != TEST_MAGIC) {
114 * The test failed, so we assume that the single
115 * ranked module is installed:
117 * Crucial CT6464AC667.4FE - 512MB SO-DIMM (single rank)
122 mtdcr(SDRAM_R0BAS, 0x0000F000);
123 mtsdram(SDRAM_MCOPT1, 0x05322000);
124 mtsdram(SDRAM_CODT, 0x00800021);
129 return CONFIG_SYS_MBYTES_SDRAM << 20;