2 * Copyright (c) 2010, CompuLab, Ltd.
3 * Author: Mike Rapoport <mike@compulab.co.il>
5 * Based on NVIDIA PCIe driver
6 * Copyright (c) 2008-2009, NVIDIA Corporation.
8 * Copyright (c) 2013-2014, NVIDIA Corporation.
10 * SPDX-License-Identifier: GPL-2.0
14 #define pr_fmt(fmt) "tegra-pcie: " fmt
25 #include <asm/arch/clock.h>
26 #include <asm/arch/powergate.h>
27 #include <asm/arch-tegra/xusb-padctl.h>
29 #include <linux/list.h>
31 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
33 DECLARE_GLOBAL_DATA_PTR;
35 #define AFI_AXI_BAR0_SZ 0x00
36 #define AFI_AXI_BAR1_SZ 0x04
37 #define AFI_AXI_BAR2_SZ 0x08
38 #define AFI_AXI_BAR3_SZ 0x0c
39 #define AFI_AXI_BAR4_SZ 0x10
40 #define AFI_AXI_BAR5_SZ 0x14
42 #define AFI_AXI_BAR0_START 0x18
43 #define AFI_AXI_BAR1_START 0x1c
44 #define AFI_AXI_BAR2_START 0x20
45 #define AFI_AXI_BAR3_START 0x24
46 #define AFI_AXI_BAR4_START 0x28
47 #define AFI_AXI_BAR5_START 0x2c
49 #define AFI_FPCI_BAR0 0x30
50 #define AFI_FPCI_BAR1 0x34
51 #define AFI_FPCI_BAR2 0x38
52 #define AFI_FPCI_BAR3 0x3c
53 #define AFI_FPCI_BAR4 0x40
54 #define AFI_FPCI_BAR5 0x44
56 #define AFI_CACHE_BAR0_SZ 0x48
57 #define AFI_CACHE_BAR0_ST 0x4c
58 #define AFI_CACHE_BAR1_SZ 0x50
59 #define AFI_CACHE_BAR1_ST 0x54
61 #define AFI_MSI_BAR_SZ 0x60
62 #define AFI_MSI_FPCI_BAR_ST 0x64
63 #define AFI_MSI_AXI_BAR_ST 0x68
65 #define AFI_CONFIGURATION 0xac
66 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
68 #define AFI_FPCI_ERROR_MASKS 0xb0
70 #define AFI_INTR_MASK 0xb4
71 #define AFI_INTR_MASK_INT_MASK (1 << 0)
72 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
74 #define AFI_SM_INTR_ENABLE 0xc4
75 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
76 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
77 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
78 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
79 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
80 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
81 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
82 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
84 #define AFI_AFI_INTR_ENABLE 0xc8
85 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
86 #define AFI_INTR_EN_INI_DECERR (1 << 1)
87 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
88 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
89 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
90 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
91 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
92 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
93 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
95 #define AFI_PCIE_CONFIG 0x0f8
96 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
97 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
98 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
99 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
100 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
101 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
102 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
103 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
104 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
105 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
107 #define AFI_FUSE 0x104
108 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
110 #define AFI_PEX0_CTRL 0x110
111 #define AFI_PEX1_CTRL 0x118
112 #define AFI_PEX2_CTRL 0x128
113 #define AFI_PEX_CTRL_RST (1 << 0)
114 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
115 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
116 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
118 #define AFI_PLLE_CONTROL 0x160
119 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
120 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
122 #define AFI_PEXBIAS_CTRL_0 0x168
124 #define PADS_CTL_SEL 0x0000009C
126 #define PADS_CTL 0x000000A0
127 #define PADS_CTL_IDDQ_1L (1 << 0)
128 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
129 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
131 #define PADS_PLL_CTL_TEGRA20 0x000000B8
132 #define PADS_PLL_CTL_TEGRA30 0x000000B4
133 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1)
134 #define PADS_PLL_CTL_LOCKDET (0x1 << 8)
135 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
136 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0x0 << 16)
137 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (0x1 << 16)
138 #define PADS_PLL_CTL_REFCLK_EXTERNAL (0x2 << 16)
139 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
140 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0x0 << 20)
141 #define PADS_PLL_CTL_TXCLKREF_DIV5 (0x1 << 20)
142 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (0x1 << 22)
144 #define PADS_REFCLK_CFG0 0x000000C8
145 #define PADS_REFCLK_CFG1 0x000000CC
148 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
149 * entries, one entry per PCIe port. These field definitions and desired
150 * values aren't in the TRM, but do come from NVIDIA.
152 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
153 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
154 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
155 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
157 /* Default value provided by HW engineering is 0xfa5c */
158 #define PADS_REFCLK_CFG_VALUE \
160 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
161 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
162 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
163 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
166 #define RP_VEND_XP 0x00000F00
167 #define RP_VEND_XP_DL_UP (1 << 30)
169 #define RP_PRIV_MISC 0x00000FE0
170 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
171 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
173 #define RP_LINK_CONTROL_STATUS 0x00000090
174 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
175 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
179 struct tegra_pcie_port {
180 struct tegra_pcie *pcie;
182 struct fdt_resource regs;
183 unsigned int num_lanes;
186 struct list_head list;
189 struct tegra_pcie_soc {
190 unsigned int num_ports;
191 unsigned long pads_pll_ctl;
192 unsigned long tx_ref_sel;
193 bool has_pex_clkreq_en;
194 bool has_pex_bias_ctrl;
200 struct pci_controller hose;
202 struct fdt_resource pads;
203 struct fdt_resource afi;
204 struct fdt_resource cs;
206 struct fdt_resource prefetch;
207 struct fdt_resource mem;
208 struct fdt_resource io;
210 struct list_head ports;
213 const struct tegra_pcie_soc *soc;
214 struct tegra_xusb_phy *phy;
217 static inline struct tegra_pcie *to_tegra_pcie(struct pci_controller *hose)
219 return container_of(hose, struct tegra_pcie, hose);
222 static void afi_writel(struct tegra_pcie *pcie, unsigned long value,
223 unsigned long offset)
225 writel(value, pcie->afi.start + offset);
228 static unsigned long afi_readl(struct tegra_pcie *pcie, unsigned long offset)
230 return readl(pcie->afi.start + offset);
233 static void pads_writel(struct tegra_pcie *pcie, unsigned long value,
234 unsigned long offset)
236 writel(value, pcie->pads.start + offset);
239 static unsigned long pads_readl(struct tegra_pcie *pcie, unsigned long offset)
241 return readl(pcie->pads.start + offset);
244 static unsigned long rp_readl(struct tegra_pcie_port *port,
245 unsigned long offset)
247 return readl(port->regs.start + offset);
250 static void rp_writel(struct tegra_pcie_port *port, unsigned long value,
251 unsigned long offset)
253 writel(value, port->regs.start + offset);
256 static unsigned long tegra_pcie_conf_offset(pci_dev_t bdf, int where)
258 return ((where & 0xf00) << 16) | (PCI_BUS(bdf) << 16) |
259 (PCI_DEV(bdf) << 11) | (PCI_FUNC(bdf) << 8) |
263 static int tegra_pcie_conf_address(struct tegra_pcie *pcie, pci_dev_t bdf,
264 int where, unsigned long *address)
266 unsigned int bus = PCI_BUS(bdf);
269 unsigned int dev = PCI_DEV(bdf);
270 struct tegra_pcie_port *port;
272 list_for_each_entry(port, &pcie->ports, list) {
273 if (port->index + 1 == dev) {
274 *address = port->regs.start + (where & ~3);
279 *address = pcie->cs.start + tegra_pcie_conf_offset(bdf, where);
286 static int tegra_pcie_read_conf(struct pci_controller *hose, pci_dev_t bdf,
287 int where, u32 *value)
289 struct tegra_pcie *pcie = to_tegra_pcie(hose);
290 unsigned long address;
293 err = tegra_pcie_conf_address(pcie, bdf, where, &address);
299 *value = readl(address);
301 /* fixup root port class */
302 if (PCI_BUS(bdf) == 0) {
303 if (where == PCI_CLASS_REVISION) {
304 *value &= ~0x00ff0000;
305 *value |= PCI_CLASS_BRIDGE_PCI << 16;
312 static int tegra_pcie_write_conf(struct pci_controller *hose, pci_dev_t bdf,
313 int where, u32 value)
315 struct tegra_pcie *pcie = to_tegra_pcie(hose);
316 unsigned long address;
319 err = tegra_pcie_conf_address(pcie, bdf, where, &address);
323 writel(value, address);
328 static int tegra_pcie_port_parse_dt(const void *fdt, int node,
329 struct tegra_pcie_port *port)
334 addr = fdt_getprop(fdt, node, "assigned-addresses", &len);
336 error("property \"assigned-addresses\" not found");
337 return -FDT_ERR_NOTFOUND;
340 port->regs.start = fdt32_to_cpu(addr[2]);
341 port->regs.end = port->regs.start + fdt32_to_cpu(addr[4]);
346 static int tegra_pcie_get_xbar_config(const void *fdt, int node, u32 lanes,
349 enum fdt_compat_id id = fdtdec_lookup(fdt, node);
352 case COMPAT_NVIDIA_TEGRA20_PCIE:
355 debug("single-mode configuration\n");
356 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
360 debug("dual-mode configuration\n");
361 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
366 case COMPAT_NVIDIA_TEGRA30_PCIE:
369 debug("4x1, 2x1 configuration\n");
370 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
374 debug("2x3 configuration\n");
375 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
379 debug("4x1, 1x2 configuration\n");
380 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
385 case COMPAT_NVIDIA_TEGRA124_PCIE:
388 debug("4x1, 1x1 configuration\n");
389 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
393 debug("2x1, 1x1 configuration\n");
394 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
403 return -FDT_ERR_NOTFOUND;
406 static int tegra_pcie_parse_dt_ranges(const void *fdt, int node,
407 struct tegra_pcie *pcie)
409 const u32 *ptr, *end;
412 ptr = fdt_getprop(fdt, node, "ranges", &len);
414 error("missing \"ranges\" property");
415 return -FDT_ERR_NOTFOUND;
421 struct fdt_resource *res = NULL;
422 u32 space = fdt32_to_cpu(*ptr);
424 switch ((space >> 24) & 0x3) {
429 case 0x02: /* 32 bit */
430 case 0x03: /* 64 bit */
431 if (space & (1 << 30))
432 res = &pcie->prefetch;
440 res->start = fdt32_to_cpu(ptr[3]);
441 res->end = res->start + fdt32_to_cpu(ptr[5]);
447 debug("PCI regions:\n");
448 debug(" I/O: %pa-%pa\n", &pcie->io.start, &pcie->io.end);
449 debug(" non-prefetchable memory: %pa-%pa\n", &pcie->mem.start,
451 debug(" prefetchable memory: %pa-%pa\n", &pcie->prefetch.start,
452 &pcie->prefetch.end);
457 static int tegra_pcie_parse_port_info(const void *fdt, int node,
461 struct fdt_pci_addr addr;
464 err = fdtdec_get_int(fdt, node, "nvidia,num-lanes", 0);
466 error("failed to parse \"nvidia,num-lanes\" property");
472 err = fdtdec_get_pci_addr(fdt, node, 0, "reg", &addr);
474 error("failed to parse \"reg\" property");
478 *index = PCI_DEV(addr.phys_hi) - 1;
483 static int tegra_pcie_parse_dt(const void *fdt, int node,
484 struct tegra_pcie *pcie)
489 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "pads",
492 error("resource \"pads\" not found");
496 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "afi",
499 error("resource \"afi\" not found");
503 err = fdt_get_named_resource(fdt, node, "reg", "reg-names", "cs",
506 error("resource \"cs\" not found");
510 pcie->phy = tegra_xusb_phy_get(TEGRA_XUSB_PADCTL_PCIE);
512 err = tegra_xusb_phy_prepare(pcie->phy);
514 error("failed to prepare PHY: %d", err);
519 err = tegra_pcie_parse_dt_ranges(fdt, node, pcie);
521 error("failed to parse \"ranges\" property");
525 fdt_for_each_subnode(fdt, subnode, node) {
526 unsigned int index = 0, num_lanes = 0;
527 struct tegra_pcie_port *port;
529 err = tegra_pcie_parse_port_info(fdt, subnode, &index,
532 error("failed to obtain root port info");
536 lanes |= num_lanes << (index << 3);
538 if (!fdtdec_get_is_enabled(fdt, subnode))
541 port = malloc(sizeof(*port));
545 memset(port, 0, sizeof(*port));
546 port->num_lanes = num_lanes;
549 err = tegra_pcie_port_parse_dt(fdt, subnode, port);
555 list_add_tail(&port->list, &pcie->ports);
559 err = tegra_pcie_get_xbar_config(fdt, node, lanes, &pcie->xbar);
561 error("invalid lane configuration");
568 int __weak tegra_pcie_board_init(void)
573 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
575 const struct tegra_pcie_soc *soc = pcie->soc;
579 /* reset PCIEXCLK logic, AFI controller and PCIe controller */
580 reset_set_enable(PERIPH_ID_PCIEXCLK, 1);
581 reset_set_enable(PERIPH_ID_AFI, 1);
582 reset_set_enable(PERIPH_ID_PCIE, 1);
584 err = tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
586 error("failed to power off PCIe partition: %d", err);
590 tegra_pcie_board_init();
592 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
595 error("failed to power up PCIe partition: %d", err);
599 /* take AFI controller out of reset */
600 reset_set_enable(PERIPH_ID_AFI, 0);
602 /* enable AFI clock */
603 clock_enable(PERIPH_ID_AFI);
605 if (soc->has_cml_clk) {
606 /* enable CML clock */
607 value = readl(NV_PA_CLK_RST_BASE + 0x48c);
610 writel(value, NV_PA_CLK_RST_BASE + 0x48c);
613 err = tegra_plle_enable();
615 error("failed to enable PLLE: %d\n", err);
622 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
624 const struct tegra_pcie_soc *soc = pcie->soc;
625 unsigned long start = get_timer(0);
628 while (get_timer(start) < timeout) {
629 value = pads_readl(pcie, soc->pads_pll_ctl);
630 if (value & PADS_PLL_CTL_LOCKDET)
637 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
639 const struct tegra_pcie_soc *soc = pcie->soc;
643 /* initialize internal PHY, enable up to 16 PCIe lanes */
644 pads_writel(pcie, 0, PADS_CTL_SEL);
646 /* override IDDQ to 1 on all 4 lanes */
647 value = pads_readl(pcie, PADS_CTL);
648 value |= PADS_CTL_IDDQ_1L;
649 pads_writel(pcie, value, PADS_CTL);
652 * Set up PHY PLL inputs select PLLE output as refclock, set TX
653 * ref sel to div10 (not div5).
655 value = pads_readl(pcie, soc->pads_pll_ctl);
656 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
657 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
658 pads_writel(pcie, value, soc->pads_pll_ctl);
661 value = pads_readl(pcie, soc->pads_pll_ctl);
662 value &= ~PADS_PLL_CTL_RST_B4SM;
663 pads_writel(pcie, value, soc->pads_pll_ctl);
667 /* take PLL out of reset */
668 value = pads_readl(pcie, soc->pads_pll_ctl);
669 value |= PADS_PLL_CTL_RST_B4SM;
670 pads_writel(pcie, value, soc->pads_pll_ctl);
672 /* configure the reference clock driver */
673 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
674 pads_writel(pcie, value, PADS_REFCLK_CFG0);
676 if (soc->num_ports > 2)
677 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
679 /* wait for the PLL to lock */
680 err = tegra_pcie_pll_wait(pcie, 500);
682 error("PLL failed to lock: %d", err);
686 /* turn off IDDQ override */
687 value = pads_readl(pcie, PADS_CTL);
688 value &= ~PADS_CTL_IDDQ_1L;
689 pads_writel(pcie, value, PADS_CTL);
691 /* enable TX/RX data */
692 value = pads_readl(pcie, PADS_CTL);
693 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
694 pads_writel(pcie, value, PADS_CTL);
699 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
701 const struct tegra_pcie_soc *soc = pcie->soc;
702 struct tegra_pcie_port *port;
707 value = afi_readl(pcie, AFI_PLLE_CONTROL);
708 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
709 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
710 afi_writel(pcie, value, AFI_PLLE_CONTROL);
713 if (soc->has_pex_bias_ctrl)
714 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
716 value = afi_readl(pcie, AFI_PCIE_CONFIG);
717 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
718 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar;
720 list_for_each_entry(port, &pcie->ports, list)
721 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
723 afi_writel(pcie, value, AFI_PCIE_CONFIG);
725 value = afi_readl(pcie, AFI_FUSE);
728 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
730 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
732 afi_writel(pcie, value, AFI_FUSE);
735 err = tegra_xusb_phy_enable(pcie->phy);
737 err = tegra_pcie_phy_enable(pcie);
740 error("failed to power on PHY: %d\n", err);
744 /* take the PCIEXCLK logic out of reset */
745 reset_set_enable(PERIPH_ID_PCIEXCLK, 0);
747 /* finally enable PCIe */
748 value = afi_readl(pcie, AFI_CONFIGURATION);
749 value |= AFI_CONFIGURATION_EN_FPCI;
750 afi_writel(pcie, value, AFI_CONFIGURATION);
752 /* disable all interrupts */
753 afi_writel(pcie, 0, AFI_AFI_INTR_ENABLE);
754 afi_writel(pcie, 0, AFI_SM_INTR_ENABLE);
755 afi_writel(pcie, 0, AFI_INTR_MASK);
756 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
761 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
763 unsigned long fpci, axi, size;
765 /* BAR 0: type 1 extended configuration space */
767 size = fdt_resource_size(&pcie->cs);
768 axi = pcie->cs.start;
770 afi_writel(pcie, axi, AFI_AXI_BAR0_START);
771 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
772 afi_writel(pcie, fpci, AFI_FPCI_BAR0);
774 /* BAR 1: downstream I/O */
776 size = fdt_resource_size(&pcie->io);
777 axi = pcie->io.start;
779 afi_writel(pcie, axi, AFI_AXI_BAR1_START);
780 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
781 afi_writel(pcie, fpci, AFI_FPCI_BAR1);
783 /* BAR 2: prefetchable memory */
784 fpci = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
785 size = fdt_resource_size(&pcie->prefetch);
786 axi = pcie->prefetch.start;
788 afi_writel(pcie, axi, AFI_AXI_BAR2_START);
789 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
790 afi_writel(pcie, fpci, AFI_FPCI_BAR2);
792 /* BAR 3: non-prefetchable memory */
793 fpci = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
794 size = fdt_resource_size(&pcie->mem);
795 axi = pcie->mem.start;
797 afi_writel(pcie, axi, AFI_AXI_BAR3_START);
798 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
799 afi_writel(pcie, fpci, AFI_FPCI_BAR3);
801 /* NULL out the remaining BARs as they are not used */
802 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
803 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
804 afi_writel(pcie, 0, AFI_FPCI_BAR4);
806 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
807 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
808 afi_writel(pcie, 0, AFI_FPCI_BAR5);
810 /* map all upstream transactions as uncached */
811 afi_writel(pcie, NV_PA_SDRAM_BASE, AFI_CACHE_BAR0_ST);
812 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
813 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
814 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
816 /* MSI translations are setup only when needed */
817 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
818 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
819 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
820 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
823 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
825 unsigned long ret = 0;
827 switch (port->index) {
844 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
846 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
849 /* pulse reset signel */
850 value = afi_readl(port->pcie, ctrl);
851 value &= ~AFI_PEX_CTRL_RST;
852 afi_writel(port->pcie, value, ctrl);
856 value = afi_readl(port->pcie, ctrl);
857 value |= AFI_PEX_CTRL_RST;
858 afi_writel(port->pcie, value, ctrl);
861 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
863 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
866 /* enable reference clock */
867 value = afi_readl(port->pcie, ctrl);
868 value |= AFI_PEX_CTRL_REFCLK_EN;
870 if (port->pcie->soc->has_pex_clkreq_en)
871 value |= AFI_PEX_CTRL_CLKREQ_EN;
873 value |= AFI_PEX_CTRL_OVERRIDE_EN;
875 afi_writel(port->pcie, value, ctrl);
877 tegra_pcie_port_reset(port);
880 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
882 unsigned int retries = 3;
885 value = rp_readl(port, RP_PRIV_MISC);
886 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
887 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
888 rp_writel(port, value, RP_PRIV_MISC);
891 unsigned int timeout = 200;
894 value = rp_readl(port, RP_VEND_XP);
895 if (value & RP_VEND_XP_DL_UP)
902 debug("link %u down, retrying\n", port->index);
909 value = rp_readl(port, RP_LINK_CONTROL_STATUS);
910 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
917 tegra_pcie_port_reset(port);
923 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
925 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
928 /* assert port reset */
929 value = afi_readl(port->pcie, ctrl);
930 value &= ~AFI_PEX_CTRL_RST;
931 afi_writel(port->pcie, value, ctrl);
933 /* disable reference clock */
934 value = afi_readl(port->pcie, ctrl);
935 value &= ~AFI_PEX_CTRL_REFCLK_EN;
936 afi_writel(port->pcie, value, ctrl);
939 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
941 list_del(&port->list);
945 static int tegra_pcie_enable(struct tegra_pcie *pcie)
947 struct tegra_pcie_port *port, *tmp;
949 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
950 debug("probing port %u, using %u lanes\n", port->index,
953 tegra_pcie_port_enable(port);
955 if (tegra_pcie_port_check_link(port))
958 debug("link %u down, ignoring\n", port->index);
960 tegra_pcie_port_disable(port);
961 tegra_pcie_port_free(port);
967 static const struct tegra_pcie_soc tegra20_pcie_soc = {
969 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
970 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
971 .has_pex_clkreq_en = false,
972 .has_pex_bias_ctrl = false,
973 .has_cml_clk = false,
977 static const struct tegra_pcie_soc tegra30_pcie_soc = {
979 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
980 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
981 .has_pex_clkreq_en = true,
982 .has_pex_bias_ctrl = true,
987 static const struct tegra_pcie_soc tegra124_pcie_soc = {
989 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
990 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
991 .has_pex_clkreq_en = true,
992 .has_pex_bias_ctrl = true,
997 static int process_nodes(const void *fdt, int nodes[], unsigned int count)
1001 for (i = 0; i < count; i++) {
1002 const struct tegra_pcie_soc *soc;
1003 struct tegra_pcie *pcie;
1004 enum fdt_compat_id id;
1007 if (!fdtdec_get_is_enabled(fdt, nodes[i]))
1010 id = fdtdec_lookup(fdt, nodes[i]);
1012 case COMPAT_NVIDIA_TEGRA20_PCIE:
1013 soc = &tegra20_pcie_soc;
1016 case COMPAT_NVIDIA_TEGRA30_PCIE:
1017 soc = &tegra30_pcie_soc;
1020 case COMPAT_NVIDIA_TEGRA124_PCIE:
1021 soc = &tegra124_pcie_soc;
1025 error("unsupported compatible: %s",
1026 fdtdec_get_compatible(id));
1030 pcie = malloc(sizeof(*pcie));
1032 error("failed to allocate controller");
1036 memset(pcie, 0, sizeof(*pcie));
1039 INIT_LIST_HEAD(&pcie->ports);
1041 err = tegra_pcie_parse_dt(fdt, nodes[i], pcie);
1047 err = tegra_pcie_power_on(pcie);
1049 error("failed to power on");
1053 err = tegra_pcie_enable_controller(pcie);
1055 error("failed to enable controller");
1059 tegra_pcie_setup_translations(pcie);
1061 err = tegra_pcie_enable(pcie);
1063 error("failed to enable PCIe");
1067 pcie->hose.first_busno = 0;
1068 pcie->hose.current_busno = 0;
1069 pcie->hose.last_busno = 0;
1071 pci_set_region(&pcie->hose.regions[0], NV_PA_SDRAM_BASE,
1072 NV_PA_SDRAM_BASE, gd->ram_size,
1073 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
1075 pci_set_region(&pcie->hose.regions[1], pcie->io.start,
1076 pcie->io.start, fdt_resource_size(&pcie->io),
1079 pci_set_region(&pcie->hose.regions[2], pcie->mem.start,
1080 pcie->mem.start, fdt_resource_size(&pcie->mem),
1083 pci_set_region(&pcie->hose.regions[3], pcie->prefetch.start,
1084 pcie->prefetch.start,
1085 fdt_resource_size(&pcie->prefetch),
1086 PCI_REGION_MEM | PCI_REGION_PREFETCH);
1088 pcie->hose.region_count = 4;
1090 pci_set_ops(&pcie->hose,
1091 pci_hose_read_config_byte_via_dword,
1092 pci_hose_read_config_word_via_dword,
1093 tegra_pcie_read_conf,
1094 pci_hose_write_config_byte_via_dword,
1095 pci_hose_write_config_word_via_dword,
1096 tegra_pcie_write_conf);
1098 pci_register_hose(&pcie->hose);
1100 #ifdef CONFIG_PCI_SCAN_SHOW
1101 printf("PCI: Enumerating devices...\n");
1102 printf("---------------------------------------\n");
1103 printf(" Device ID Description\n");
1104 printf(" ------ -- -----------\n");
1107 pcie->hose.last_busno = pci_hose_scan(&pcie->hose);
1113 void pci_init_board(void)
1115 const void *fdt = gd->fdt_blob;
1116 int count, nodes[1];
1118 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
1119 COMPAT_NVIDIA_TEGRA124_PCIE,
1120 nodes, ARRAY_SIZE(nodes));
1121 if (process_nodes(fdt, nodes, count))
1124 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
1125 COMPAT_NVIDIA_TEGRA30_PCIE,
1126 nodes, ARRAY_SIZE(nodes));
1127 if (process_nodes(fdt, nodes, count))
1130 count = fdtdec_find_aliases_for_id(fdt, "pcie-controller",
1131 COMPAT_NVIDIA_TEGRA20_PCIE,
1132 nodes, ARRAY_SIZE(nodes));
1133 if (process_nodes(fdt, nodes, count))
1137 int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
1139 if (PCI_BUS(dev) != 0 && PCI_DEV(dev) > 0)