2 * (C) Copyright 2009, 2010 Wolfgang Denk <wd@denx.de>
4 * (C) Copyright 2009-2010
5 * Michael Weiß, ifm ecomatic gmbh, michael.weiss@ifm.com
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/bitops.h>
31 #include <asm/processor.h>
32 #include <asm/mpc512x.h>
33 #include <fdt_support.h>
35 #ifdef CONFIG_MISC_INIT_R
39 #include <jffs2/load_kernel.h>
42 DECLARE_GLOBAL_DATA_PTR;
44 extern flash_info_t flash_info[];
45 ulong flash_get_size (phys_addr_t base, int banknum);
47 sdram_conf_t mddrc_config[] = {
49 (512 << 20), /* 512 MB RAM configuration */
51 CONFIG_SYS_MDDRC_SYS_CFG,
52 CONFIG_SYS_MDDRC_TIME_CFG0,
53 CONFIG_SYS_MDDRC_TIME_CFG1,
54 CONFIG_SYS_MDDRC_TIME_CFG2
58 (128 << 20), /* 128 MB RAM configuration */
60 CONFIG_SYS_MDDRC_SYS_CFG_ALT1,
61 CONFIG_SYS_MDDRC_TIME_CFG0_ALT1,
62 CONFIG_SYS_MDDRC_TIME_CFG1_ALT1,
63 CONFIG_SYS_MDDRC_TIME_CFG2_ALT1
68 phys_size_t initdram (int board_type)
72 u32 pdm360ng_init_seq[] = {
73 CONFIG_SYS_DDRCMD_NOP,
74 CONFIG_SYS_DDRCMD_NOP,
75 CONFIG_SYS_DDRCMD_NOP,
76 CONFIG_SYS_DDRCMD_NOP,
77 CONFIG_SYS_DDRCMD_NOP,
78 CONFIG_SYS_DDRCMD_NOP,
79 CONFIG_SYS_DDRCMD_NOP,
80 CONFIG_SYS_DDRCMD_NOP,
81 CONFIG_SYS_DDRCMD_NOP,
82 CONFIG_SYS_DDRCMD_NOP,
83 CONFIG_SYS_DDRCMD_PCHG_ALL,
84 CONFIG_SYS_DDRCMD_NOP,
85 CONFIG_SYS_DDRCMD_RFSH,
86 CONFIG_SYS_DDRCMD_NOP,
87 CONFIG_SYS_DDRCMD_RFSH,
88 CONFIG_SYS_DDRCMD_NOP,
89 CONFIG_SYS_MICRON_INIT_DEV_OP,
90 CONFIG_SYS_DDRCMD_NOP,
91 CONFIG_SYS_DDRCMD_EM2,
92 CONFIG_SYS_DDRCMD_NOP,
93 CONFIG_SYS_DDRCMD_PCHG_ALL,
94 CONFIG_SYS_DDRCMD_EM2,
95 CONFIG_SYS_DDRCMD_EM3,
96 CONFIG_SYS_DDRCMD_EN_DLL,
97 CONFIG_SYS_DDRCMD_RES_DLL,
98 CONFIG_SYS_DDRCMD_PCHG_ALL,
99 CONFIG_SYS_DDRCMD_RFSH,
100 CONFIG_SYS_DDRCMD_RFSH,
101 CONFIG_SYS_MICRON_INIT_DEV_OP,
102 CONFIG_SYS_DDRCMD_OCD_DEFAULT,
103 CONFIG_SYS_DDRCMD_OCD_EXIT,
104 CONFIG_SYS_DDRCMD_PCHG_ALL,
105 CONFIG_SYS_DDRCMD_NOP
108 for (i = 0; i < ARRAY_SIZE(mddrc_config); i++) {
109 msize = fixed_sdram(&mddrc_config[i].cfg, pdm360ng_init_seq,
110 ARRAY_SIZE(pdm360ng_init_seq));
111 if (msize == mddrc_config[i].size)
118 static int set_lcd_brightness(char *);
120 int misc_init_r(void)
122 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
125 * Re-configure flash setup using auto-detected info
127 if (flash_info[1].size > 0) {
128 out_be32(&im->sysconf.lpcs1aw,
129 CSAW_START(gd->bd->bi_flashstart + flash_info[1].size) |
130 CSAW_STOP(gd->bd->bi_flashstart + flash_info[1].size,
131 flash_info[1].size));
132 sync_law(&im->sysconf.lpcs1aw);
134 * Re-check to get correct base address
136 flash_get_size (gd->bd->bi_flashstart + flash_info[1].size, 1);
139 out_be32(&im->sysconf.lpcs1aw, 0x01000100);
140 sync_law(&im->sysconf.lpcs1aw);
143 out_be32(&im->sysconf.lpcs0aw,
144 CSAW_START(gd->bd->bi_flashstart) |
145 CSAW_STOP(gd->bd->bi_flashstart, flash_info[0].size));
146 sync_law(&im->sysconf.lpcs0aw);
149 * Re-check to get correct base address
151 flash_get_size (gd->bd->bi_flashstart, 0);
154 * Re-do flash protection upon new addresses
156 flash_protect (FLAG_PROTECT_CLEAR,
157 gd->bd->bi_flashstart, 0xffffffff,
160 /* Monitor protection ON by default */
161 flash_protect (FLAG_PROTECT_SET,
162 CONFIG_SYS_MONITOR_BASE,
163 CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
166 /* Environment protection ON by default */
167 flash_protect (FLAG_PROTECT_SET,
169 CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
172 #ifdef CONFIG_ENV_ADDR_REDUND
173 /* Redundant environment protection ON by default */
174 flash_protect (FLAG_PROTECT_SET,
175 CONFIG_ENV_ADDR_REDUND,
176 CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
180 #ifdef CONFIG_FSL_DIU_FB
181 set_lcd_brightness(0);
182 /* Switch LCD-Backlight and LVDS-Interface on */
183 setbits_be32(&im->gpio.gpdir, 0x01040000);
184 clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
187 #if defined(CONFIG_HARD_I2C)
188 if (!getenv("ethaddr")) {
190 uchar ifm_oui[3] = { 0, 2, 1, };
193 /* I2C-0 for on-board eeprom */
194 i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS_NUM);
196 /* Read ethaddr from EEPROM */
197 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR,
198 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET, 1, buf, 6);
200 printf("Error: Unable to read MAC from I2C"
201 " EEPROM at address %02X:%02X\n",
202 CONFIG_SYS_I2C_EEPROM_ADDR,
203 CONFIG_SYS_I2C_EEPROM_MAC_OFFSET);
208 if (memcmp(buf, ifm_oui, sizeof(ifm_oui))) {
209 printf("Illegal MAC address in EEPROM: %pM\n", buf);
213 eth_setenv_enetaddr("ethaddr", buf);
215 #endif /* defined(CONFIG_HARD_I2C) */
220 static iopin_t ioregs_init[] = {
223 offsetof(struct ioctrl512x, io_control_pata_ce1), 1, 0,
224 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
225 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(3)
229 offsetof(struct ioctrl512x, io_control_pata_ce2), 1, 0,
230 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
231 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
235 offsetof(struct ioctrl512x, io_control_pata_isolate), 1, 0,
236 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
237 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
241 offsetof(struct ioctrl512x, io_control_pata_iochrdy), 1, 0,
242 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
243 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
245 /* FUNC2=DIU_LD22 Sets Next 2 to DIU_LD pads */
246 /* DIU_LD22-DIU_LD23 */
248 offsetof(struct ioctrl512x, io_control_pci_ad31), 2, 0,
249 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
250 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
252 /* FUNC2=USB1_DATA7 Sets Next 12 to USB1 pads */
253 /* USB1_DATA7-USB1_DATA0, USB1_STOP, USB1_NEXT, USB1_CLK, USB1_DIR */
255 offsetof(struct ioctrl512x, io_control_pci_ad29), 12, 0,
256 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
257 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
259 /* FUNC1=VIU_DATA0 Sets Next 3 to VIU_DATA pads */
260 /* VIU_DATA0-VIU_DATA2 */
262 offsetof(struct ioctrl512x, io_control_pci_ad17), 3, 0,
263 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
264 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
266 /* FUNC2=FEC_TXD_0 */
268 offsetof(struct ioctrl512x, io_control_pci_ad14), 1, 0,
269 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
270 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
272 /* FUNC1=VIU_DATA3 Sets Next 2 to VIU_DATA pads */
273 /* VIU_DATA3, VIU_DATA4 */
275 offsetof(struct ioctrl512x, io_control_pci_ad13), 2, 0,
276 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
277 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
279 /* FUNC2=FEC_RXD_1 Sets Next 12 to FEC pads */
280 /* FEC_RXD_1, FEC_RXD_0, FEC_RX_CLK, FEC_TX_CLK, FEC_RX_ER, FEC_RX_DV */
281 /* FEC_TX_EN, FEC_TX_ER, FEC_CRS, FEC_MDC, FEC_MDIO, FEC_COL */
283 offsetof(struct ioctrl512x, io_control_pci_ad11), 12, 0,
284 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
285 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
287 /* FUNC2=DIU_LD03 Sets Next 25 to DIU pads */
288 /* DIU_LD00-DIU_LD21 */
290 offsetof(struct ioctrl512x, io_control_pci_cbe0), 22, 0,
291 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
292 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(1)
294 /* FUNC2=DIU_CLK Sets Next 3 to DIU pads */
295 /* DIU_CLK, DIU_VSYNC, DIU_HSYNC */
297 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
298 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
299 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
303 offsetof(struct ioctrl512x, io_control_irq1), 1, 0,
304 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
305 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
307 /* Sets lowest slew on 2 CAN_TX Pins*/
309 offsetof(struct ioctrl512x, io_control_can1_tx), 2, 0,
310 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
311 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
313 /* FUNC3=CAN4_TX Sets Next 2 to CAN4 pads */
314 /* CAN4_TX, CAN4_RX */
316 offsetof(struct ioctrl512x, io_control_j1850_tx), 2, 0,
317 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
318 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
320 /* FUNC3=GPIO8 Sets Next 2 to GPIO pads */
323 offsetof(struct ioctrl512x, io_control_psc0_0), 2, 0,
324 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
325 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
327 /* FUNC1=FEC_TXD_1 Sets Next 3 to FEC pads */
328 /* FEC_TXD_1, FEC_TXD_2, FEC_TXD_3 */
330 offsetof(struct ioctrl512x, io_control_psc0_4), 3, 0,
331 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
332 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
334 /* FUNC1=FEC_RXD_3 Sets Next 2 to FEC pads */
335 /* FEC_RXD_3, FEC_RXD_2 */
337 offsetof(struct ioctrl512x, io_control_psc1_4), 2, 0,
338 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
339 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
343 offsetof(struct ioctrl512x, io_control_psc2_1), 1, 0,
344 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
345 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
347 /* FUNC3=GPIO2/GPT2 Sets Next 3 to GPIO pads */
348 /* GPIO2, GPIO20, GPIO21 */
350 offsetof(struct ioctrl512x, io_control_psc2_4), 3, 0,
351 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
352 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
354 /* FUNC2=VIU_PIX_CLK */
356 offsetof(struct ioctrl512x, io_control_psc3_4), 1, 0,
357 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
358 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
360 /* FUNC3=GPIO24 Sets Next 2 to GPIO pads */
363 offsetof(struct ioctrl512x, io_control_psc4_0), 2, 0,
364 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
365 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
369 offsetof(struct ioctrl512x, io_control_psc4_4), 1, 0,
370 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(1) |
371 IO_PIN_PUE(1) | IO_PIN_ST(0) | IO_PIN_DS(0)
373 /* FUNC2=VIU_DATA5 Sets Next 5 to VIU_DATA pads */
374 /* VIU_DATA5-VIU_DATA9 */
376 offsetof(struct ioctrl512x, io_control_psc5_0), 5, 0,
377 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
378 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
380 /* FUNC1=LPC_TSIZ1 Sets Next 2 to LPC_TSIZ pads */
381 /* LPC_TSIZ1-LPC_TSIZ2 */
383 offsetof(struct ioctrl512x, io_control_psc6_0), 2, 0,
384 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
385 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
389 offsetof(struct ioctrl512x, io_control_psc6_4), 1, 0,
390 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
391 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
395 offsetof(struct ioctrl512x, io_control_psc7_0), 1, 0,
396 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
397 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
399 /* FUNC3=GPIO18 Sets Next 3 to GPIO pads */
400 /* GPIO18-GPIO19, GPT7/GPIO7 */
402 offsetof(struct ioctrl512x, io_control_psc7_2), 3, 0,
403 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
404 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
406 /* FUNC3=GPIO0/GPT0 */
408 offsetof(struct ioctrl512x, io_control_psc8_4), 1, 0,
409 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
410 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
412 /* FUNC3=GPIO11 Sets Next 4 to GPIO pads */
413 /* GPIO11, GPIO2, GPIO12, GPIO13 */
415 offsetof(struct ioctrl512x, io_control_psc10_3), 4, 0,
416 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
417 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(0)
421 offsetof(struct ioctrl512x, io_control_psc11_4), 1, 0,
422 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
423 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
427 int checkboard (void)
429 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
431 puts("Board: PDM360NG\n");
433 /* initialize function mux & slew rate IO inter alia on IO Pins */
435 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
437 /* initialize IO_CONTROL_GP (GPIO/GPT-mux-register) */
438 setbits_be32(&im->io_ctrl.io_control_gp,
439 (1 << 0) | /* GP_MUX7->GPIO7 */
440 (1 << 5)); /* GP_MUX2->GPIO2 */
442 /* configure GPIO24 (VIU_CE), output/high */
443 setbits_be32(&im->gpio.gpdir, 0x80);
444 setbits_be32(&im->gpio.gpdat, 0x80);
449 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
450 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
451 struct node_info nodes[] = {
452 { "fsl,mpc5121-nfc", MTD_DEV_TYPE_NAND, },
453 { "cfi-flash", MTD_DEV_TYPE_NOR, },
457 #if defined(CONFIG_VIDEO)
459 * EDID block has been generated using Phoenix EDID Designer 1.3.
460 * This tool creates a text file containing:
463 * 0x 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
464 * ------------------------------------------------
465 * 00 | 00 FF FF FF FF FF FF 00 42 C9 34 12 01 00 00 00
466 * 10 | 0A 0C 01 03 80 98 5B 78 CA 7E 50 A0 58 4E 96 25
467 * 20 | 1E 50 54 00 00 00 01 01 01 01 01 01 01 01 01 01
468 * 30 | 01 01 01 01 01 01 80 0C 20 00 31 E0 2D 10 2A 80
469 * 40 | 12 08 30 E4 10 00 00 18 00 00 00 FD 00 38 3C 1F
470 * 50 | 3C 04 0A 20 20 20 20 20 20 20 00 00 00 FF 00 50
471 * 60 | 4D 30 37 30 57 4C 33 0A 0A 0A 0A 0A 00 00 00 FF
472 * 70 | 00 41 30 30 30 30 30 30 30 30 30 30 30 31 00 D4
474 * Then this data has been manually converted to the char
477 static unsigned char edid_buf[128] = {
478 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
479 0x42, 0xC9, 0x34, 0x12, 0x01, 0x00, 0x00, 0x00,
480 0x0A, 0x0C, 0x01, 0x03, 0x80, 0x98, 0x5B, 0x78,
481 0xCA, 0x7E, 0x50, 0xA0, 0x58, 0x4E, 0x96, 0x25,
482 0x1E, 0x50, 0x54, 0x00, 0x00, 0x00, 0x01, 0x01,
483 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
484 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x80, 0x0C,
485 0x20, 0x00, 0x31, 0xE0, 0x2D, 0x10, 0x2A, 0x80,
486 0x12, 0x08, 0x30, 0xE4, 0x10, 0x00, 0x00, 0x18,
487 0x00, 0x00, 0x00, 0xFD, 0x00, 0x38, 0x3C, 0x1F,
488 0x3C, 0x04, 0x0A, 0x20, 0x20, 0x20, 0x20, 0x20,
489 0x20, 0x20, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x50,
490 0x4D, 0x30, 0x37, 0x30, 0x57, 0x4C, 0x33, 0x0A,
491 0x0A, 0x0A, 0x0A, 0x0A, 0x00, 0x00, 0x00, 0xFF,
492 0x00, 0x41, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30,
493 0x30, 0x30, 0x30, 0x30, 0x30, 0x31, 0x00, 0xD4,
497 void ft_board_setup(void *blob, bd_t *bd)
502 ft_cpu_setup(blob, bd);
503 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
504 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
506 #if defined(CONFIG_VIDEO)
507 fdt_add_edid(blob, "fsl,mpc5121-diu", edid_buf);
510 /* Fixup NOR FLASH mapping */
511 val[i++] = 0; /* chip select number */
512 val[i++] = 0; /* always 0 */
513 val[i++] = gd->bd->bi_flashstart;
514 val[i++] = gd->bd->bi_flashsize;
516 /* Fixup MRAM mapping */
517 val[i++] = 2; /* chip select number */
518 val[i++] = 0; /* always 0 */
519 val[i++] = CONFIG_SYS_MRAM_BASE;
520 val[i++] = CONFIG_SYS_MRAM_SIZE;
522 rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
523 val, i * sizeof(u32), 1);
525 printf("Unable to update localbus ranges, err=%s\n",
528 /* Fixup reg property in NOR Flash node */
530 val[i++] = 0; /* always 0 */
531 val[i++] = 0; /* start at offset 0 */
532 val[i++] = flash_info[0].size; /* size of Bank 0 */
534 /* Second Bank available? */
535 if (flash_info[1].size > 0) {
536 val[i++] = 0; /* always 0 */
537 val[i++] = flash_info[0].size; /* offset of Bank 1 */
538 val[i++] = flash_info[1].size; /* size of Bank 1 */
541 rc = fdt_find_and_setprop(blob, "/localbus/flash", "reg",
542 val, i * sizeof(u32), 1);
544 printf("Unable to update flash reg property, err=%s\n",
547 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
550 * If argument is NULL, set the LCD brightness to the
551 * value from "brightness" environment variable. Set
552 * the LCD brightness to the value specified by the
553 * argument otherwise. Default brightness is zero.
555 #define MAX_BRIGHTNESS 99
556 static int set_lcd_brightness(char *brightness)
558 struct stdio_dev *cop_port;
566 val = simple_strtol(brightness, NULL, 10);
568 env = getenv("brightness");
570 val = simple_strtol(env, NULL, 10);
576 if (val > MAX_BRIGHTNESS)
577 val = MAX_BRIGHTNESS;
579 sprintf(cmd_buf, "$SB;%04d;", val);
581 len = strlen(cmd_buf);
582 for (i = 1; i <= len; i++)
585 cs = (~cs + 1) & 0xff;
586 sprintf(cmd_buf + len, "%02X\n", cs);
588 /* IO Coprocessor communication */
589 cop_port = open_port(4, CONFIG_SYS_PDM360NG_COPROC_BAUDRATE);
591 printf("Error: Can't open IO Coprocessor port.\n");
595 debug("%s: cmd: %s", __func__, cmd_buf);
596 write_port(cop_port, cmd_buf);
598 * Wait for transmission and maybe response data
599 * before closing the port.
601 udelay(CONFIG_SYS_PDM360NG_COPROC_READ_DELAY);
602 memset(cmd_buf, 0, sizeof(cmd_buf));
603 len = read_port(cop_port, cmd_buf, sizeof(cmd_buf));
605 printf("Error: %s\n", cmd_buf);
612 static int cmd_lcd_brightness(cmd_tbl_t *cmdtp, int flag,
613 int argc, char * const argv[])
616 return cmd_usage(cmdtp);
618 return set_lcd_brightness(argv[1]);
621 U_BOOT_CMD(lcdbr, 2, 1, cmd_lcd_brightness,
622 "set LCD brightness",
623 "<brightness> - set LCD backlight level to <brightness>.\n"