3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Author: Igor Lisitsin <igor@emcraft.com>
7 * See file CREDITS for list of people who contributed to this
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
31 * The Ethernet Media Access Controllers (EMAC) are tested in the
32 * internal loopback mode.
33 * The controllers are configured accordingly and several packets
34 * are transmitted. The configurable test parameters are:
35 * MIN_PACKET_LENGTH - minimum size of packet to transmit
36 * MAX_PACKET_LENGTH - maximum size of packet to transmit
37 * TEST_NUM - number of tests
44 #if CONFIG_POST & CFG_POST_ETHER
46 #include <asm/cache.h>
48 #include <asm/processor.h>
50 #include <ppc4xx_enet.h>
53 DECLARE_GLOBAL_DATA_PTR;
55 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
56 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
59 #define MIN_PACKET_LENGTH 64
60 #define MAX_PACKET_LENGTH 256
63 static volatile mal_desc_t tx __cacheline_aligned;
64 static volatile mal_desc_t rx __cacheline_aligned;
68 static void ether_post_init (int devnum, int hw_addr)
72 #if defined(CONFIG_440GX) || \
73 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
74 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
77 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE)
81 #if defined(CONFIG_440GX) || \
82 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
83 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
84 /* Need to get the OPB frequency so we can access the PHY */
85 get_sys_info (&sysinfo);
88 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
89 /* provide clocks for EMAC internal loopback */
91 mfr |= SDR0_MFR_ETH_CLK_SEL_V(devnum);
96 out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
100 if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
103 printf ("Timeout resetting EMAC\n");
108 #if defined(CONFIG_440GX) || \
109 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
110 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
111 /* Whack the M1 register */
113 if (sysinfo.freqOPB <= 50000000);
114 else if (sysinfo.freqOPB <= 66666667)
115 mode_reg |= EMAC_M1_OBCI_66;
116 else if (sysinfo.freqOPB <= 83333333)
117 mode_reg |= EMAC_M1_OBCI_83;
118 else if (sysinfo.freqOPB <= 100000000)
119 mode_reg |= EMAC_M1_OBCI_100;
121 mode_reg |= EMAC_M1_OBCI_GT100;
123 out32 (EMAC_M1 + hw_addr, mode_reg);
125 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
127 /* set the Mal configuration reg */
128 #if defined(CONFIG_440GX) || \
129 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
130 defined(CONFIG_440SP) || defined(CONFIG_440SPE)
131 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
132 MAL_CR_PLBLT_DEFAULT | 0x00330000);
134 mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
135 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
136 if (get_pvr() == PVR_440GP_RB) {
137 mtdcr (malmcr, mfdcr(malmcr) & ~MAL_CR_PLBB);
140 /* setup buffer descriptors */
141 tx.ctrl = MAL_TX_CTRL_WRAP;
143 tx.data_ptr = (char*)L1_CACHE_ALIGN((u32)tx_buf);
145 rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
147 rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
151 /* setup MAL tx & rx channel pointers */
152 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
153 mtdcr (maltxctp2r, &tx);
155 mtdcr (maltxctp1r, &tx);
157 #if defined(CONFIG_440)
158 mtdcr (maltxbattr, 0x0);
159 mtdcr (malrxbattr, 0x0);
161 mtdcr (malrxctp1r, &rx);
162 /* set RX buffer size */
163 mtdcr (malrcbs1, PKTSIZE_ALIGN / 16);
167 /* setup MAL tx & rx channel pointers */
168 #if defined(CONFIG_440)
169 mtdcr (maltxbattr, 0x0);
170 mtdcr (malrxbattr, 0x0);
172 mtdcr (maltxctp0r, &tx);
173 mtdcr (malrxctp0r, &rx);
174 /* set RX buffer size */
175 mtdcr (malrcbs0, PKTSIZE_ALIGN / 16);
179 /* Enable MAL transmit and receive channels */
180 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
181 mtdcr (maltxcasr, (MAL_TXRX_CASR >> (devnum*2)));
183 mtdcr (maltxcasr, (MAL_TXRX_CASR >> devnum));
185 mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
187 /* set internal loopback mode */
188 out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
189 EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
190 EMAC_M1_MF_100MBPS | EMAC_M1_IST |
193 /* set transmit enable & receive enable */
194 out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
196 /* enable broadcast address */
197 out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
199 /* set transmit request threshold register */
200 out32 (EMAC_TRTR + hw_addr, 0x18000000); /* 256 byte threshold */
202 /* set receive low/high water mark register */
203 #if defined(CONFIG_440)
204 /* 440s has a 64 byte burst length */
205 out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
207 /* 405s have a 16 byte burst length */
208 out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
209 #endif /* defined(CONFIG_440) */
210 out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
212 /* Set fifo limit entry in tx mode 0 */
213 out32 (EMAC_TXM0 + hw_addr, 0x00000003);
215 out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
219 static void ether_post_halt (int devnum, int hw_addr)
222 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
226 /* 1st reset MAL channel */
227 /* Note: writing a 0 to a channel has no effect */
228 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
229 mtdcr (maltxcarr, MAL_TXRX_CASR >> (devnum * 2));
231 mtdcr (maltxcarr, MAL_TXRX_CASR >> devnum);
233 mtdcr (malrxcarr, MAL_TXRX_CASR >> devnum);
236 while (mfdcr (malrxcasr) & (MAL_TXRX_CASR >> devnum)) {
242 out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
244 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
245 /* remove clocks for EMAC internal loopback */
246 mfsdr (sdr_mfr, mfr);
247 mfr &= ~SDR0_MFR_ETH_CLK_SEL_V(devnum);
248 mtsdr (sdr_mfr, mfr);
252 static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
256 while (tx.ctrl & MAL_TX_CTRL_READY) {
258 printf ("TX timeout\n");
263 tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
264 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
265 tx.data_len = length;
266 memcpy (tx.data_ptr, packet, length);
269 out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
273 static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_length)
278 while (rx.ctrl & MAL_RX_CTRL_EMPTY) {
280 printf ("RX timeout\n");
285 length = rx.data_len - 4;
286 if (length <= max_length)
287 memcpy(packet, rx.data_ptr, length);
290 rx.ctrl |= MAL_RX_CTRL_EMPTY;
300 static void packet_fill (char *packet, int length)
302 char c = (char) length;
305 /* set up ethernet header */
306 memset (packet, 0xff, 14);
308 for (i = 14; i < length; i++) {
313 static int packet_check (char *packet, int length)
315 char c = (char) length;
318 for (i = 14; i < length; i++) {
319 if (packet[i] != c++)
326 static int test_ctlr (int devnum, int hw_addr)
329 char packet_send[MAX_PACKET_LENGTH];
330 char packet_recv[MAX_PACKET_LENGTH];
335 ether_post_init (devnum, hw_addr);
337 for (i = 0; i < TEST_NUM; i++) {
338 for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) {
339 packet_fill (packet_send, l);
341 ether_post_send (devnum, hw_addr, packet_send, l);
343 length = ether_post_recv (devnum, hw_addr, packet_recv,
344 sizeof (packet_recv));
346 if (length != l || packet_check (packet_recv, length) < 0) {
356 ether_post_halt (devnum, hw_addr);
359 post_log ("EMAC%d test failed\n", devnum);
365 int ether_post_test (int flags)
369 /* Allocate tx & rx packet buffers */
370 tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
371 rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
373 if (!tx_buf || !rx_buf) {
374 printf ("Failed to allocate packet buffers\n");
380 if (test_ctlr (0, 0))
384 if (test_ctlr (1, 0x100))
394 #endif /* CONFIG_POST & CFG_POST_ETHER */
395 #endif /* CONFIG_POST */