1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * Load instructions: lbz(x)(u), lhz(x)(u), lha(x)(u), lwz(x)(u)
13 * All operations are performed on a 16-byte array. The array
14 * is 4-byte aligned. The base register points to offset 8.
15 * The immediate offset (index register) ranges in [-8 ... +7].
16 * The test cases are composed so that they do not
17 * cause alignment exceptions.
18 * The test contains a pre-built table describing all test cases.
19 * The table entry contains:
20 * the instruction opcode, the array contents, the value of the index
21 * register and the expected value of the destination register.
22 * After executing the instruction, the test verifies the
23 * value of the destination register and the value of the base
24 * register (it must change for "load with update" instructions).
30 #if CONFIG_POST & CONFIG_SYS_POST_CPU
32 extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3);
33 extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2);
35 static struct cpu_post_load_s
42 } cpu_post_load_table[] =
157 static unsigned int cpu_post_load_size = ARRAY_SIZE(cpu_post_load_table);
159 int cpu_post_test_load (void)
163 int flag = disable_interrupts();
165 for (i = 0; i < cpu_post_load_size && ret == 0; i++)
167 struct cpu_post_load_s *test = cpu_post_load_table + i;
169 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
170 ulong base0 = (ulong) (data + 8);
178 ASM_12(test->cmd, 5, 3, 4),
182 cpu_post_exec_22w (code, &base, test->offset, &value);
188 ASM_11I(test->cmd, 4, 3, test->offset),
192 cpu_post_exec_21w (code, &base, &value);
198 ret = base == base0 + test->offset ? 0 : -1;
200 ret = base == base0 ? 0 : -1;
208 ret = *(uchar *)(base0 + test->offset) == value ?
212 ret = *(ushort *)(base0 + test->offset) == value ?
216 ret = *(short *)(base0 + test->offset) == value ?
220 ret = *(ulong *)(base0 + test->offset) == value ?
228 post_log ("Error at load test %d !\n", i);