1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * Shift instructions: rlwimi
13 * The test contains a pre-built table of instructions, operands and
14 * expected results. For each table entry, the test will cyclically use
15 * different sets of operand registers and result registers.
21 #if CONFIG_POST & CONFIG_SYS_POST_CPU
23 extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
25 extern ulong cpu_post_makecr (long v);
27 static struct cpu_post_rlwimi_s
36 } cpu_post_rlwimi_table[] =
48 static unsigned int cpu_post_rlwimi_size = ARRAY_SIZE(cpu_post_rlwimi_table);
50 int cpu_post_test_rlwimi (void)
54 int flag = disable_interrupts();
56 for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++)
58 struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i;
60 for (reg = 0; reg < 32 && ret == 0; reg++)
62 unsigned int reg0 = (reg + 0) % 32;
63 unsigned int reg1 = (reg + 1) % 32;
64 unsigned int stk = reg < 16 ? 31 : 15;
65 unsigned long code[] =
68 ASM_ADDI(stk, 1, -20),
71 ASM_STW(reg0, stk, 4),
72 ASM_STW(reg1, stk, 0),
73 ASM_LWZ(reg1, stk, 8),
74 ASM_LWZ(reg0, stk, 12),
75 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
76 ASM_STW(reg1, stk, 8),
77 ASM_LWZ(reg1, stk, 0),
78 ASM_LWZ(reg0, stk, 4),
84 unsigned long codecr[] =
87 ASM_ADDI(stk, 1, -20),
90 ASM_STW(reg0, stk, 4),
91 ASM_STW(reg1, stk, 0),
92 ASM_LWZ(reg1, stk, 8),
93 ASM_LWZ(reg0, stk, 12),
94 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) |
96 ASM_STW(reg1, stk, 8),
97 ASM_LWZ(reg1, stk, 0),
98 ASM_LWZ(reg0, stk, 4),
100 ASM_ADDI(1, stk, 20),
110 cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1);
112 ret = res == test->res && cr == 0 ? 0 : -1;
116 post_log ("Error at rlwimi test %d !\n", i);
122 cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1);
124 ret = res == test->res &&
125 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
129 post_log ("Error at rlwimi test %d !\n", i);