1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * Shift instructions: rlwinm
13 * The test contains a pre-built table of instructions, operands and
14 * expected results. For each table entry, the test will cyclically use
15 * different sets of operand registers and result registers.
21 #if CONFIG_POST & CONFIG_SYS_POST_CPU
23 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
24 extern ulong cpu_post_makecr (long v);
26 static struct cpu_post_rlwinm_s
34 } cpu_post_rlwinm_table[] =
45 static unsigned int cpu_post_rlwinm_size = ARRAY_SIZE(cpu_post_rlwinm_table);
47 int cpu_post_test_rlwinm (void)
51 int flag = disable_interrupts();
53 for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++)
55 struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i;
57 for (reg = 0; reg < 32 && ret == 0; reg++)
59 unsigned int reg0 = (reg + 0) % 32;
60 unsigned int reg1 = (reg + 1) % 32;
61 unsigned int stk = reg < 16 ? 31 : 15;
62 unsigned long code[] =
65 ASM_ADDI(stk, 1, -16),
67 ASM_STW(reg0, stk, 4),
68 ASM_STW(reg1, stk, 0),
69 ASM_LWZ(reg0, stk, 8),
70 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me),
71 ASM_STW(reg1, stk, 8),
72 ASM_LWZ(reg1, stk, 0),
73 ASM_LWZ(reg0, stk, 4),
79 unsigned long codecr[] =
82 ASM_ADDI(stk, 1, -16),
84 ASM_STW(reg0, stk, 4),
85 ASM_STW(reg1, stk, 0),
86 ASM_LWZ(reg0, stk, 8),
87 ASM_113(test->cmd, reg1, reg0, test->op2, test->mb,
89 ASM_STW(reg1, stk, 8),
90 ASM_LWZ(reg1, stk, 0),
91 ASM_LWZ(reg0, stk, 4),
103 cpu_post_exec_21 (code, & cr, & res, test->op1);
105 ret = res == test->res && cr == 0 ? 0 : -1;
109 post_log ("Error at rlwinm test %d !\n", i);
115 cpu_post_exec_21 (codecr, & cr, & res, test->op1);
117 ret = res == test->res &&
118 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
122 post_log ("Error at rlwinm test %d !\n", i);