1 // SPDX-License-Identifier: GPL-2.0+
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
11 * Binary instructions instr rD,rA
13 * Logic instructions: neg
14 * Arithmetic instructions: addme, addze, subfme, subfze
16 * The test contains a pre-built table of instructions, operands and
17 * expected results. For each table entry, the test will cyclically use
18 * different sets of operand registers and result registers.
24 #if CONFIG_POST & CONFIG_SYS_POST_CPU
26 extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1);
27 extern ulong cpu_post_makecr (long v);
29 static struct cpu_post_two_s
34 } cpu_post_two_table[] =
67 static unsigned int cpu_post_two_size = ARRAY_SIZE(cpu_post_two_table);
69 int cpu_post_test_two (void)
73 int flag = disable_interrupts();
75 for (i = 0; i < cpu_post_two_size && ret == 0; i++)
77 struct cpu_post_two_s *test = cpu_post_two_table + i;
79 for (reg = 0; reg < 32 && ret == 0; reg++)
81 unsigned int reg0 = (reg + 0) % 32;
82 unsigned int reg1 = (reg + 1) % 32;
83 unsigned int stk = reg < 16 ? 31 : 15;
84 unsigned long code[] =
87 ASM_ADDI(stk, 1, -16),
89 ASM_STW(reg0, stk, 4),
90 ASM_STW(reg1, stk, 0),
91 ASM_LWZ(reg0, stk, 8),
92 ASM_11(test->cmd, reg1, reg0),
93 ASM_STW(reg1, stk, 8),
94 ASM_LWZ(reg1, stk, 0),
95 ASM_LWZ(reg0, stk, 4),
101 unsigned long codecr[] =
104 ASM_ADDI(stk, 1, -16),
106 ASM_STW(reg0, stk, 4),
107 ASM_STW(reg1, stk, 0),
108 ASM_LWZ(reg0, stk, 8),
109 ASM_11(test->cmd, reg1, reg0) | BIT_C,
110 ASM_STW(reg1, stk, 8),
111 ASM_LWZ(reg1, stk, 0),
112 ASM_LWZ(reg0, stk, 4),
114 ASM_ADDI(1, stk, 16),
124 cpu_post_exec_21 (code, & cr, & res, test->op);
126 ret = res == test->res && cr == 0 ? 0 : -1;
130 post_log ("Error at two test %d !\n", i);
136 cpu_post_exec_21 (codecr, & cr, & res, test->op);
138 ret = res == test->res &&
139 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
143 post_log ("Error at two test %d !\n", i);