1 /*****************************************************************************/
5 /* Environment independent low level optimizations */
9 /* (C) 2001-2009, Ullrich von Bassewitz */
10 /* Roemerstrasse 52 */
11 /* D-70794 Filderstadt */
12 /* EMail: uz@cc65.org */
15 /* This software is provided 'as-is', without any expressed or implied */
16 /* warranty. In no event will the authors be held liable for any damages */
17 /* arising from the use of this software. */
19 /* Permission is granted to anyone to use this software for any purpose, */
20 /* including commercial applications, and to alter it and redistribute it */
21 /* freely, subject to the following restrictions: */
23 /* 1. The origin of this software must not be misrepresented; you must not */
24 /* claim that you wrote the original software. If you use this software */
25 /* in a product, an acknowledgment in the product documentation would be */
26 /* appreciated but is not required. */
27 /* 2. Altered source versions must be plainly marked as such, and must not */
28 /* be misrepresented as being the original software. */
29 /* 3. This notice may not be removed or altered from any source */
32 /*****************************************************************************/
48 /*****************************************************************************/
49 /* Helper functions */
50 /*****************************************************************************/
54 static int MemAccess (CodeSeg* S, unsigned From, unsigned To, const CodeEntry* N)
55 /* Checks a range of code entries if there are any memory accesses to N->Arg */
57 /* Get the length of the argument */
58 unsigned NLen = strlen (N->Arg);
60 /* What to check for? */
63 Base = 0x01, /* Check for location without "+1" */
64 Word = 0x02, /* Check for location with "+1" added */
68 /* If the argument of N is a zero page location that ends with "+1", we
69 * must also check for word accesses to the location without +1.
71 if (N->AM == AM65_ZP && NLen > 2 && strcmp (N->Arg + NLen - 2, "+1") == 0) {
75 /* If the argument is zero page indirect, we must also check for accesses
78 if (N->AM == AM65_ZP_INDY || N->AM == AM65_ZPX_IND || N->AM == AM65_ZP_IND) {
82 /* Walk over all code entries */
85 /* Get the next entry */
86 CodeEntry* E = CS_GetEntry (S, From);
88 /* Check if there is an argument and if this argument equals Arg in
91 if (E->Arg[0] != '\0') {
95 if (strcmp (E->Arg, N->Arg) == 0) {
100 ELen = strlen (E->Arg);
101 if ((What & Base) != 0) {
102 if (ELen == NLen - 2 && strncmp (E->Arg, N->Arg, NLen-2) == 0) {
103 /* Found an access */
108 if ((What & Word) != 0) {
109 if (ELen == NLen + 2 && strncmp (E->Arg, N->Arg, NLen) == 0 &&
110 E->Arg[NLen] == '+' && E->Arg[NLen+1] == '1') {
111 /* Found an access */
127 static int GetBranchDist (CodeSeg* S, unsigned From, CodeEntry* To)
128 /* Get the branch distance between the two entries and return it. The distance
129 * will be negative for backward jumps and positive for forward jumps.
132 /* Get the index of the branch target */
133 unsigned TI = CS_GetEntryIndex (S, To);
135 /* Determine the branch distance */
138 /* Forward branch, do not count the current insn */
141 CodeEntry* N = CS_GetEntry (S, J++);
145 /* Backward branch */
148 CodeEntry* N = CS_GetEntry (S, J++);
153 /* Return the calculated distance */
159 static int IsShortDist (int Distance)
160 /* Return true if the given distance is a short branch distance */
162 return (Distance >= -125 && Distance <= 125);
167 static short ZPRegVal (unsigned short Use, const RegContents* RC)
168 /* Return the contents of the given zeropage register */
170 if ((Use & REG_TMP1) != 0) {
172 } else if ((Use & REG_PTR1_LO) != 0) {
174 } else if ((Use & REG_PTR1_HI) != 0) {
176 } else if ((Use & REG_SREG_LO) != 0) {
178 } else if ((Use & REG_SREG_HI) != 0) {
181 return UNKNOWN_REGVAL;
187 static short RegVal (unsigned short Use, const RegContents* RC)
188 /* Return the contents of the given register */
190 if ((Use & REG_A) != 0) {
192 } else if ((Use & REG_X) != 0) {
194 } else if ((Use & REG_Y) != 0) {
197 return ZPRegVal (Use, RC);
203 /*****************************************************************************/
204 /* Replace jumps to RTS by RTS */
205 /*****************************************************************************/
209 unsigned OptRTSJumps1 (CodeSeg* S)
210 /* Replace jumps to RTS by RTS */
212 unsigned Changes = 0;
214 /* Walk over all entries minus the last one */
216 while (I < CS_GetEntryCount (S)) {
218 /* Get the next entry */
219 CodeEntry* E = CS_GetEntry (S, I);
221 /* Check if it's an unconditional branch to a local target */
222 if ((E->Info & OF_UBRA) != 0 &&
224 E->JumpTo->Owner->OPC == OP65_RTS) {
226 /* Insert an RTS instruction */
227 CodeEntry* X = NewCodeEntry (OP65_RTS, AM65_IMP, 0, 0, E->LI);
228 CS_InsertEntry (S, X, I+1);
230 /* Delete the jump */
233 /* Remember, we had changes */
243 /* Return the number of changes made */
249 unsigned OptRTSJumps2 (CodeSeg* S)
250 /* Replace long conditional jumps to RTS */
252 unsigned Changes = 0;
254 /* Walk over all entries minus the last one */
256 while (I < CS_GetEntryCount (S)) {
260 /* Get the next entry */
261 CodeEntry* E = CS_GetEntry (S, I);
263 /* Check if it's an unconditional branch to a local target */
264 if ((E->Info & OF_CBRA) != 0 && /* Conditional branch */
265 (E->Info & OF_LBRA) != 0 && /* Long branch */
266 E->JumpTo != 0 && /* Local label */
267 E->JumpTo->Owner->OPC == OP65_RTS && /* Target is an RTS */
268 (N = CS_GetNextEntry (S, I)) != 0) { /* There is a next entry */
274 /* We will create a jump around an RTS instead of the long branch */
275 X = NewCodeEntry (OP65_RTS, AM65_IMP, 0, 0, E->JumpTo->Owner->LI);
276 CS_InsertEntry (S, X, I+1);
278 /* Get the new branch opcode */
279 NewBranch = MakeShortBranch (GetInverseBranch (E->OPC));
281 /* Get the label attached to N, create a new one if needed */
282 LN = CS_GenLabel (S, N);
284 /* Generate the branch */
285 X = NewCodeEntry (NewBranch, AM65_BRA, LN->Name, LN, E->LI);
286 CS_InsertEntry (S, X, I+1);
288 /* Delete the long branch */
291 /* Remember, we had changes */
301 /* Return the number of changes made */
307 /*****************************************************************************/
308 /* Remove dead jumps */
309 /*****************************************************************************/
313 unsigned OptDeadJumps (CodeSeg* S)
314 /* Remove dead jumps (jumps to the next instruction) */
316 unsigned Changes = 0;
318 /* Walk over all entries minus the last one */
320 while (I < CS_GetEntryCount (S)) {
322 /* Get the next entry */
323 CodeEntry* E = CS_GetEntry (S, I);
325 /* Check if it's a branch, if it has a local target, and if the target
326 * is the next instruction.
328 if (E->AM == AM65_BRA &&
330 E->JumpTo->Owner == CS_GetNextEntry (S, I)) {
332 /* Delete the dead jump */
335 /* Remember, we had changes */
346 /* Return the number of changes made */
352 /*****************************************************************************/
353 /* Remove dead code */
354 /*****************************************************************************/
358 unsigned OptDeadCode (CodeSeg* S)
359 /* Remove dead code (code that follows an unconditional jump or an rts/rti
363 unsigned Changes = 0;
365 /* Walk over all entries */
367 while (I < CS_GetEntryCount (S)) {
373 CodeEntry* E = CS_GetEntry (S, I);
375 /* Check if it's an unconditional branch, and if the next entry has
376 * no labels attached, or if the label is just used so that the insn
377 * can jump to itself.
379 if ((E->Info & OF_DEAD) != 0 && /* Dead code follows */
380 (N = CS_GetNextEntry (S, I)) != 0 && /* Has next entry */
381 (!CE_HasLabel (N) || /* Don't has a label */
382 ((N->Info & OF_UBRA) != 0 && /* Uncond branch */
383 (LN = N->JumpTo) != 0 && /* Jumps to known label */
384 LN->Owner == N && /* Attached to insn */
385 CL_GetRefCount (LN) == 1))) { /* Only reference */
387 /* Delete the next entry */
388 CS_DelEntry (S, I+1);
390 /* Remember, we had changes */
401 /* Return the number of changes made */
407 /*****************************************************************************/
408 /* Optimize jump cascades */
409 /*****************************************************************************/
413 unsigned OptJumpCascades (CodeSeg* S)
414 /* Optimize jump cascades (jumps to jumps). In such a case, the jump is
415 * replaced by a jump to the final location. This will in some cases produce
416 * worse code, because some jump targets are no longer reachable by short
417 * branches, but this is quite rare, so there are more advantages than
421 unsigned Changes = 0;
423 /* Walk over all entries */
425 while (I < CS_GetEntryCount (S)) {
431 CodeEntry* E = CS_GetEntry (S, I);
433 /* Check if it's a branch, if it has a jump label, if this jump
434 * label is not attached to the instruction itself, and if the
435 * target instruction is itself a branch.
437 if ((E->Info & OF_BRA) != 0 &&
438 (OldLabel = E->JumpTo) != 0 &&
439 (N = OldLabel->Owner) != E &&
440 (N->Info & OF_BRA) != 0) {
442 /* Check if we can use the final target label. This is the case,
443 * if the target branch is an absolut branch, or if it is a
444 * conditional branch checking the same condition as the first one.
446 if ((N->Info & OF_UBRA) != 0 ||
447 ((E->Info & OF_CBRA) != 0 &&
448 GetBranchCond (E->OPC) == GetBranchCond (N->OPC))) {
450 /* This is a jump cascade and we may jump to the final target,
451 * provided that the other insn does not jump to itself. If
452 * this is the case, we can also jump to ourselves, otherwise
453 * insert a jump to the new instruction and remove the old one.
456 CodeLabel* LN = N->JumpTo;
458 if (LN != 0 && LN->Owner == N) {
460 /* We found a jump to a jump to itself. Replace our jump
461 * by a jump to itself.
463 CodeLabel* LE = CS_GenLabel (S, E);
464 X = NewCodeEntry (E->OPC, E->AM, LE->Name, LE, E->LI);
468 /* Jump to the final jump target */
469 X = NewCodeEntry (E->OPC, E->AM, N->Arg, N->JumpTo, E->LI);
473 /* Insert it behind E */
474 CS_InsertEntry (S, X, I+1);
479 /* Remember, we had changes */
482 /* Check if both are conditional branches, and the condition of
483 * the second is the inverse of that of the first. In this case,
484 * the second branch will never be taken, and we may jump directly
485 * to the instruction behind this one.
487 } else if ((E->Info & OF_CBRA) != 0 && (N->Info & OF_CBRA) != 0) {
489 CodeEntry* X; /* Instruction behind N */
490 CodeLabel* LX; /* Label attached to X */
492 /* Get the branch conditions of both branches */
493 bc_t BC1 = GetBranchCond (E->OPC);
494 bc_t BC2 = GetBranchCond (N->OPC);
496 /* Check the branch conditions */
497 if (BC1 != GetInverseCond (BC2)) {
498 /* Condition not met */
502 /* We may jump behind this conditional branch. Get the
503 * pointer to the next instruction
505 if ((X = CS_GetNextEntry (S, CS_GetEntryIndex (S, N))) == 0) {
506 /* N is the last entry, bail out */
510 /* Get the label attached to X, create a new one if needed */
511 LX = CS_GenLabel (S, X);
513 /* Move the reference from E to the new label */
514 CS_MoveLabelRef (S, E, LX);
516 /* Remember, we had changes */
527 /* Return the number of changes made */
533 /*****************************************************************************/
534 /* Optimize jsr/rts */
535 /*****************************************************************************/
539 unsigned OptRTS (CodeSeg* S)
540 /* Optimize subroutine calls followed by an RTS. The subroutine call will get
541 * replaced by a jump. Don't bother to delete the RTS if it does not have a
542 * label, the dead code elimination should take care of it.
545 unsigned Changes = 0;
547 /* Walk over all entries minus the last one */
549 while (I < CS_GetEntryCount (S)) {
554 CodeEntry* E = CS_GetEntry (S, I);
556 /* Check if it's a subroutine call and if the following insn is RTS */
557 if (E->OPC == OP65_JSR &&
558 (N = CS_GetNextEntry (S, I)) != 0 &&
559 N->OPC == OP65_RTS) {
561 /* Change the jsr to a jmp and use the additional info for a jump */
563 CE_ReplaceOPC (E, OP65_JMP);
565 /* Remember, we had changes */
575 /* Return the number of changes made */
581 /*****************************************************************************/
582 /* Optimize jump targets */
583 /*****************************************************************************/
587 unsigned OptJumpTarget1 (CodeSeg* S)
588 /* If the instruction preceeding an unconditional branch is the same as the
589 * instruction preceeding the jump target, the jump target may be moved
590 * one entry back. This is a size optimization, since the instruction before
591 * the branch gets removed.
594 unsigned Changes = 0;
595 CodeEntry* E1; /* Entry 1 */
596 CodeEntry* E2; /* Entry 2 */
597 CodeEntry* T1; /* Jump target entry 1 */
598 CodeLabel* TL1; /* Target label 1 */
600 /* Walk over the entries */
602 while (I < CS_GetEntryCount (S)) {
605 E2 = CS_GetNextEntry (S, I);
607 /* Check if we have a jump or branch without a label attached, and
608 * a jump target, which is not attached to the jump itself
611 (E2->Info & OF_UBRA) != 0 &&
614 E2->JumpTo->Owner != E2) {
616 /* Get the entry preceeding the branch target */
617 T1 = CS_GetPrevEntry (S, CS_GetEntryIndex (S, E2->JumpTo->Owner));
619 /* There is no such entry */
623 /* The entry preceeding the branch target may not be the branch
630 /* Get the entry preceeding the jump */
631 E1 = CS_GetEntry (S, I);
633 /* Check if both preceeding instructions are identical */
634 if (!CodeEntriesAreEqual (E1, T1)) {
635 /* Not equal, try next */
639 /* Get the label for the instruction preceeding the jump target.
640 * This routine will create a new label if the instruction does
641 * not already have one.
643 TL1 = CS_GenLabel (S, T1);
645 /* Change the jump target to point to this new label */
646 CS_MoveLabelRef (S, E2, TL1);
648 /* If the instruction preceeding the jump has labels attached,
649 * move references to this label to the new label.
651 if (CE_HasLabel (E1)) {
652 CS_MoveLabels (S, E1, T1);
655 /* Remove the entry preceeding the jump */
658 /* Remember, we had changes */
668 /* Return the number of changes made */
674 unsigned OptJumpTarget2 (CodeSeg* S)
675 /* If a bcs jumps to a sec insn or a bcc jumps to clc, skip this insn, since
676 * it's job is already done.
679 unsigned Changes = 0;
681 /* Walk over the entries */
683 while (I < CS_GetEntryCount (S)) {
685 /* OP that may be skipped */
688 /* Jump target insn, old and new */
696 CodeEntry* E = CS_GetEntry (S, I);
698 /* Check if this is a bcc insn */
699 if (E->OPC == OP65_BCC || E->OPC == OP65_JCC) {
701 } else if (E->OPC == OP65_BCS || E->OPC == OP65_JCS) {
704 /* Not what we're looking for */
708 /* Must have a jump target */
709 if (E->JumpTo == 0) {
713 /* Get the owner insn of the jump target and check if it's the one, we
714 * will skip if present.
716 T = E->JumpTo->Owner;
721 /* Get the entry following the branch target */
722 N = CS_GetNextEntry (S, CS_GetEntryIndex (S, T));
724 /* There is no such entry */
728 /* Get the label for the instruction following the jump target.
729 * This routine will create a new label if the instruction does
730 * not already have one.
732 L = CS_GenLabel (S, N);
734 /* Change the jump target to point to this new label */
735 CS_MoveLabelRef (S, E, L);
737 /* Remember that we had changes */
745 /* Return the number of changes made */
751 /*****************************************************************************/
752 /* Optimize conditional branches */
753 /*****************************************************************************/
757 unsigned OptCondBranches1 (CodeSeg* S)
758 /* Performs several optimization steps:
760 * - If an immidiate load of a register is followed by a conditional jump that
761 * is never taken because the load of the register sets the flags in such a
762 * manner, remove the conditional branch.
763 * - If the conditional branch is always taken because of the register load,
764 * replace it by a jmp.
765 * - If a conditional branch jumps around an unconditional branch, remove the
766 * conditional branch and make the jump a conditional branch with the
767 * inverse condition of the first one.
770 unsigned Changes = 0;
772 /* Walk over the entries */
774 while (I < CS_GetEntryCount (S)) {
780 CodeEntry* E = CS_GetEntry (S, I);
782 /* Check if it's a register load */
783 if ((E->Info & OF_LOAD) != 0 && /* It's a load instruction */
784 E->AM == AM65_IMM && /* ..with immidiate addressing */
785 (E->Flags & CEF_NUMARG) != 0 && /* ..and a numeric argument. */
786 (N = CS_GetNextEntry (S, I)) != 0 && /* There is a following entry */
787 (N->Info & OF_CBRA) != 0 && /* ..which is a conditional branch */
788 !CE_HasLabel (N)) { /* ..and does not have a label */
790 /* Get the branch condition */
791 bc_t BC = GetBranchCond (N->OPC);
793 /* Check the argument against the branch condition */
794 if ((BC == BC_EQ && E->Num != 0) ||
795 (BC == BC_NE && E->Num == 0) ||
796 (BC == BC_PL && (E->Num & 0x80) != 0) ||
797 (BC == BC_MI && (E->Num & 0x80) == 0)) {
799 /* Remove the conditional branch */
800 CS_DelEntry (S, I+1);
802 /* Remember, we had changes */
805 } else if ((BC == BC_EQ && E->Num == 0) ||
806 (BC == BC_NE && E->Num != 0) ||
807 (BC == BC_PL && (E->Num & 0x80) == 0) ||
808 (BC == BC_MI && (E->Num & 0x80) != 0)) {
810 /* The branch is always taken, replace it by a jump */
811 CE_ReplaceOPC (N, OP65_JMP);
813 /* Remember, we had changes */
819 if ((E->Info & OF_CBRA) != 0 && /* It's a conditional branch */
820 (L = E->JumpTo) != 0 && /* ..referencing a local label */
821 (N = CS_GetNextEntry (S, I)) != 0 && /* There is a following entry */
822 (N->Info & OF_UBRA) != 0 && /* ..which is an uncond branch, */
823 !CE_HasLabel (N) && /* ..has no label attached */
824 L->Owner == CS_GetNextEntry (S, I+1)) {/* ..and jump target follows */
826 /* Replace the jump by a conditional branch with the inverse branch
827 * condition than the branch around it.
829 CE_ReplaceOPC (N, GetInverseBranch (E->OPC));
831 /* Remove the conditional branch */
834 /* Remember, we had changes */
844 /* Return the number of changes made */
850 unsigned OptCondBranches2 (CodeSeg* S)
851 /* If on entry to a "rol a" instruction the accu is zero, and a beq/bne follows,
852 * we can remove the rol and branch on the state of the carry flag.
855 unsigned Changes = 0;
858 /* Generate register info for this step */
861 /* Walk over the entries */
863 while (I < CS_GetEntryCount (S)) {
868 CodeEntry* E = CS_GetEntry (S, I);
870 /* Check if it's a rol insn with A in accu and a branch follows */
871 if (E->OPC == OP65_ROL &&
873 E->RI->In.RegA == 0 &&
875 (N = CS_GetNextEntry (S, I)) != 0 &&
876 (N->Info & OF_ZBRA) != 0 &&
877 !RegAUsed (S, I+1)) {
879 /* Replace the branch condition */
880 switch (GetBranchCond (N->OPC)) {
881 case BC_EQ: CE_ReplaceOPC (N, OP65_JCC); break;
882 case BC_NE: CE_ReplaceOPC (N, OP65_JCS); break;
883 default: Internal ("Unknown branch condition in OptCondBranches2");
886 /* Delete the rol insn */
889 /* Remember, we had changes */
897 /* Free register info */
900 /* Return the number of changes made */
906 /*****************************************************************************/
907 /* Remove unused loads and stores */
908 /*****************************************************************************/
912 unsigned OptUnusedLoads (CodeSeg* S)
913 /* Remove loads of registers where the value loaded is not used later. */
915 unsigned Changes = 0;
917 /* Walk over the entries */
919 while (I < CS_GetEntryCount (S)) {
924 CodeEntry* E = CS_GetEntry (S, I);
926 /* Check if it's a register load or transfer insn */
927 if ((E->Info & (OF_LOAD | OF_XFR | OF_REG_INCDEC)) != 0 &&
928 (N = CS_GetNextEntry (S, I)) != 0 &&
929 !CE_UseLoadFlags (N)) {
931 /* Check which sort of load or transfer it is */
938 case OP65_TYA: R = REG_A; break;
942 case OP65_TAX: R = REG_X; break;
946 case OP65_TAY: R = REG_Y; break;
947 default: goto NextEntry; /* OOPS */
950 /* Get register usage and check if the register value is used later */
951 if ((GetRegInfo (S, I+1, R) & R) == 0) {
953 /* Register value is not used, remove the load */
956 /* Remember, we had changes. Account the deleted entry in I. */
969 /* Return the number of changes made */
975 unsigned OptUnusedStores (CodeSeg* S)
976 /* Remove stores into zero page registers that aren't used later */
978 unsigned Changes = 0;
980 /* Walk over the entries */
982 while (I < CS_GetEntryCount (S)) {
985 CodeEntry* E = CS_GetEntry (S, I);
987 /* Check if it's a register load or transfer insn */
988 if ((E->Info & OF_STORE) != 0 &&
990 (E->Chg & REG_ZP) != 0) {
992 /* Check for the zero page location. We know that there cannot be
993 * more than one zero page location involved in the store.
995 unsigned R = E->Chg & REG_ZP;
997 /* Get register usage and check if the register value is used later */
998 if ((GetRegInfo (S, I+1, R) & R) == 0) {
1000 /* Register value is not used, remove the load */
1003 /* Remember, we had changes */
1006 /* Continue with next insn */
1016 /* Return the number of changes made */
1022 unsigned OptDupLoads (CodeSeg* S)
1023 /* Remove loads of registers where the value loaded is already in the register. */
1025 unsigned Changes = 0;
1028 /* Generate register info for this step */
1031 /* Walk over the entries */
1033 while (I < CS_GetEntryCount (S)) {
1037 /* Get next entry */
1038 CodeEntry* E = CS_GetEntry (S, I);
1040 /* Assume we won't delete the entry */
1043 /* Get a pointer to the input registers of the insn */
1044 const RegContents* In = &E->RI->In;
1046 /* Handle the different instructions */
1050 if (RegValIsKnown (In->RegA) && /* Value of A is known */
1051 CE_IsKnownImm (E, In->RegA) && /* Value to be loaded is known */
1052 (N = CS_GetNextEntry (S, I)) != 0 && /* There is a next entry */
1053 !CE_UseLoadFlags (N)) { /* Which does not use the flags */
1059 if (RegValIsKnown (In->RegX) && /* Value of X is known */
1060 CE_IsKnownImm (E, In->RegX) && /* Value to be loaded is known */
1061 (N = CS_GetNextEntry (S, I)) != 0 && /* There is a next entry */
1062 !CE_UseLoadFlags (N)) { /* Which does not use the flags */
1068 if (RegValIsKnown (In->RegY) && /* Value of Y is known */
1069 CE_IsKnownImm (E, In->RegY) && /* Value to be loaded is known */
1070 (N = CS_GetNextEntry (S, I)) != 0 && /* There is a next entry */
1071 !CE_UseLoadFlags (N)) { /* Which does not use the flags */
1077 /* If we store into a known zero page location, and this
1078 * location does already contain the value to be stored,
1081 if (RegValIsKnown (In->RegA) && /* Value of A is known */
1082 E->AM == AM65_ZP && /* Store into zp */
1083 In->RegA == ZPRegVal (E->Chg, In)) { /* Value identical */
1090 /* If we store into a known zero page location, and this
1091 * location does already contain the value to be stored,
1094 if (RegValIsKnown (In->RegX) && /* Value of A is known */
1095 E->AM == AM65_ZP && /* Store into zp */
1096 In->RegX == ZPRegVal (E->Chg, In)) { /* Value identical */
1100 /* If the value in the X register is known and the same as
1101 * that in the A register, replace the store by a STA. The
1102 * optimizer will then remove the load instruction for X
1103 * later. STX does support the zeropage,y addressing mode,
1104 * so be sure to check for that.
1106 } else if (RegValIsKnown (In->RegX) &&
1107 In->RegX == In->RegA &&
1108 E->AM != AM65_ABSY &&
1109 E->AM != AM65_ZPY) {
1110 /* Use the A register instead */
1111 CE_ReplaceOPC (E, OP65_STA);
1116 /* If we store into a known zero page location, and this
1117 * location does already contain the value to be stored,
1120 if (RegValIsKnown (In->RegY) && /* Value of Y is known */
1121 E->AM == AM65_ZP && /* Store into zp */
1122 In->RegY == ZPRegVal (E->Chg, In)) { /* Value identical */
1126 /* If the value in the Y register is known and the same as
1127 * that in the A register, replace the store by a STA. The
1128 * optimizer will then remove the load instruction for Y
1129 * later. If replacement by A is not possible try a
1130 * replacement by X, but check for invalid addressing modes
1133 } else if (RegValIsKnown (In->RegY)) {
1134 if (In->RegY == In->RegA) {
1135 CE_ReplaceOPC (E, OP65_STA);
1136 } else if (In->RegY == In->RegX &&
1137 E->AM != AM65_ABSX &&
1138 E->AM != AM65_ZPX) {
1139 CE_ReplaceOPC (E, OP65_STX);
1145 /* If we store into a known zero page location, and this
1146 * location does already contain the value to be stored,
1149 if ((CPUIsets[CPU] & CPU_ISET_65SC02) != 0 && E->AM == AM65_ZP) {
1150 if (ZPRegVal (E->Chg, In) == 0) {
1157 if (RegValIsKnown (In->RegA) &&
1158 In->RegA == In->RegX &&
1159 (N = CS_GetNextEntry (S, I)) != 0 &&
1160 !CE_UseLoadFlags (N)) {
1161 /* Value is identical and not followed by a branch */
1167 if (RegValIsKnown (In->RegA) &&
1168 In->RegA == In->RegY &&
1169 (N = CS_GetNextEntry (S, I)) != 0 &&
1170 !CE_UseLoadFlags (N)) {
1171 /* Value is identical and not followed by a branch */
1177 if (RegValIsKnown (In->RegX) &&
1178 In->RegX == In->RegA &&
1179 (N = CS_GetNextEntry (S, I)) != 0 &&
1180 !CE_UseLoadFlags (N)) {
1181 /* Value is identical and not followed by a branch */
1187 if (RegValIsKnown (In->RegY) &&
1188 In->RegY == In->RegA &&
1189 (N = CS_GetNextEntry (S, I)) != 0 &&
1190 !CE_UseLoadFlags (N)) {
1191 /* Value is identical and not followed by a branch */
1201 /* Delete the entry if requested */
1204 /* Register value is not used, remove the load */
1207 /* Remember, we had changes */
1219 /* Free register info */
1222 /* Return the number of changes made */
1228 unsigned OptStoreLoad (CodeSeg* S)
1229 /* Remove a store followed by a load from the same location. */
1231 unsigned Changes = 0;
1233 /* Walk over the entries */
1235 while (I < CS_GetEntryCount (S)) {
1240 /* Get next entry */
1241 CodeEntry* E = CS_GetEntry (S, I);
1243 /* Check if it is a store instruction followed by a load from the
1244 * same address which is itself not followed by a conditional branch.
1246 if ((E->Info & OF_STORE) != 0 &&
1247 (N = CS_GetNextEntry (S, I)) != 0 &&
1250 ((E->OPC == OP65_STA && N->OPC == OP65_LDA) ||
1251 (E->OPC == OP65_STX && N->OPC == OP65_LDX) ||
1252 (E->OPC == OP65_STY && N->OPC == OP65_LDY)) &&
1253 strcmp (E->Arg, N->Arg) == 0 &&
1254 (X = CS_GetNextEntry (S, I+1)) != 0 &&
1255 !CE_UseLoadFlags (X)) {
1257 /* Register has already the correct value, remove the load */
1258 CS_DelEntry (S, I+1);
1260 /* Remember, we had changes */
1270 /* Return the number of changes made */
1276 unsigned OptTransfers1 (CodeSeg* S)
1277 /* Remove transfers from one register to another and back */
1279 unsigned Changes = 0;
1281 /* Walk over the entries */
1283 while (I < CS_GetEntryCount (S)) {
1289 /* Get next entry */
1290 CodeEntry* E = CS_GetEntry (S, I);
1292 /* Check if we have two transfer instructions */
1293 if ((E->Info & OF_XFR) != 0 &&
1294 (N = CS_GetNextEntry (S, I)) != 0 &&
1296 (N->Info & OF_XFR) != 0) {
1298 /* Check if it's a transfer and back */
1299 if ((E->OPC == OP65_TAX && N->OPC == OP65_TXA && !RegXUsed (S, I+2)) ||
1300 (E->OPC == OP65_TAY && N->OPC == OP65_TYA && !RegYUsed (S, I+2)) ||
1301 (E->OPC == OP65_TXA && N->OPC == OP65_TAX && !RegAUsed (S, I+2)) ||
1302 (E->OPC == OP65_TYA && N->OPC == OP65_TAY && !RegAUsed (S, I+2))) {
1304 /* If the next insn is a conditional branch, check if the insn
1305 * preceeding the first xfr will set the flags right, otherwise we
1306 * may not remove the sequence.
1308 if ((X = CS_GetNextEntry (S, I+1)) == 0) {
1311 if (CE_UseLoadFlags (X)) {
1313 /* No preceeding entry */
1316 P = CS_GetEntry (S, I-1);
1317 if ((P->Info & OF_SETF) == 0) {
1318 /* Does not set the flags */
1323 /* Remove both transfers */
1324 CS_DelEntry (S, I+1);
1327 /* Remember, we had changes */
1338 /* Return the number of changes made */
1344 unsigned OptTransfers2 (CodeSeg* S)
1345 /* Replace loads followed by a register transfer by a load with the second
1346 * register if possible.
1349 unsigned Changes = 0;
1351 /* Walk over the entries */
1353 while (I < CS_GetEntryCount (S)) {
1357 /* Get next entry */
1358 CodeEntry* E = CS_GetEntry (S, I);
1360 /* Check if we have a load followed by a transfer where the loaded
1361 * register is not used later.
1363 if ((E->Info & OF_LOAD) != 0 &&
1364 (N = CS_GetNextEntry (S, I)) != 0 &&
1366 (N->Info & OF_XFR) != 0 &&
1367 GetRegInfo (S, I+2, E->Chg) != E->Chg) {
1371 if (E->OPC == OP65_LDA && N->OPC == OP65_TAX) {
1372 /* LDA/TAX - check for the right addressing modes */
1373 if (E->AM == AM65_IMM ||
1375 E->AM == AM65_ABS ||
1376 E->AM == AM65_ABSY) {
1378 X = NewCodeEntry (OP65_LDX, E->AM, E->Arg, 0, N->LI);
1380 } else if (E->OPC == OP65_LDA && N->OPC == OP65_TAY) {
1381 /* LDA/TAY - check for the right addressing modes */
1382 if (E->AM == AM65_IMM ||
1384 E->AM == AM65_ZPX ||
1385 E->AM == AM65_ABS ||
1386 E->AM == AM65_ABSX) {
1388 X = NewCodeEntry (OP65_LDY, E->AM, E->Arg, 0, N->LI);
1390 } else if (E->OPC == OP65_LDY && N->OPC == OP65_TYA) {
1391 /* LDY/TYA. LDA supports all addressing modes LDY does */
1392 X = NewCodeEntry (OP65_LDA, E->AM, E->Arg, 0, N->LI);
1393 } else if (E->OPC == OP65_LDX && N->OPC == OP65_TXA) {
1394 /* LDX/TXA. LDA doesn't support zp,y, so we must map it to
1397 am_t AM = (E->AM == AM65_ZPY)? AM65_ABSY : E->AM;
1398 X = NewCodeEntry (OP65_LDA, AM, E->Arg, 0, N->LI);
1401 /* If we have a load entry, add it and remove the old stuff */
1403 CS_InsertEntry (S, X, I+2);
1404 CS_DelEntries (S, I, 2);
1406 --I; /* Correct for one entry less */
1414 /* Return the number of changes made */
1420 unsigned OptTransfers3 (CodeSeg* S)
1421 /* Replace a register transfer followed by a store of the second register by a
1422 * store of the first register if this is possible.
1425 unsigned Changes = 0;
1426 unsigned UsedRegs = REG_NONE; /* Track used registers */
1427 unsigned Xfer = 0; /* Index of transfer insn */
1428 unsigned Store = 0; /* Index of store insn */
1429 CodeEntry* XferEntry = 0; /* Pointer to xfer insn */
1430 CodeEntry* StoreEntry = 0; /* Pointer to store insn */
1437 } State = Initialize;
1439 /* Walk over the entries. Look for a xfer instruction that is followed by
1440 * a store later, where the value of the register is not used later.
1443 while (I < CS_GetEntryCount (S)) {
1445 /* Get next entry */
1446 CodeEntry* E = CS_GetEntry (S, I);
1451 /* Clear the list of used registers */
1452 UsedRegs = REG_NONE;
1456 if (E->Info & OF_XFR) {
1457 /* Found start of sequence */
1465 /* If we find a conditional jump, abort the sequence, since
1466 * handling them makes things really complicated.
1468 if (E->Info & OF_CBRA) {
1470 /* Switch back to searching */
1474 /* Does this insn use the target register of the transfer? */
1475 } else if ((E->Use & XferEntry->Chg) != 0) {
1477 /* It it's a store instruction, and the block is a basic
1478 * block, proceed. Otherwise restart
1480 if ((E->Info & OF_STORE) != 0 &&
1481 CS_IsBasicBlock (S, Xfer, I)) {
1490 /* Does this insn change the target register of the transfer? */
1491 } else if (E->Chg & XferEntry->Chg) {
1493 /* We *may* add code here to remove the transfer, but I'm
1494 * currently not sure about the consequences, so I won't
1495 * do that and bail out instead.
1500 /* Does this insn have a label? */
1501 } else if (CE_HasLabel (E)) {
1503 /* Too complex to handle - bail out */
1508 /* Track used registers */
1514 /* We are at the instruction behind the store. If the register
1515 * isn't used later, and we have an address mode match, we can
1516 * replace the transfer by a store and remove the store here.
1518 if ((GetRegInfo (S, I, XferEntry->Chg) & XferEntry->Chg) == 0 &&
1519 (StoreEntry->AM == AM65_ABS ||
1520 StoreEntry->AM == AM65_ZP) &&
1521 (StoreEntry->AM != AM65_ZP ||
1522 (StoreEntry->Chg & UsedRegs) == 0) &&
1523 !MemAccess (S, Xfer+1, Store-1, StoreEntry)) {
1525 /* Generate the replacement store insn */
1527 switch (XferEntry->OPC) {
1530 X = NewCodeEntry (OP65_STX,
1538 X = NewCodeEntry (OP65_STA,
1546 X = NewCodeEntry (OP65_STY,
1554 X = NewCodeEntry (OP65_STA,
1565 /* If we have a replacement store, change the code */
1567 /* Insert after the xfer insn */
1568 CS_InsertEntry (S, X, Xfer+1);
1570 /* Remove the xfer instead */
1571 CS_DelEntry (S, Xfer);
1573 /* Remove the final store */
1574 CS_DelEntry (S, Store);
1576 /* Correct I so we continue with the next insn */
1579 /* Remember we had changes */
1582 /* Restart after last xfer insn */
1586 /* Restart after last xfer insn */
1598 /* Return the number of changes made */
1604 unsigned OptTransfers4 (CodeSeg* S)
1605 /* Replace a load of a register followed by a transfer insn of the same register
1606 * by a load of the second register if possible.
1609 unsigned Changes = 0;
1610 unsigned Load = 0; /* Index of load insn */
1611 unsigned Xfer = 0; /* Index of transfer insn */
1612 CodeEntry* LoadEntry = 0; /* Pointer to load insn */
1613 CodeEntry* XferEntry = 0; /* Pointer to xfer insn */
1621 /* Walk over the entries. Look for a load instruction that is followed by
1625 while (I < CS_GetEntryCount (S)) {
1627 /* Get next entry */
1628 CodeEntry* E = CS_GetEntry (S, I);
1633 if (E->Info & OF_LOAD) {
1634 /* Found start of sequence */
1642 /* If we find a conditional jump, abort the sequence, since
1643 * handling them makes things really complicated.
1645 if (E->Info & OF_CBRA) {
1647 /* Switch back to searching */
1651 /* Does this insn use the target register of the load? */
1652 } else if ((E->Use & LoadEntry->Chg) != 0) {
1654 /* It it's a xfer instruction, and the block is a basic
1655 * block, proceed. Otherwise restart
1657 if ((E->Info & OF_XFR) != 0 &&
1658 CS_IsBasicBlock (S, Load, I)) {
1667 /* Does this insn change the target register of the load? */
1668 } else if (E->Chg & LoadEntry->Chg) {
1670 /* We *may* add code here to remove the load, but I'm
1671 * currently not sure about the consequences, so I won't
1672 * do that and bail out instead.
1680 /* We are at the instruction behind the xfer. If the register
1681 * isn't used later, and we have an address mode match, we can
1682 * replace the transfer by a load and remove the initial load.
1684 if ((GetRegInfo (S, I, LoadEntry->Chg) & LoadEntry->Chg) == 0 &&
1685 (LoadEntry->AM == AM65_ABS ||
1686 LoadEntry->AM == AM65_ZP ||
1687 LoadEntry->AM == AM65_IMM) &&
1688 !MemAccess (S, Load+1, Xfer-1, LoadEntry)) {
1690 /* Generate the replacement load insn */
1692 switch (XferEntry->OPC) {
1696 X = NewCodeEntry (OP65_LDA,
1704 X = NewCodeEntry (OP65_LDX,
1712 X = NewCodeEntry (OP65_LDY,
1723 /* If we have a replacement load, change the code */
1725 /* Insert after the xfer insn */
1726 CS_InsertEntry (S, X, Xfer+1);
1728 /* Remove the xfer instead */
1729 CS_DelEntry (S, Xfer);
1731 /* Remove the initial load */
1732 CS_DelEntry (S, Load);
1734 /* Correct I so we continue with the next insn */
1737 /* Remember we had changes */
1740 /* Restart after last xfer insn */
1744 /* Restart after last xfer insn */
1756 /* Return the number of changes made */
1762 unsigned OptPushPop (CodeSeg* S)
1763 /* Remove a PHA/PLA sequence were A is not used later */
1765 unsigned Changes = 0;
1766 unsigned Push = 0; /* Index of push insn */
1767 unsigned Pop = 0; /* Index of pop insn */
1768 unsigned ChgA = 0; /* Flag for A changed */
1773 } State = Searching;
1775 /* Walk over the entries. Look for a push instruction that is followed by
1776 * a pop later, where the pop is not followed by an conditional branch,
1777 * and where the value of the A register is not used later on.
1778 * Look out for the following problems:
1780 * - There may be another PHA/PLA inside the sequence: Restart it.
1781 * - If the PLA has a label, all jumps to this label must be inside
1782 * the sequence, otherwise we cannot remove the PHA/PLA.
1785 while (I < CS_GetEntryCount (S)) {
1789 /* Get next entry */
1790 CodeEntry* E = CS_GetEntry (S, I);
1795 if (E->OPC == OP65_PHA) {
1796 /* Found start of sequence */
1804 if (E->OPC == OP65_PHA) {
1805 /* Inner push/pop, restart */
1808 } else if (E->OPC == OP65_PLA) {
1809 /* Found a matching pop */
1811 /* Check that the block between Push and Pop is a basic
1812 * block (one entry, one exit). Otherwise ignore it.
1814 if (CS_IsBasicBlock (S, Push, Pop)) {
1817 /* Go into searching mode again */
1820 } else if (E->Chg & REG_A) {
1826 /* We're at the instruction after the PLA.
1827 * Check for the following conditions:
1828 * - If this instruction is a store of A, and A is not used
1829 * later, we may replace the PHA by the store and remove
1830 * pla if several other conditions are met.
1831 * - If this instruction is not a conditional branch, and A
1832 * is either unused later, or not changed by the code
1833 * between push and pop, we may remove PHA and PLA.
1835 if (E->OPC == OP65_STA &&
1836 !RegAUsed (S, I+1) &&
1837 !MemAccess (S, Push+1, Pop-1, E)) {
1839 /* Insert a STA after the PHA */
1840 X = NewCodeEntry (E->OPC, E->AM, E->Arg, E->JumpTo, E->LI);
1841 CS_InsertEntry (S, X, Push+1);
1843 /* Remove the PHA instead */
1844 CS_DelEntry (S, Push);
1846 /* Remove the PLA/STA sequence */
1847 CS_DelEntries (S, Pop, 2);
1849 /* Correct I so we continue with the next insn */
1852 /* Remember we had changes */
1855 } else if ((E->Info & OF_CBRA) == 0 &&
1856 (!RegAUsed (S, I) || !ChgA)) {
1858 /* We can remove the PHA and PLA instructions */
1859 CS_DelEntry (S, Pop);
1860 CS_DelEntry (S, Push);
1862 /* Correct I so we continue with the next insn */
1865 /* Remember we had changes */
1869 /* Go into search mode again */
1879 /* Return the number of changes made */
1885 unsigned OptPrecalc (CodeSeg* S)
1886 /* Replace immediate operations with the accu where the current contents are
1887 * known by a load of the final value.
1890 unsigned Changes = 0;
1893 /* Generate register info for this step */
1896 /* Walk over the entries */
1898 while (I < CS_GetEntryCount (S)) {
1900 /* Get next entry */
1901 CodeEntry* E = CS_GetEntry (S, I);
1903 /* Get pointers to the input and output registers of the insn */
1904 const RegContents* Out = &E->RI->Out;
1905 const RegContents* In = &E->RI->In;
1907 /* Argument for LDn and flag */
1908 const char* Arg = 0;
1909 opc_t OPC = OP65_LDA;
1911 /* Handle the different instructions */
1915 if (E->AM != AM65_IMM && RegValIsKnown (Out->RegA)) {
1916 /* Result of load is known */
1917 Arg = MakeHexArg (Out->RegA);
1922 if (E->AM != AM65_IMM && RegValIsKnown (Out->RegX)) {
1923 /* Result of load is known but register is X */
1924 Arg = MakeHexArg (Out->RegX);
1930 if (E->AM != AM65_IMM && RegValIsKnown (Out->RegY)) {
1931 /* Result of load is known but register is Y */
1932 Arg = MakeHexArg (Out->RegY);
1938 if (RegValIsKnown (Out->RegA)) {
1939 /* Accu op zp with known contents */
1940 Arg = MakeHexArg (Out->RegA);
1946 /* If this is an operation with an immediate operand of zero,
1947 * and the register is zero, the operation won't give us any
1948 * results we don't already have (including the flags), so
1949 * remove it. Something like this is generated as a result of
1950 * a compare where parts of the values are known to be zero.
1952 if (In->RegA == 0 && CE_IsKnownImm (E, 0x00)) {
1953 /* 0-0 or 0+0 -> remove */
1960 if (CE_IsKnownImm (E, 0xFF)) {
1961 /* AND with 0xFF, remove */
1964 } else if (CE_IsKnownImm (E, 0x00)) {
1965 /* AND with 0x00, replace by lda #$00 */
1966 Arg = MakeHexArg (0x00);
1967 } else if (RegValIsKnown (Out->RegA)) {
1968 /* Accu AND zp with known contents */
1969 Arg = MakeHexArg (Out->RegA);
1970 } else if (In->RegA == 0xFF) {
1971 /* AND but A contains 0xFF - replace by lda */
1972 CE_ReplaceOPC (E, OP65_LDA);
1978 if (CE_IsKnownImm (E, 0x00)) {
1979 /* ORA with zero, remove */
1982 } else if (CE_IsKnownImm (E, 0xFF)) {
1983 /* ORA with 0xFF, replace by lda #$ff */
1984 Arg = MakeHexArg (0xFF);
1985 } else if (RegValIsKnown (Out->RegA)) {
1986 /* Accu AND zp with known contents */
1987 Arg = MakeHexArg (Out->RegA);
1988 } else if (In->RegA == 0) {
1989 /* ORA but A contains 0x00 - replace by lda */
1990 CE_ReplaceOPC (E, OP65_LDA);
2000 /* Check if we have to replace the insn by LDA */
2002 CodeEntry* X = NewCodeEntry (OPC, AM65_IMM, Arg, 0, E->LI);
2003 CS_InsertEntry (S, X, I+1);
2012 /* Free register info */
2015 /* Return the number of changes made */
2021 /*****************************************************************************/
2022 /* Optimize branch types */
2023 /*****************************************************************************/
2027 unsigned OptBranchDist (CodeSeg* S)
2028 /* Change branches for the distance needed. */
2030 unsigned Changes = 0;
2032 /* Walk over the entries */
2034 while (I < CS_GetEntryCount (S)) {
2036 /* Get next entry */
2037 CodeEntry* E = CS_GetEntry (S, I);
2039 /* Check if it's a conditional branch to a local label. */
2040 if (E->Info & OF_CBRA) {
2042 /* Is this a branch to a local symbol? */
2043 if (E->JumpTo != 0) {
2045 /* Check if the branch distance is short */
2046 int IsShort = IsShortDist (GetBranchDist (S, I, E->JumpTo->Owner));
2048 /* Make the branch short/long according to distance */
2049 if ((E->Info & OF_LBRA) == 0 && !IsShort) {
2050 /* Short branch but long distance */
2051 CE_ReplaceOPC (E, MakeLongBranch (E->OPC));
2053 } else if ((E->Info & OF_LBRA) != 0 && IsShort) {
2054 /* Long branch but short distance */
2055 CE_ReplaceOPC (E, MakeShortBranch (E->OPC));
2059 } else if ((E->Info & OF_LBRA) == 0) {
2061 /* Short branch to external symbol - make it long */
2062 CE_ReplaceOPC (E, MakeLongBranch (E->OPC));
2067 } else if ((CPUIsets[CPU] & CPU_ISET_65SC02) != 0 &&
2068 (E->Info & OF_UBRA) != 0 &&
2070 IsShortDist (GetBranchDist (S, I, E->JumpTo->Owner))) {
2072 /* The jump is short and may be replaced by a BRA on the 65C02 CPU */
2073 CE_ReplaceOPC (E, OP65_BRA);
2082 /* Return the number of changes made */
2088 /*****************************************************************************/
2089 /* Optimize indirect loads */
2090 /*****************************************************************************/
2094 unsigned OptIndLoads1 (CodeSeg* S)
2103 * provided that x and y are both zero.
2106 unsigned Changes = 0;
2109 /* Generate register info for this step */
2112 /* Walk over the entries */
2114 while (I < CS_GetEntryCount (S)) {
2116 /* Get next entry */
2117 CodeEntry* E = CS_GetEntry (S, I);
2119 /* Check if it's what we're looking for */
2120 if (E->OPC == OP65_LDA &&
2121 E->AM == AM65_ZP_INDY &&
2122 E->RI->In.RegY == 0 &&
2123 E->RI->In.RegX == 0) {
2125 /* Replace by the same insn with other addressing mode */
2126 CodeEntry* X = NewCodeEntry (E->OPC, AM65_ZPX_IND, E->Arg, 0, E->LI);
2127 CS_InsertEntry (S, X, I+1);
2129 /* Remove the old insn */
2139 /* Free register info */
2142 /* Return the number of changes made */
2148 unsigned OptIndLoads2 (CodeSeg* S)
2157 * provided that x and y are both zero.
2160 unsigned Changes = 0;
2163 /* Generate register info for this step */
2166 /* Walk over the entries */
2168 while (I < CS_GetEntryCount (S)) {
2170 /* Get next entry */
2171 CodeEntry* E = CS_GetEntry (S, I);
2173 /* Check if it's what we're looking for */
2174 if (E->OPC == OP65_LDA &&
2175 E->AM == AM65_ZPX_IND &&
2176 E->RI->In.RegY == 0 &&
2177 E->RI->In.RegX == 0) {
2179 /* Replace by the same insn with other addressing mode */
2180 CodeEntry* X = NewCodeEntry (E->OPC, AM65_ZP_INDY, E->Arg, 0, E->LI);
2181 CS_InsertEntry (S, X, I+1);
2183 /* Remove the old insn */
2193 /* Free register info */
2196 /* Return the number of changes made */