1 /***************************************************************************
2 * Copyright (C) 2006 by Magnus Lundin *
5 * Copyright (C) 2008 by Gheorghe Guran (atlas) *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
15 * GNU General public License for more details. *
17 * You should have received a copy of the GNU General public License *
18 * along with this program; if not, write to the *
19 * Free Software Foundation, Inc., *
20 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
21 ****************************************************************************/
23 /***************************************************************************************************************************************************************************************
25 * New flash setup command:
27 * flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
29 * <ext_freq_khz> - MUST be used if clock is from external source,
30 * CAN be used if main oscillator frequency is known (recomended)
32 * flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000 ==== RECOMENDED ============
33 * flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000 (auto-detection, except for clock) ==== RECOMENDED ============
34 * flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
35 * flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
36 ****************************************************************************************************************************************************************************************/
42 #include "replacements.h"
49 #include "binarybuffer.h"
56 int at91sam7_register_commands(struct command_context_s *cmd_ctx);
57 int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
58 int at91sam7_erase(struct flash_bank_s *bank, int first, int last);
59 int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last);
60 int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
61 int at91sam7_probe(struct flash_bank_s *bank);
62 int at91sam7_auto_probe(struct flash_bank_s *bank);
63 int at91sam7_erase_check(struct flash_bank_s *bank);
64 int at91sam7_protect_check(struct flash_bank_s *bank);
65 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size);
67 u32 at91sam7_get_flash_status(target_t *target, int bank_number);
68 void at91sam7_set_flash_mode(flash_bank_t *bank, int mode);
69 u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout);
70 int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen);
71 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
73 flash_driver_t at91sam7_flash =
75 .name = "at91sam7_new",
76 .register_commands = at91sam7_register_commands,
77 .flash_bank_command = at91sam7_flash_bank_command,
78 .erase = at91sam7_erase,
79 .protect = at91sam7_protect,
80 .write = at91sam7_write,
81 .probe = at91sam7_probe,
82 .auto_probe = at91sam7_probe,
83 .erase_check = at91sam7_erase_check,
84 .protect_check = at91sam7_protect_check,
89 u32 MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
90 u32 MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
91 u32 MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
93 char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
114 int at91sam7_register_commands(struct command_context_s *cmd_ctx)
116 command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7_new", NULL, COMMAND_ANY, NULL);
118 register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
119 "at91sam7 gpnvm <bit> set|clear, set or clear one gpnvm bit");
123 u32 at91sam7_get_flash_status(target_t *target, int bank_number)
126 target_read_u32(target, MC_FSR[bank_number], &fsr);
131 /* Read clock configuration and set at91sam7_info->mck_freq */
132 void at91sam7_read_clock_info(flash_bank_t *bank)
134 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
135 target_t *target = bank->target;
136 u32 mckr, mcfr, pllr, mor;
137 unsigned long tmp = 0, mainfreq;
139 /* Read Clock Generator Main Oscillator Register */
140 target_read_u32(target, CKGR_MOR, &mor);
141 /* Read Clock Generator Main Clock Frequency Register */
142 target_read_u32(target, CKGR_MCFR, &mcfr);
143 /* Read Master Clock Register*/
144 target_read_u32(target, PMC_MCKR, &mckr);
145 /* Read Clock Generator PLL Register */
146 target_read_u32(target, CKGR_PLLR, &pllr);
148 at91sam7_info->mck_valid = 0;
149 at91sam7_info->mck_freq = 0;
150 switch (mckr & PMC_MCKR_CSS)
152 case 0: /* Slow Clock */
153 at91sam7_info->mck_valid = 1;
157 case 1: /* Main Clock */
158 if ((mcfr & CKGR_MCFR_MAINRDY) &&
159 (at91sam7_info->ext_freq == 0))
161 at91sam7_info->mck_valid = 1;
162 tmp = RC_FREQ / 16ul * (mcfr & 0xffff);
164 else if (at91sam7_info->ext_freq != 0)
166 at91sam7_info->mck_valid = 1;
167 tmp = at91sam7_info->ext_freq;
171 case 2: /* Reserved */
174 case 3: /* PLL Clock */
175 if ((mcfr & CKGR_MCFR_MAINRDY) &&
176 (at91sam7_info->ext_freq == 0))
178 target_read_u32(target, CKGR_PLLR, &pllr);
179 if (!(pllr & CKGR_PLLR_DIV))
181 at91sam7_info->mck_valid = 1;
182 mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
183 /* Integer arithmetic should have sufficient precision
184 as long as PLL is properly configured. */
185 tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
186 (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
188 else if ((at91sam7_info->ext_freq != 0) &&
189 ((pllr&CKGR_PLLR_DIV) != 0))
191 at91sam7_info->mck_valid = 1;
192 tmp = at91sam7_info->ext_freq / (pllr&CKGR_PLLR_DIV)*
193 (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
198 /* Prescaler adjust */
199 if ( (((mckr & PMC_MCKR_PRES) >> 2) == 7) || (tmp == 0) )
201 at91sam7_info->mck_valid = 0;
202 at91sam7_info->mck_freq = 0;
204 else if (((mckr & PMC_MCKR_PRES) >> 2) != 0)
205 at91sam7_info->mck_freq = tmp >> ((mckr & PMC_MCKR_PRES) >> 2);
207 at91sam7_info->mck_freq = tmp;
210 /* Setup the timimg registers for nvbits or normal flash */
211 void at91sam7_set_flash_mode(flash_bank_t *bank, int mode)
213 u32 fmr, fmcn = 0, fws = 0;
214 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
215 target_t *target = bank->target;
217 if (mode && (mode != at91sam7_info->flashmode))
219 /* Always round up (ceil) */
220 if (mode == FMR_TIMING_NVBITS)
222 if (at91sam7_info->cidr_arch == 0x60)
224 /* AT91SAM7A3 uses master clocks in 100 ns */
225 fmcn = (at91sam7_info->mck_freq/10000000ul)+1;
229 /* master clocks in 1uS for ARCH 0x7 types */
230 fmcn = (at91sam7_info->mck_freq/1000000ul)+1;
233 else if (mode == FMR_TIMING_FLASH)
235 /* main clocks in 1.5uS */
236 fmcn = (at91sam7_info->mck_freq/1000000ul)+
237 (at91sam7_info->mck_freq/2000000ul)+1;
240 /* hard overclocking */
244 /* Only allow fmcn=0 if clock period is > 30 us = 33kHz. */
245 if (at91sam7_info->mck_freq <= 33333ul)
247 /* Only allow fws=0 if clock frequency is < 30 MHz. */
248 if (at91sam7_info->mck_freq > 30000000ul)
251 LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, fmcn);
252 fmr = fmcn << 16 | fws << 8;
253 target_write_u32(target, MC_FMR[bank->bank_number], fmr);
256 at91sam7_info->flashmode = mode;
259 u32 at91sam7_wait_status_busy(flash_bank_t *bank, u32 waitbits, int timeout)
263 while ((!((status = at91sam7_get_flash_status(bank->target, bank->bank_number)) & waitbits)) && (timeout-- > 0))
265 LOG_DEBUG("status[%i]: 0x%x", bank->bank_number, status);
269 LOG_DEBUG("status[%i]: 0x%x", bank->bank_number, status);
273 LOG_ERROR("status register: 0x%x", status);
275 LOG_ERROR("Lock Error Bit Detected, Operation Abort");
277 LOG_ERROR("Invalid command and/or bad keyword, Operation Abort");
279 LOG_ERROR("Security Bit Set, Operation Abort");
285 /* Send one command to the AT91SAM flash controller */
286 int at91sam7_flash_command(struct flash_bank_s *bank, u8 cmd, u16 pagen)
289 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
290 target_t *target = bank->target;
292 fcr = (0x5A<<24) | ((pagen&0x3FF)<<8) | cmd;
293 target_write_u32(target, MC_FCR[bank->bank_number], fcr);
294 LOG_DEBUG("Flash command: 0x%x, flash bank: %i, page number: %u", fcr, bank->bank_number+1, pagen);
296 if ((at91sam7_info->cidr_arch == 0x60)&&((cmd==SLB)|(cmd==CLB)))
298 /* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
299 if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
301 return ERROR_FLASH_OPERATION_FAILED;
306 if (at91sam7_wait_status_busy(bank, MC_FSR_FRDY, 10)&0x0C)
308 return ERROR_FLASH_OPERATION_FAILED;
314 /* Read device id register, main clock frequency register and fill in driver info structure */
315 int at91sam7_read_part_info(struct flash_bank_s *bank)
317 flash_bank_t *t_bank = bank;
318 at91sam7_flash_bank_t *at91sam7_info;
319 target_t *target = t_bank->target;
327 u16 pages_per_sector;
331 u32 base_address = 0;
332 char *target_name = "Unknown";
334 at91sam7_info = t_bank->driver_priv;
336 if (at91sam7_info->cidr != 0)
338 /* flash already configured, update clock and check for protected sectors */
339 flash_bank_t *fb = bank;
344 /* re-calculate master clock frequency */
345 at91sam7_read_clock_info(t_bank);
348 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
350 /* check protect state */
351 at91sam7_protect_check(t_bank);
360 /* Read and parse chip identification register */
361 target_read_u32(target, DBGU_CIDR, &cidr);
364 LOG_WARNING("Cannot identify target as an AT91SAM");
365 return ERROR_FLASH_OPERATION_FAILED;
368 if (at91sam7_info->flash_autodetection == 0)
370 /* banks and sectors are already created, based on data from input file */
371 flash_bank_t *fb = bank;
375 at91sam7_info = t_bank->driver_priv;
377 at91sam7_info->cidr = cidr;
378 at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
379 at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
380 at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
381 at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
382 at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
383 at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
384 at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
385 at91sam7_info->cidr_version = cidr&0x001F;
387 /* calculate master clock frequency */
388 at91sam7_read_clock_info(t_bank);
391 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
393 /* check protect state */
394 at91sam7_protect_check(t_bank);
403 arch = (cidr>>20)&0x00FF;
405 /* check flash size */
406 switch ((cidr>>8)&0x000F)
411 case FLASH_SIZE_16KB:
414 pages_per_sector = 32;
416 base_address = 0x00100000;
420 target_name = "AT91SAM7S161/16";
424 case FLASH_SIZE_32KB:
427 pages_per_sector = 32;
429 base_address = 0x00100000;
433 target_name = "AT91SAM7S321/32";
438 target_name = "AT91SAM7SE32";
442 case FLASH_SIZE_64KB:
445 pages_per_sector = 32;
447 base_address = 0x00100000;
451 target_name = "AT91SAM7S64";
455 case FLASH_SIZE_128KB:
458 pages_per_sector = 64;
460 base_address = 0x00100000;
464 target_name = "AT91SAM7S128";
469 target_name = "AT91SAM7XC128";
474 target_name = "AT91SAM7SE128";
479 target_name = "AT91SAM7X128";
483 case FLASH_SIZE_256KB:
486 pages_per_sector = 64;
488 base_address = 0x00100000;
492 target_name = "AT91SAM7A3";
497 target_name = "AT91SAM7S256";
502 target_name = "AT91SAM7XC256";
507 target_name = "AT91SAM7SE256";
512 target_name = "AT91SAM7X256";
516 case FLASH_SIZE_512KB:
519 pages_per_sector = 64;
521 base_address = 0x00100000;
525 target_name = "AT91SAM7S512";
530 target_name = "AT91SAM7XC512";
535 target_name = "AT91SAM7SE512";
540 target_name = "AT91SAM7X512";
544 case FLASH_SIZE_1024KB:
547 case FLASH_SIZE_2048KB:
551 if (strcmp(target_name, "Unknown") == 0)
553 LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
554 return ERROR_FLASH_OPERATION_FAILED;
557 ext_freq = at91sam7_info->ext_freq;
559 /* calculate bank size */
560 bank_size = sectors_num * pages_per_sector * page_size;
562 for (bnk=0; bnk<banks_num; bnk++)
566 /* create a new flash bank element */
567 flash_bank_t *fb = malloc(sizeof(flash_bank_t));
569 fb->driver = &at91sam7_flash;
570 fb->driver_priv = malloc(sizeof(at91sam7_flash_bank_t));
573 /* link created bank in 'flash_banks' list and redirect t_bank */
578 t_bank->bank_number = bnk;
579 t_bank->base = base_address + bnk * bank_size;
580 t_bank->size = bank_size;
581 t_bank->chip_width = 0;
582 t_bank->bus_width = 4;
583 t_bank->num_sectors = sectors_num;
585 /* allocate sectors */
586 t_bank->sectors = malloc(sectors_num * sizeof(flash_sector_t));
587 for (sec=0; sec<sectors_num; sec++)
589 t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
590 t_bank->sectors[sec].size = pages_per_sector * page_size;
591 t_bank->sectors[sec].is_erased = -1;
592 t_bank->sectors[sec].is_protected = -1;
595 at91sam7_info = t_bank->driver_priv;
597 at91sam7_info->cidr = cidr;
598 at91sam7_info->cidr_ext = (cidr>>31)&0x0001;
599 at91sam7_info->cidr_nvptyp = (cidr>>28)&0x0007;
600 at91sam7_info->cidr_arch = (cidr>>20)&0x00FF;
601 at91sam7_info->cidr_sramsiz = (cidr>>16)&0x000F;
602 at91sam7_info->cidr_nvpsiz2 = (cidr>>12)&0x000F;
603 at91sam7_info->cidr_nvpsiz = (cidr>>8)&0x000F;
604 at91sam7_info->cidr_eproc = (cidr>>5)&0x0007;
605 at91sam7_info->cidr_version = cidr&0x001F;
607 at91sam7_info->target_name = target_name;
608 at91sam7_info->flashmode = 0;
609 at91sam7_info->ext_freq = ext_freq;
610 at91sam7_info->num_nvmbits = num_nvmbits;
611 at91sam7_info->num_nvmbits_on = 0;
612 at91sam7_info->pagesize = page_size;
613 at91sam7_info->pages_per_sector = pages_per_sector;
615 /* calculate master clock frequency */
616 at91sam7_read_clock_info(t_bank);
619 at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
621 /* check protect state */
622 at91sam7_protect_check(t_bank);
625 LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch );
630 int at91sam7_erase_check(struct flash_bank_s *bank)
632 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
634 target_t *target = bank->target;
642 if (bank->target->state != TARGET_HALTED)
644 LOG_ERROR("Target not halted");
645 return ERROR_TARGET_NOT_HALTED;
648 /* Configure the flash controller timing */
649 at91sam7_read_clock_info(bank);
650 at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
653 for (nSector=0; nSector<bank->num_sectors; nSector++)
655 retval = target_blank_check_memory(target, bank->base+bank->sectors[nSector].offset,
656 bank->sectors[nSector].size, &blank);
657 if (retval != ERROR_OK)
663 bank->sectors[nSector].is_erased = 1;
665 bank->sectors[nSector].is_erased = 0;
673 LOG_USER("Running slow fallback erase check - add working memory");
675 buffer = malloc(bank->sectors[0].size);
676 for (nSector=0; nSector<bank->num_sectors; nSector++)
679 bank->sectors[nSector].is_erased = 1;
680 retval = target->type->read_memory(target, bank->base+bank->sectors[nSector].offset, 4,
681 bank->sectors[nSector].size/4, buffer);
682 if (retval != ERROR_OK)
685 for (nByte=0; nByte<bank->sectors[nSector].size; nByte++)
687 if (buffer[nByte] != 0xFF)
689 bank->sectors[nSector].is_erased = 0;
699 int at91sam7_protect_check(struct flash_bank_s *bank)
701 u8 lock_pos, gpnvm_pos;
704 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
706 if (at91sam7_info->cidr == 0)
708 return ERROR_FLASH_BANK_NOT_PROBED;
710 if (bank->target->state != TARGET_HALTED)
712 LOG_ERROR("Target not halted");
713 return ERROR_TARGET_NOT_HALTED;
716 status = at91sam7_get_flash_status(bank->target, bank->bank_number);
717 at91sam7_info->lockbits = (status>>16);
719 at91sam7_info->num_lockbits_on = 0;
720 for (lock_pos=0; lock_pos<bank->num_sectors; lock_pos++)
722 if ( ((status>>(16+lock_pos))&(0x0001)) == 1)
724 at91sam7_info->num_lockbits_on++;
725 bank->sectors[lock_pos].is_protected = 1;
728 bank->sectors[lock_pos].is_protected = 0;
731 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
732 status = at91sam7_get_flash_status(bank->target, 0);
734 at91sam7_info->securitybit = (status>>4)&0x01;
735 at91sam7_info->nvmbits = (status>>8)&0xFF;
737 at91sam7_info->num_nvmbits_on = 0;
738 for (gpnvm_pos=0; gpnvm_pos<at91sam7_info->num_nvmbits; gpnvm_pos++)
740 if ( ((status>>(8+gpnvm_pos))&(0x01)) == 1)
742 at91sam7_info->num_nvmbits_on++;
749 /***************************************************************************************************************************************************************************************
750 # flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
751 # <ext_freq_khz> - MUST be used if clock is from external source
752 # CAN be used if main oscillator frequency is known
754 # flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000 ==== RECOMENDED ============
755 # flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000 (auto-detection, except for clock) ==== RECOMENDED ============
756 # flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0 ==== NOT RECOMENDED !!! ====
757 # flash bank at91sam7 0 0 0 0 0 (old style, full auto-detection) ==== NOT RECOMENDED !!! ====
758 ****************************************************************************************************************************************************************************************/
759 int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
761 flash_bank_t *t_bank = bank;
762 at91sam7_flash_bank_t *at91sam7_info;
763 target_t *target = t_bank->target;
774 u16 pages_per_sector;
782 at91sam7_info = malloc(sizeof(at91sam7_flash_bank_t));
783 t_bank->driver_priv = at91sam7_info;
785 /* part wasn't probed for info yet */
786 at91sam7_info->cidr = 0;
787 at91sam7_info->flashmode = 0;
788 at91sam7_info->ext_freq = 0;
789 at91sam7_info->flash_autodetection = 0;
793 ext_freq = atol(args[13]) * 1000;
794 at91sam7_info->ext_freq = ext_freq;
798 (atoi(args[4]) == 0) || /* bus width */
799 (atoi(args[8]) == 0) || /* banks number */
800 (atoi(args[9]) == 0) || /* sectors per bank */
801 (atoi(args[10]) == 0) || /* pages per sector */
802 (atoi(args[11]) == 0) || /* page size */
803 (atoi(args[12]) == 0)) /* nvmbits number */
805 at91sam7_info->flash_autodetection = 1;
809 base_address = strtoul(args[1], NULL, 0);
810 chip_width = atoi(args[3]);
811 bus_width = atoi(args[4]);
812 banks_num = atoi(args[8]);
813 num_sectors = atoi(args[9]);
814 pages_per_sector = atoi(args[10]);
815 page_size = atoi(args[11]);
816 num_nvmbits = atoi(args[12]);
818 target_name = calloc(strlen(args[7])+1, sizeof(char));
819 strcpy(target_name, args[7]);
821 /* calculate bank size */
822 bank_size = num_sectors * pages_per_sector * page_size;
824 for (bnk=0; bnk<banks_num; bnk++)
828 /* create a new bank element */
829 flash_bank_t *fb = malloc(sizeof(flash_bank_t));
831 fb->driver = &at91sam7_flash;
832 fb->driver_priv = malloc(sizeof(at91sam7_flash_bank_t));
835 /* link created bank in 'flash_banks' list and redirect t_bank */
840 t_bank->bank_number = bnk;
841 t_bank->base = base_address + bnk * bank_size;
842 t_bank->size = bank_size;
843 t_bank->chip_width = chip_width;
844 t_bank->bus_width = bus_width;
845 t_bank->num_sectors = num_sectors;
847 /* allocate sectors */
848 t_bank->sectors = malloc(num_sectors * sizeof(flash_sector_t));
849 for (sec=0; sec<num_sectors; sec++)
851 t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
852 t_bank->sectors[sec].size = pages_per_sector * page_size;
853 t_bank->sectors[sec].is_erased = -1;
854 t_bank->sectors[sec].is_protected = -1;
857 at91sam7_info = t_bank->driver_priv;
859 at91sam7_info->target_name = target_name;
860 at91sam7_info->flashmode = 0;
861 at91sam7_info->ext_freq = ext_freq;
862 at91sam7_info->num_nvmbits = num_nvmbits;
863 at91sam7_info->num_nvmbits_on = 0;
864 at91sam7_info->pagesize = page_size;
865 at91sam7_info->pages_per_sector = pages_per_sector;
871 int at91sam7_erase(struct flash_bank_s *bank, int first, int last)
873 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
879 if (at91sam7_info->cidr == 0)
881 return ERROR_FLASH_BANK_NOT_PROBED;
884 if (bank->target->state != TARGET_HALTED)
886 LOG_ERROR("Target not halted");
887 return ERROR_TARGET_NOT_HALTED;
890 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
892 return ERROR_FLASH_SECTOR_INVALID;
896 if ((first == 0) && (last == (bank->num_sectors-1)))
901 /* Configure the flash controller timing */
902 at91sam7_read_clock_info(bank);
903 at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
907 if (at91sam7_flash_command(bank, EA, 0) != ERROR_OK)
909 return ERROR_FLASH_OPERATION_FAILED;
914 /* allocate and clean buffer */
915 nbytes = (last - first + 1) * bank->sectors[first].size;
916 buffer = malloc(nbytes * sizeof(u8));
917 for (pos=0; pos<nbytes; pos++)
922 if ( at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
924 return ERROR_FLASH_OPERATION_FAILED;
930 /* mark erased sectors */
931 for (sec=first; sec<=last; sec++)
933 bank->sectors[sec].is_erased = 1;
939 int at91sam7_protect(struct flash_bank_s *bank, int set, int first, int last)
944 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
946 if (at91sam7_info->cidr == 0)
948 return ERROR_FLASH_BANK_NOT_PROBED;
951 if (bank->target->state != TARGET_HALTED)
953 LOG_ERROR("Target not halted");
954 return ERROR_TARGET_NOT_HALTED;
957 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
959 return ERROR_FLASH_SECTOR_INVALID;
962 /* Configure the flash controller timing */
963 at91sam7_read_clock_info(bank);
964 at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
966 for (sector=first; sector<=last; sector++)
973 /* if we lock a page from one sector then entire sector will be locked, also,
974 if we unlock a page from a locked sector, entire sector will be unlocked */
975 pagen = sector * at91sam7_info->pages_per_sector;
977 if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
979 return ERROR_FLASH_OPERATION_FAILED;
983 at91sam7_protect_check(bank);
988 int at91sam7_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
990 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
991 target_t *target = bank->target;
992 u32 dst_min_alignment, wcount, bytes_remaining = count;
993 u32 first_page, last_page, pagen, buffer_pos;
995 if (at91sam7_info->cidr == 0)
997 return ERROR_FLASH_BANK_NOT_PROBED;
1000 if (bank->target->state != TARGET_HALTED)
1002 LOG_ERROR("Target not halted");
1003 return ERROR_TARGET_NOT_HALTED;
1006 if (offset + count > bank->size)
1007 return ERROR_FLASH_DST_OUT_OF_BANK;
1009 dst_min_alignment = at91sam7_info->pagesize;
1011 if (offset % dst_min_alignment)
1013 LOG_WARNING("offset 0x%x breaks required alignment 0x%x", offset, dst_min_alignment);
1014 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
1017 if (at91sam7_info->cidr_arch == 0)
1018 return ERROR_FLASH_BANK_NOT_PROBED;
1020 first_page = offset/dst_min_alignment;
1021 last_page = CEIL(offset + count, dst_min_alignment);
1023 LOG_DEBUG("first_page: %i, last_page: %i, count %i", first_page, last_page, count);
1025 /* Configure the flash controller timing */
1026 at91sam7_read_clock_info(bank);
1027 at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
1029 for (pagen=first_page; pagen<last_page; pagen++)
1031 if (bytes_remaining<dst_min_alignment)
1032 count = bytes_remaining;
1034 count = dst_min_alignment;
1035 bytes_remaining -= count;
1037 /* Write one block to the PageWriteBuffer */
1038 buffer_pos = (pagen-first_page)*dst_min_alignment;
1039 wcount = CEIL(count,4);
1040 target->type->write_memory(target, bank->base+pagen*dst_min_alignment, 4, wcount, buffer+buffer_pos);
1042 /* Send Write Page command to Flash Controller */
1043 if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
1045 return ERROR_FLASH_OPERATION_FAILED;
1047 LOG_DEBUG("Write flash bank:%i page number:%i", bank->bank_number, pagen);
1053 int at91sam7_probe(struct flash_bank_s *bank)
1055 /* we can't probe on an at91sam7
1056 * if this is an at91sam7, it has the configured flash
1058 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
1061 if (bank->target->state != TARGET_HALTED)
1063 LOG_ERROR("Target not halted");
1064 return ERROR_TARGET_NOT_HALTED;
1067 retval = at91sam7_read_part_info(bank);
1068 if (retval != ERROR_OK)
1074 int at91sam7_info(struct flash_bank_s *bank, char *buf, int buf_size)
1077 at91sam7_flash_bank_t *at91sam7_info = bank->driver_priv;
1079 if (at91sam7_info->cidr == 0)
1081 return ERROR_FLASH_BANK_NOT_PROBED;
1084 printed = snprintf(buf, buf_size,
1085 "\n at91sam7 driver information: Chip is %s\n",
1086 at91sam7_info->target_name);
1089 buf_size -= printed;
1091 printed = snprintf(buf, buf_size,
1092 " Cidr: 0x%8.8x | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8x\n",
1093 at91sam7_info->cidr, at91sam7_info->cidr_arch, EPROC[at91sam7_info->cidr_eproc],
1094 at91sam7_info->cidr_version, bank->size);
1097 buf_size -= printed;
1099 printed = snprintf(buf, buf_size,
1100 " Master clock (estimated): %li KHz | External clock: %li KHz\n",
1101 at91sam7_info->mck_freq / 1000, at91sam7_info->ext_freq / 1000);
1104 buf_size -= printed;
1106 printed = snprintf(buf, buf_size,
1107 " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
1108 at91sam7_info->pagesize, bank->num_sectors, at91sam7_info->num_lockbits_on,
1109 at91sam7_info->lockbits, at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
1112 buf_size -= printed;
1114 printed = snprintf(buf, buf_size,
1115 " Securitybit: %i | Nvmbits(%i): %i 0x%1.1x\n",
1116 at91sam7_info->securitybit, at91sam7_info->num_nvmbits,
1117 at91sam7_info->num_nvmbits_on, at91sam7_info->nvmbits);
1120 buf_size -= printed;
1126 * On AT91SAM7S: When the gpnvm bits are set with
1127 * > at91sam7 gpnvm bitnr set
1128 * the changes are not visible in the flash controller status register MC_FSR
1129 * until the processor has been reset.
1130 * On the Olimex board this requires a power cycle.
1131 * Note that the AT91SAM7S has the following errata (doc6175.pdf sec 14.1.3):
1132 * The maximum number of write/erase cycles for Non volatile Memory bits is 100. this includes
1133 * Lock Bits (LOCKx), General Purpose NVM bits (GPNVMx) and the Security Bit.
1135 int at91sam7_handle_gpnvm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1141 at91sam7_flash_bank_t *at91sam7_info;
1146 command_print(cmd_ctx, "at91sam7 gpnvm <bit> <set|clear>");
1150 bank = get_flash_bank_by_num_noprobe(0);
1153 return ERROR_FLASH_BANK_INVALID;
1155 if (bank->driver != &at91sam7_flash)
1157 command_print(cmd_ctx, "not an at91sam7 flash bank '%s'", args[0]);
1158 return ERROR_FLASH_BANK_INVALID;
1160 if (bank->target->state != TARGET_HALTED)
1162 LOG_ERROR("target has to be halted to perform flash operation");
1163 return ERROR_TARGET_NOT_HALTED;
1166 if (strcmp(args[1], "set") == 0)
1170 else if (strcmp(args[1], "clear") == 0)
1176 return ERROR_COMMAND_SYNTAX_ERROR;
1179 at91sam7_info = bank->driver_priv;
1180 if (at91sam7_info->cidr == 0)
1182 retval = at91sam7_read_part_info(bank);
1183 if (retval != ERROR_OK)
1189 bit = atoi(args[0]);
1190 if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits))
1192 command_print(cmd_ctx, "gpnvm bit '#%s' is out of bounds for target %s", args[0], at91sam7_info->target_name);
1196 /* Configure the flash controller timing */
1197 at91sam7_read_clock_info(bank);
1198 at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
1200 if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
1202 return ERROR_FLASH_OPERATION_FAILED;
1205 /* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
1206 status = at91sam7_get_flash_status(bank->target, 0);
1207 LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value 0x%x, status 0x%x \n", flashcmd, bit, status);
1209 /* check protect state */
1210 at91sam7_protect_check(bank);