git.sur5r.net Git - openocd/blob - src/flash/cfi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28
  29 #include "flash.h"
  30 #include "target.h"
  31 #include "log.h"
  32 #include "armv4_5.h"
  33 #include "algorithm.h"
  34 #include "binarybuffer.h"
  35 #include "types.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40
  41 int cfi_register_commands(struct command_context_s *cmd_ctx);
  42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
  44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  46 int cfi_probe(struct flash_bank_s *bank);
  47 int cfi_auto_probe(struct flash_bank_s *bank);
  48 int cfi_protect_check(struct flash_bank_s *bank);
  49 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  50
  51 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52
  53 #define CFI_MAX_BUS_WIDTH       4
  54 #define CFI_MAX_CHIP_WIDTH      4
  55
  56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  57 #define CFI_MAX_INTEL_CODESIZE 256
  58
  59 flash_driver_t cfi_flash =
  60 {
  61         .name = "cfi",
  62         .register_commands = cfi_register_commands,
  63         .flash_bank_command = cfi_flash_bank_command,
  64         .erase = cfi_erase,
  65         .protect = cfi_protect,
  66         .write = cfi_write,
  67         .probe = cfi_probe,
  68         .auto_probe = cfi_auto_probe,
  69         .erase_check = default_flash_blank_check,
  70         .protect_check = cfi_protect_check,
  71         .info = cfi_info
  72 };
  73
  74 cfi_unlock_addresses_t cfi_unlock_addresses[] =
  75 {
  76         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  77         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  78 };
  79
  80 /* CFI fixups foward declarations */
  81 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  82 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  84
  85 /* fixup after identifying JEDEC manufactuer and ID */
  86 cfi_fixup_t cfi_jedec_fixups[] = {
  87         {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
  88         {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
  89         {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
  90         {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
  91         {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
  92         {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
  93         {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
  94         {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
  95         {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
  96         {0, 0, NULL, NULL}
  97 };
  98
  99 /* fixup after reading cmdset 0002 primary query table */
 100 cfi_fixup_t cfi_0002_fixups[] = {
 101         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 102         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 103         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 104         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 105         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 106         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
 107         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
 108         {0, 0, NULL, NULL}
 109 };
 110
 111 /* fixup after reading cmdset 0001 primary query table */
 112 cfi_fixup_t cfi_0001_fixups[] = {
 113         {0, 0, NULL, NULL}
 114 };
 115
 116 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
 117 {
 118         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 119         cfi_fixup_t *f;
 120
 121         for (f = fixups; f->fixup; f++)
 122         {
 123                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 124                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 125                 {
 126                         f->fixup(bank, f->param);
 127                 }
 128         }
 129 }
 130
 131 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 132 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 133 {
 134         /* while the sector list isn't built, only accesses to sector 0 work */
 135         if (sector == 0)
 136                 return bank->base + offset * bank->bus_width;
 137         else
 138         {
 139                 if (!bank->sectors)
 140                 {
 141                         LOG_ERROR("BUG: sector list not yet built");
 142                         exit(-1);
 143                 }
 144                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 145         }
 146
 147 }
 148
 149 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 150 {
 151         int i;
 152
 153         /* clear whole buffer, to ensure bits that exceed the bus_width
 154          * are set to zero
 155          */
 156         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 157                 cmd_buf[i] = 0;
 158
 159         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 160         {
 161                 for (i = bank->bus_width; i > 0; i--)
 162                 {
 163                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 164                 }
 165         }
 166         else
 167         {
 168                 for (i = 1; i <= bank->bus_width; i++)
 169                 {
 170                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 171                 }
 172         }
 173 }
 174
 175 /* read unsigned 8-bit value from the bank
 176  * flash banks are expected to be made of similar chips
 177  * the query result should be the same for all
 178  */
 179 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 180 {
 181         target_t *target = bank->target;
 182         u8 data[CFI_MAX_BUS_WIDTH];
 183
 184         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 185
 186         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 187                 return data[0];
 188         else
 189                 return data[bank->bus_width - 1];
 190 }
 191
 192 /* read unsigned 8-bit value from the bank
 193  * in case of a bank made of multiple chips,
 194  * the individual values are ORed
 195  */
 196 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 197 {
 198         target_t *target = bank->target;
 199         u8 data[CFI_MAX_BUS_WIDTH];
 200         int i;
 201
 202         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 203
 204         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 205         {
 206                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 207                         data[0] |= data[i];
 208
 209                 return data[0];
 210         }
 211         else
 212         {
 213                 u8 value = 0;
 214                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 215                         value |= data[bank->bus_width - 1 - i];
 216
 217                 return value;
 218         }
 219 }
 220
 221 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 222 {
 223         target_t *target = bank->target;
 224         u8 data[CFI_MAX_BUS_WIDTH * 2];
 225
 226         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 227
 228         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 229                 return data[0] | data[bank->bus_width] << 8;
 230         else
 231                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 232 }
 233
 234 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 235 {
 236         target_t *target = bank->target;
 237         u8 data[CFI_MAX_BUS_WIDTH * 4];
 238
 239         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 240
 241         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 242                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 243         else
 244                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 245                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 246 }
 247
 248 void cfi_intel_clear_status_register(flash_bank_t *bank)
 249 {
 250         target_t *target = bank->target;
 251         u8 command[8];
 252
 253         if (target->state != TARGET_HALTED)
 254         {
 255                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 256                 exit(-1);
 257         }
 258
 259         cfi_command(bank, 0x50, command);
 260         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 261 }
 262
 263 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 264 {
 265         u8 status;
 266
 267         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 268         {
 269                 LOG_DEBUG("status: 0x%x", status);
 270                 usleep(1000);
 271         }
 272
 273         /* mask out bit 0 (reserved) */
 274         status = status & 0xfe;
 275
 276         LOG_DEBUG("status: 0x%x", status);
 277
 278         if ((status & 0x80) != 0x80)
 279         {
 280                 LOG_ERROR("timeout while waiting for WSM to become ready");
 281         }
 282         else if (status != 0x80)
 283         {
 284                 LOG_ERROR("status register: 0x%x", status);
 285                 if (status & 0x2)
 286                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 287                 if (status & 0x4)
 288                         LOG_ERROR("Program suspended");
 289                 if (status & 0x8)
 290                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 291                 if (status & 0x10)
 292                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 293                 if (status & 0x20)
 294                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 295                 if (status & 0x40)
 296                         LOG_ERROR("Block Erase Suspended");
 297
 298                 cfi_intel_clear_status_register(bank);
 299         }
 300
 301         return status;
 302 }
 303
 304 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 305 {
 306         u8 status, oldstatus;
 307
 308         oldstatus = cfi_get_u8(bank, 0, 0x0);
 309
 310         do {
 311                 status = cfi_get_u8(bank, 0, 0x0);
 312                 if ((status ^ oldstatus) & 0x40) {
 313                         if (status & 0x20) {
 314                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 315                                 status = cfi_get_u8(bank, 0, 0x0);
 316                                 if ((status ^ oldstatus) & 0x40) {
 317                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 318                                         return(ERROR_FLASH_OPERATION_FAILED);
 319                                 } else {
 320                                         LOG_DEBUG("status: 0x%x", status);
 321                                         return(ERROR_OK);
 322                                 }
 323                         }
 324                 } else {
 325                         LOG_DEBUG("status: 0x%x", status);
 326                         return(ERROR_OK);
 327                 }
 328
 329                 oldstatus = status;
 330                 usleep(1000);
 331         } while (timeout-- > 0);
 332
 333         LOG_ERROR("timeout, status: 0x%x", status);
 334
 335         return(ERROR_FLASH_BUSY);
 336 }
 337
 338 int cfi_read_intel_pri_ext(flash_bank_t *bank)
 339 {
 340         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 341         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 342         target_t *target = bank->target;
 343         u8 command[8];
 344
 345         cfi_info->pri_ext = pri_ext;
 346
 347         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 348         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 349         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 350
 351         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 352         {
 353                 cfi_command(bank, 0xf0, command);
 354                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 355                 cfi_command(bank, 0xff, command);
 356                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 357                 return ERROR_FLASH_BANK_INVALID;
 358         }
 359
 360         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 361         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 362
 363         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 364
 365         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 366         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 367         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 368
 369         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 370
 371         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 372         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 373
 374         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 375                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 376                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 377
 378         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 379         if (pri_ext->num_protection_fields != 1)
 380         {
 381                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 382         }
 383
 384         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 385         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 386         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 387
 388         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 389
 390         return ERROR_OK;
 391 }
 392
 393 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 394 {
 395         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 396         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 397         target_t *target = bank->target;
 398         u8 command[8];
 399
 400         cfi_info->pri_ext = pri_ext;
 401
 402         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 403         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 404         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 405
 406         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 407         {
 408                 cfi_command(bank, 0xf0, command);
 409                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 410                 return ERROR_FLASH_BANK_INVALID;
 411         }
 412
 413         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 414         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 415
 416         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 417
 418         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 419         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 420         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 421         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 422         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 423         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 424         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 425         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 426         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 427         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 428         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 429
 430         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 431               pri_ext->EraseSuspend, pri_ext->BlkProt);
 432
 433         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 434               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 435
 436         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 437
 438
 439         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 440                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 441                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 442
 443         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 444
 445         /* default values for implementation specific workarounds */
 446         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 447         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 448         pri_ext->_reversed_geometry = 0;
 449
 450         return ERROR_OK;
 451 }
 452
 453 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 454 {
 455         cfi_atmel_pri_ext_t atmel_pri_ext;
 456         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 457         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 458         target_t *target = bank->target;
 459         u8 command[8];
 460
 461         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 462          * but a different primary extended query table.
 463          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 464          */
 465
 466         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 467
 468         cfi_info->pri_ext = pri_ext;
 469
 470         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 471         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 472         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 473
 474         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 475         {
 476                 cfi_command(bank, 0xf0, command);
 477                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 478                 return ERROR_FLASH_BANK_INVALID;
 479         }
 480
 481         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 482         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 483         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 484
 485         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 486         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 487
 488         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 489
 490         pri_ext->major_version = atmel_pri_ext.major_version;
 491         pri_ext->minor_version = atmel_pri_ext.minor_version;
 492
 493         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 494         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 495         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 496         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 497
 498         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 499                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 500
 501         if (atmel_pri_ext.features & 0x02)
 502                 pri_ext->EraseSuspend = 2;
 503
 504         if (atmel_pri_ext.bottom_boot)
 505                 pri_ext->TopBottom = 2;
 506         else
 507                 pri_ext->TopBottom = 3;
 508
 509         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 510         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 511
 512         return ERROR_OK;
 513 }
 514
 515 int cfi_read_0002_pri_ext(flash_bank_t *bank)
 516 {
 517         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 518
 519         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 520         {
 521                 return cfi_read_atmel_pri_ext(bank);
 522         }
 523         else
 524         {
 525                 return cfi_read_spansion_pri_ext(bank);
 526         }
 527 }
 528
 529 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 530 {
 531         int printed;
 532         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 533         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 534
 535         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 536         buf += printed;
 537         buf_size -= printed;
 538
 539         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 540                            pri_ext->pri[1], pri_ext->pri[2],
 541                            pri_ext->major_version, pri_ext->minor_version);
 542         buf += printed;
 543         buf_size -= printed;
 544
 545         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 546                            (pri_ext->SiliconRevision) >> 2,
 547                            (pri_ext->SiliconRevision) & 0x03);
 548         buf += printed;
 549         buf_size -= printed;
 550
 551         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 552                            pri_ext->EraseSuspend,
 553                            pri_ext->BlkProt);
 554         buf += printed;
 555         buf_size -= printed;
 556
 557         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 558                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 559                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 560
 561         return ERROR_OK;
 562 }
 563
 564 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 565 {
 566         int printed;
 567         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 568         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 569
 570         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 571         buf += printed;
 572         buf_size -= printed;
 573
 574         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 575         buf += printed;
 576         buf_size -= printed;
 577
 578         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 579         buf += printed;
 580         buf_size -= printed;
 581
 582         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 583                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 584                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 585         buf += printed;
 586         buf_size -= printed;
 587
 588         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 589
 590         return ERROR_OK;
 591 }
 592
 593 int cfi_register_commands(struct command_context_s *cmd_ctx)
 594 {
 595         /*command_t *cfi_cmd = */
 596         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 597         /*
 598         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 599                                          "print part id of cfi flash bank <num>");
 600         */
 601         return ERROR_OK;
 602 }
 603
 604 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 605  */
 606 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 607 {
 608         cfi_flash_bank_t *cfi_info;
 609         int i;
 610
 611         if (argc < 6)
 612         {
 613                 LOG_WARNING("incomplete flash_bank cfi configuration");
 614                 return ERROR_FLASH_BANK_INVALID;
 615         }
 616
 617         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 618                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 619         {
 620                 LOG_ERROR("chip and bus width have to specified in bytes");
 621                 return ERROR_FLASH_BANK_INVALID;
 622         }
 623
 624         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 625         cfi_info->probed = 0;
 626         bank->driver_priv = cfi_info;
 627
 628         cfi_info->write_algorithm = NULL;
 629
 630         cfi_info->x16_as_x8 = 0;
 631         cfi_info->jedec_probe = 0;
 632         cfi_info->not_cfi = 0;
 633
 634         for (i = 6; i < argc; i++)
 635         {
 636                 if (strcmp(args[i], "x16_as_x8") == 0)
 637                 {
 638                         cfi_info->x16_as_x8 = 1;
 639                 }
 640                 else if (strcmp(args[i], "jedec_probe") == 0)
 641                 {
 642                         cfi_info->jedec_probe = 1;
 643                 }
 644         }
 645
 646         cfi_info->write_algorithm = NULL;
 647
 648         /* bank wasn't probed yet */
 649         cfi_info->qry[0] = -1;
 650
 651         return ERROR_OK;
 652 }
 653
 654 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 655 {
 656         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 657         target_t *target = bank->target;
 658         u8 command[8];
 659         int i;
 660
 661         cfi_intel_clear_status_register(bank);
 662
 663         for (i = first; i <= last; i++)
 664         {
 665                 cfi_command(bank, 0x20, command);
 666                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 667
 668                 cfi_command(bank, 0xd0, command);
 669                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 670
 671                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 672                         bank->sectors[i].is_erased = 1;
 673                 else
 674                 {
 675                         cfi_command(bank, 0xff, command);
 676                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 677
 678                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 679                         return ERROR_FLASH_OPERATION_FAILED;
 680                 }
 681         }
 682
 683         cfi_command(bank, 0xff, command);
 684         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 685
 686         return ERROR_OK;
 687 }
 688
 689 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 690 {
 691         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 692         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 693         target_t *target = bank->target;
 694         u8 command[8];
 695         int i;
 696
 697         for (i = first; i <= last; i++)
 698         {
 699                 cfi_command(bank, 0xaa, command);
 700                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 701
 702                 cfi_command(bank, 0x55, command);
 703                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 704
 705                 cfi_command(bank, 0x80, command);
 706                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 707
 708                 cfi_command(bank, 0xaa, command);
 709                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 710
 711                 cfi_command(bank, 0x55, command);
 712                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 713
 714                 cfi_command(bank, 0x30, command);
 715                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 716
 717                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 718                         bank->sectors[i].is_erased = 1;
 719                 else
 720                 {
 721                         cfi_command(bank, 0xf0, command);
 722                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 723
 724                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 725                         return ERROR_FLASH_OPERATION_FAILED;
 726                 }
 727         }
 728
 729         cfi_command(bank, 0xf0, command);
 730         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 731
 732         return ERROR_OK;
 733 }
 734
 735 int cfi_erase(struct flash_bank_s *bank, int first, int last)
 736 {
 737         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 738
 739         if (bank->target->state != TARGET_HALTED)
 740         {
 741                 return ERROR_TARGET_NOT_HALTED;
 742         }
 743
 744         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 745         {
 746                 return ERROR_FLASH_SECTOR_INVALID;
 747         }
 748
 749         if (cfi_info->qry[0] != 'Q')
 750                 return ERROR_FLASH_BANK_NOT_PROBED;
 751
 752         switch(cfi_info->pri_id)
 753         {
 754                 case 1:
 755                 case 3:
 756                         return cfi_intel_erase(bank, first, last);
 757                         break;
 758                 case 2:
 759                         return cfi_spansion_erase(bank, first, last);
 760                         break;
 761                 default:
 762                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 763                         break;
 764         }
 765
 766         return ERROR_OK;
 767 }
 768
 769 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 770 {
 771         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 772         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 773         target_t *target = bank->target;
 774         u8 command[8];
 775         int retry = 0;
 776         int i;
 777
 778         /* if the device supports neither legacy lock/unlock (bit 3) nor
 779          * instant individual block locking (bit 5).
 780          */
 781         if (!(pri_ext->feature_support & 0x28))
 782                 return ERROR_FLASH_OPERATION_FAILED;
 783
 784         cfi_intel_clear_status_register(bank);
 785
 786         for (i = first; i <= last; i++)
 787         {
 788                 cfi_command(bank, 0x60, command);
 789                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 790                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 791                 if (set)
 792                 {
 793                         cfi_command(bank, 0x01, command);
 794                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 795                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 796                         bank->sectors[i].is_protected = 1;
 797                 }
 798                 else
 799                 {
 800                         cfi_command(bank, 0xd0, command);
 801                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 802                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 803                         bank->sectors[i].is_protected = 0;
 804                 }
 805
 806                 /* instant individual block locking doesn't require reading of the status register */
 807                 if (!(pri_ext->feature_support & 0x20))
 808                 {
 809                         /* Clear lock bits operation may take up to 1.4s */
 810                         cfi_intel_wait_status_busy(bank, 1400);
 811                 }
 812                 else
 813                 {
 814                         u8 block_status;
 815                         /* read block lock bit, to verify status */
 816                         cfi_command(bank, 0x90, command);
 817                         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 818                         block_status = cfi_get_u8(bank, i, 0x2);
 819
 820                         if ((block_status & 0x1) != set)
 821                         {
 822                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 823                                 cfi_command(bank, 0x70, command);
 824                                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 825                                 cfi_intel_wait_status_busy(bank, 10);
 826
 827                                 if (retry > 10)
 828                                         return ERROR_FLASH_OPERATION_FAILED;
 829                                 else
 830                                 {
 831                                         i--;
 832                                         retry++;
 833                                 }
 834                         }
 835                 }
 836         }
 837
 838         /* if the device doesn't support individual block lock bits set/clear,
 839          * all blocks have been unlocked in parallel, so we set those that should be protected
 840          */
 841         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 842         {
 843                 for (i = 0; i < bank->num_sectors; i++)
 844                 {
 845                         if (bank->sectors[i].is_protected == 1)
 846                         {
 847                                 cfi_intel_clear_status_register(bank);
 848
 849                                 cfi_command(bank, 0x60, command);
 850                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 851
 852                                 cfi_command(bank, 0x01, command);
 853                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 854
 855                                 cfi_intel_wait_status_busy(bank, 100);
 856                         }
 857                 }
 858         }
 859
 860         cfi_command(bank, 0xff, command);
 861         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 862
 863         return ERROR_OK;
 864 }
 865
 866 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 867 {
 868         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 869
 870         if (bank->target->state != TARGET_HALTED)
 871         {
 872                 return ERROR_TARGET_NOT_HALTED;
 873         }
 874
 875         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 876         {
 877                 return ERROR_FLASH_SECTOR_INVALID;
 878         }
 879
 880         if (cfi_info->qry[0] != 'Q')
 881                 return ERROR_FLASH_BANK_NOT_PROBED;
 882
 883         switch(cfi_info->pri_id)
 884         {
 885                 case 1:
 886                 case 3:
 887                         cfi_intel_protect(bank, set, first, last);
 888                         break;
 889                 default:
 890                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 891                         break;
 892         }
 893
 894         return ERROR_OK;
 895 }
 896
 897 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 898 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 899 {
 900         /* target_t *target = bank->target; */
 901
 902         int i;
 903
 904         /* NOTE:
 905          * The data to flash must not be changed in endian! We write a bytestrem in
 906          * target byte order already. Only the control and status byte lane of the flash
 907          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 908          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 909          */
 910
 911 #if 0
 912         if (target->endianness == TARGET_LITTLE_ENDIAN)
 913         {
 914 #endif
 915                 /* shift bytes */
 916                 for (i = 0; i < bank->bus_width - 1; i++)
 917                         word[i] = word[i + 1];
 918                 word[bank->bus_width - 1] = byte;
 919 #if 0
 920         }
 921         else
 922         {
 923                 /* shift bytes */
 924                 for (i = bank->bus_width - 1; i > 0; i--)
 925                         word[i] = word[i - 1];
 926                 word[0] = byte;
 927         }
 928 #endif
 929 }
 930
 931 /* Convert code image to target endian */
 932 /* FIXME create general block conversion fcts in target.c?) */
 933 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
 934 {
 935         u32 i;
 936         for (i=0; i< count; i++)
 937         {
 938                 target_buffer_set_u32(target, dest, *src);
 939                 dest+=4;
 940                 src++;
 941         }
 942 }
 943
 944 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
 945 {
 946         target_t *target = bank->target;
 947
 948         u8 buf[CFI_MAX_BUS_WIDTH];
 949         cfi_command(bank, cmd, buf);
 950         switch (bank->bus_width)
 951         {
 952         case 1 :
 953                 return buf[0];
 954                 break;
 955         case 2 :
 956                 return target_buffer_get_u16(target, buf);
 957                 break;
 958         case 4 :
 959                 return target_buffer_get_u32(target, buf);
 960                 break;
 961         default :
 962                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
 963                 return 0;
 964         }
 965 }
 966
 967 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
 968 {
 969         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 970         target_t *target = bank->target;
 971         reg_param_t reg_params[7];
 972         armv4_5_algorithm_t armv4_5_info;
 973         working_area_t *source;
 974         u32 buffer_size = 32768;
 975         u32 write_command_val, busy_pattern_val, error_pattern_val;
 976
 977         /* algorithm register usage:
 978          * r0: source address (in RAM)
 979          * r1: target address (in Flash)
 980          * r2: count
 981          * r3: flash write command
 982          * r4: status byte (returned to host)
 983          * r5: busy test pattern
 984          * r6: error test pattern
 985          */
 986
 987         static const u32 word_32_code[] = {
 988                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
 989                 0xe5813000,   /*                str r3, [r1] */
 990                 0xe5814000,   /*                str r4, [r1] */
 991                 0xe5914000,   /* busy:  ldr r4, [r1] */
 992                 0xe0047005,   /*                and r7, r4, r5 */
 993                 0xe1570005,   /*                cmp r7, r5 */
 994                 0x1afffffb,   /*                bne busy */
 995                 0xe1140006,   /*                tst r4, r6 */
 996                 0x1a000003,   /*                bne done */
 997                 0xe2522001,   /*                subs r2, r2, #1 */
 998                 0x0a000001,   /*                beq done */
 999                 0xe2811004,   /*                add r1, r1 #4 */
1000                 0xeafffff2,   /*                b loop */
1001                 0xeafffffe    /* done:  b -2 */
1002         };
1003
1004         static const u32 word_16_code[] = {
1005                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1006                 0xe1c130b0,   /*                strh r3, [r1] */
1007                 0xe1c140b0,   /*                strh r4, [r1] */
1008                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1009                 0xe0047005,   /*                and r7, r4, r5 */
1010                 0xe1570005,   /*                cmp r7, r5 */
1011                 0x1afffffb,   /*                bne busy */
1012                 0xe1140006,   /*                tst r4, r6 */
1013                 0x1a000003,   /*                bne done */
1014                 0xe2522001,   /*                subs r2, r2, #1 */
1015                 0x0a000001,   /*                beq done */
1016                 0xe2811002,   /*                add r1, r1 #2 */
1017                 0xeafffff2,   /*                b loop */
1018                 0xeafffffe    /* done:  b -2 */
1019         };
1020
1021         static const u32 word_8_code[] = {
1022                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1023                 0xe5c13000,   /*                strb r3, [r1] */
1024                 0xe5c14000,   /*                strb r4, [r1] */
1025                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1026                 0xe0047005,   /*                and r7, r4, r5 */
1027                 0xe1570005,   /*                cmp r7, r5 */
1028                 0x1afffffb,   /*                bne busy */
1029                 0xe1140006,   /*                tst r4, r6 */
1030                 0x1a000003,   /*                bne done */
1031                 0xe2522001,   /*                subs r2, r2, #1 */
1032                 0x0a000001,   /*                beq done */
1033                 0xe2811001,   /*                add r1, r1 #1 */
1034                 0xeafffff2,   /*                b loop */
1035                 0xeafffffe    /* done:  b -2 */
1036         };
1037         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1038         const u32 *target_code_src;
1039         int target_code_size;
1040         int retval = ERROR_OK;
1041
1042
1043         cfi_intel_clear_status_register(bank);
1044
1045         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1046         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1047         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1048
1049         /* If we are setting up the write_algorith, we need target_code_src */
1050         /* if not we only need target_code_size.                                                                                                                */
1051         /*                                                                                                                                                                                                                                                                      */
1052         /* However, we don't want to create multiple code paths, so we                  */
1053         /* do the unecessary evaluation of target_code_src, which the                   */
1054         /* compiler will probably nicely optimize away if not needed                            */
1055
1056         /* prepare algorithm code for target endian */
1057         switch (bank->bus_width)
1058         {
1059         case 1 :
1060                 target_code_src = word_8_code;
1061                 target_code_size = sizeof(word_8_code);
1062                 break;
1063         case 2 :
1064                 target_code_src = word_16_code;
1065                 target_code_size = sizeof(word_16_code);
1066                 break;
1067         case 4 :
1068                 target_code_src = word_32_code;
1069                 target_code_size = sizeof(word_32_code);
1070                 break;
1071         default:
1072                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1073                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1074         }
1075
1076         /* flash write code */
1077         if (!cfi_info->write_algorithm)
1078         {
1079                 if ( target_code_size > sizeof(target_code) )
1080                 {
1081                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1082                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1083                 }
1084                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1085
1086                 /* Get memory for block write handler */
1087                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1088                 if (retval != ERROR_OK)
1089                 {
1090                         LOG_WARNING("No working area available, can't do block memory writes");
1091                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1092                 };
1093
1094                 /* write algorithm code to working area */
1095                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1096                 if (retval != ERROR_OK)
1097                 {
1098                         LOG_ERROR("Unable to write block write code to target");
1099                         goto cleanup;
1100                 }
1101         }
1102
1103         /* Get a workspace buffer for the data to flash starting with 32k size.
1104            Half size until buffer would be smaller 256 Bytem then fail back */
1105         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1106         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1107         {
1108                 buffer_size /= 2;
1109                 if (buffer_size <= 256)
1110                 {
1111                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1112                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1113                         goto cleanup;
1114                 }
1115         };
1116
1117         /* setup algo registers */
1118         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1119         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1120         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1121         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1122         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1123         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1124         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1125
1126         /* prepare command and status register patterns */
1127         write_command_val = cfi_command_val(bank, 0x40);
1128         busy_pattern_val  = cfi_command_val(bank, 0x80);
1129         error_pattern_val = cfi_command_val(bank, 0x7e);
1130
1131         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1132
1133         /* Programming main loop */
1134         while (count > 0)
1135         {
1136                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1137                 u32 wsm_error;
1138
1139                 target_write_buffer(target, source->address, thisrun_count, buffer);
1140
1141                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1142                 buf_set_u32(reg_params[1].value, 0, 32, address);
1143                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1144
1145                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1146                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1147                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1148
1149                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1150
1151                 /* Execute algorithm, assume breakpoint for last instruction */
1152                 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1153                         cfi_info->write_algorithm->address,
1154                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1155                         10000, /* 10s should be enough for max. 32k of data */
1156                         &armv4_5_info);
1157
1158                 /* On failure try a fall back to direct word writes */
1159                 if (retval != ERROR_OK)
1160                 {
1161                         cfi_intel_clear_status_register(bank);
1162                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1163                         retval = ERROR_FLASH_OPERATION_FAILED;
1164                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1165                         /* FIXME To allow fall back or recovery, we must save the actual status
1166                            somewhere, so that a higher level code can start recovery. */
1167                         goto cleanup;
1168                 }
1169
1170                 /* Check return value from algo code */
1171                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1172                 if (wsm_error)
1173                 {
1174                         /* read status register (outputs debug inforation) */
1175                         cfi_intel_wait_status_busy(bank, 100);
1176                         cfi_intel_clear_status_register(bank);
1177                         retval = ERROR_FLASH_OPERATION_FAILED;
1178                         goto cleanup;
1179                 }
1180
1181                 buffer += thisrun_count;
1182                 address += thisrun_count;
1183                 count -= thisrun_count;
1184         }
1185
1186         /* free up resources */
1187 cleanup:
1188         if (source)
1189                 target_free_working_area(target, source);
1190
1191         if (cfi_info->write_algorithm)
1192         {
1193                 target_free_working_area(target, cfi_info->write_algorithm);
1194                 cfi_info->write_algorithm = NULL;
1195         }
1196
1197         destroy_reg_param(&reg_params[0]);
1198         destroy_reg_param(&reg_params[1]);
1199         destroy_reg_param(&reg_params[2]);
1200         destroy_reg_param(&reg_params[3]);
1201         destroy_reg_param(&reg_params[4]);
1202         destroy_reg_param(&reg_params[5]);
1203         destroy_reg_param(&reg_params[6]);
1204
1205         return retval;
1206 }
1207
1208 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1209 {
1210         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1211         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1212         target_t *target = bank->target;
1213         reg_param_t reg_params[10];
1214         armv4_5_algorithm_t armv4_5_info;
1215         working_area_t *source;
1216         u32 buffer_size = 32768;
1217         u32 status;
1218         int retval;
1219         int exit_code = ERROR_OK;
1220
1221         /* input parameters - */
1222         /*      R0 = source address */
1223         /*      R1 = destination address */
1224         /*      R2 = number of writes */
1225         /*      R3 = flash write command */
1226         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1227         /* output parameters - */
1228         /*      R5 = 0x80 ok 0x00 bad */
1229         /* temp registers - */
1230         /*      R6 = value read from flash to test status */
1231         /*      R7 = holding register */
1232         /* unlock registers - */
1233         /*  R8 = unlock1_addr */
1234         /*  R9 = unlock1_cmd */
1235         /*  R10 = unlock2_addr */
1236         /*  R11 = unlock2_cmd */
1237
1238         static const u32 word_32_code[] = {
1239                                                 /* 00008100 <sp_32_code>:               */
1240                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1241                 0xe5889000,     /* str  r9, [r8]                                */
1242                 0xe58ab000,     /* str  r11, [r10]                              */
1243                 0xe5883000,     /* str  r3, [r8]                                */
1244                 0xe5815000,     /* str  r5, [r1]                                */
1245                 0xe1a00000,     /* nop                                                  */
1246                                                 /*                                                              */
1247                                                 /* 00008110 <sp_32_busy>:               */
1248                 0xe5916000,     /* ldr  r6, [r1]                                */
1249                 0xe0257006,     /* eor  r7, r5, r6                              */
1250                 0xe0147007,     /* ands r7, r4, r7                              */
1251                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1252                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1253                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1254                 0xe5916000,     /* ldr  r6, [r1]                                */
1255                 0xe0257006,     /* eor  r7, r5, r6                              */
1256                 0xe0147007,     /* ands r7, r4, r7                              */
1257                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1258                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1259                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1260                                                 /*                                                              */
1261                                 /* 00008140 <sp_32_cont>:                               */
1262                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1263                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1264                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1265                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1266                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1267                                                 /*                                                              */
1268                                                 /* 00008154 <sp_32_done>:               */
1269                 0xeafffffe              /* b    8154 <sp_32_done>               */
1270                 };
1271
1272                 static const u32 word_16_code[] = {
1273                                 /* 00008158 <sp_16_code>:              */
1274                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1275                 0xe1c890b0,     /* strh r9, [r8]                                */
1276                 0xe1cab0b0,     /* strh r11, [r10]                              */
1277                 0xe1c830b0,     /* strh r3, [r8]                                */
1278                 0xe1c150b0,     /* strh r5, [r1]                       */
1279                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1280                                 /*                                     */
1281                                 /* 00008168 <sp_16_busy>:              */
1282                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1283                 0xe0257006,     /* eor  r7, r5, r6                     */
1284                 0xe0147007,     /* ands r7, r4, r7                     */
1285                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1286                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1287                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1288                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1289                 0xe0257006,     /* eor  r7, r5, r6                     */
1290                 0xe0147007,     /* ands r7, r4, r7                     */
1291                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1292                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1293                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1294                                 /*                                     */
1295                                 /* 00008198 <sp_16_cont>:              */
1296                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1297                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1298                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1299                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1300                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1301                                 /*                                     */
1302                                 /* 000081ac <sp_16_done>:              */
1303                 0xeafffffe      /* b    81ac <sp_16_done>              */
1304                 };
1305
1306                 static const u32 word_8_code[] = {
1307                                 /* 000081b0 <sp_16_code_end>:          */
1308                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1309                 0xe5c89000,     /* strb r9, [r8]                                */
1310                 0xe5cab000,     /* strb r11, [r10]                              */
1311                 0xe5c83000,     /* strb r3, [r8]                                */
1312                 0xe5c15000,     /* strb r5, [r1]                       */
1313                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1314                                 /*                                     */
1315                                 /* 000081c0 <sp_8_busy>:               */
1316                 0xe5d16000,     /* ldrb r6, [r1]                       */
1317                 0xe0257006,     /* eor  r7, r5, r6                     */
1318                 0xe0147007,     /* ands r7, r4, r7                     */
1319                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1320                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1321                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1322                 0xe5d16000,     /* ldrb r6, [r1]                       */
1323                 0xe0257006,     /* eor  r7, r5, r6                     */
1324                 0xe0147007,     /* ands r7, r4, r7                     */
1325                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1326                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1327                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1328                                 /*                                     */
1329                                 /* 000081f0 <sp_8_cont>:               */
1330                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1331                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1332                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1333                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1334                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1335                                 /*                                     */
1336                                 /* 00008204 <sp_8_done>:               */
1337                 0xeafffffe      /* b    8204 <sp_8_done>               */
1338         };
1339
1340         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1341         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1342         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1343
1344         /* flash write code */
1345         if (!cfi_info->write_algorithm)
1346         {
1347                 u8 *target_code;
1348                 int target_code_size;
1349                 const u32 *src;
1350
1351                 /* convert bus-width dependent algorithm code to correct endiannes */
1352                 switch (bank->bus_width)
1353                 {
1354                 case 1:
1355                         src = word_8_code;
1356                         target_code_size = sizeof(word_8_code);
1357                         break;
1358                 case 2:
1359                         src = word_16_code;
1360                         target_code_size = sizeof(word_16_code);
1361                         break;
1362                 case 4:
1363                         src = word_32_code;
1364                         target_code_size = sizeof(word_32_code);
1365                         break;
1366                 default:
1367                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1368                         return ERROR_FLASH_OPERATION_FAILED;
1369                 }
1370                 target_code = malloc(target_code_size);
1371                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1372
1373                 /* allocate working area */
1374                 retval=target_alloc_working_area(target, target_code_size,
1375                                 &cfi_info->write_algorithm);
1376                 if (retval != ERROR_OK)
1377                         return retval;
1378
1379                 /* write algorithm code to working area */
1380                 target_write_buffer(target, cfi_info->write_algorithm->address,
1381                                     target_code_size, target_code);
1382
1383                 free(target_code);
1384         }
1385         /* the following code still assumes target code is fixed 24*4 bytes */
1386
1387         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1388         {
1389                 buffer_size /= 2;
1390                 if (buffer_size <= 256)
1391                 {
1392                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1393                         if (cfi_info->write_algorithm)
1394                                 target_free_working_area(target, cfi_info->write_algorithm);
1395
1396                         LOG_WARNING("not enough working area available, can't do block memory writes");
1397                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1398                 }
1399         };
1400
1401         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1402         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1403         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1404         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1405         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1406         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1407         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1408         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1409         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1410         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1411
1412         while (count > 0)
1413         {
1414                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1415
1416                 target_write_buffer(target, source->address, thisrun_count, buffer);
1417
1418                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1419                 buf_set_u32(reg_params[1].value, 0, 32, address);
1420                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1421                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1422                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1423                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1424                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1425                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1426                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1427
1428                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1429                                                      cfi_info->write_algorithm->address,
1430                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1431                                                      10000, &armv4_5_info);
1432
1433                 status = buf_get_u32(reg_params[5].value, 0, 32);
1434
1435                 if ((retval != ERROR_OK) || status != 0x80)
1436                 {
1437                         LOG_DEBUG("status: 0x%x", status);
1438                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1439                         break;
1440                 }
1441
1442                 buffer += thisrun_count;
1443                 address += thisrun_count;
1444                 count -= thisrun_count;
1445         }
1446
1447         target_free_working_area(target, source);
1448
1449         destroy_reg_param(&reg_params[0]);
1450         destroy_reg_param(&reg_params[1]);
1451         destroy_reg_param(&reg_params[2]);
1452         destroy_reg_param(&reg_params[3]);
1453         destroy_reg_param(&reg_params[4]);
1454         destroy_reg_param(&reg_params[5]);
1455         destroy_reg_param(&reg_params[6]);
1456         destroy_reg_param(&reg_params[7]);
1457         destroy_reg_param(&reg_params[8]);
1458         destroy_reg_param(&reg_params[9]);
1459
1460         return exit_code;
1461 }
1462
1463 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1464 {
1465         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1466         target_t *target = bank->target;
1467         u8 command[8];
1468
1469         cfi_intel_clear_status_register(bank);
1470         cfi_command(bank, 0x40, command);
1471         target->type->write_memory(target, address, bank->bus_width, 1, command);
1472
1473         target->type->write_memory(target, address, bank->bus_width, 1, word);
1474
1475         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1476         {
1477                 cfi_command(bank, 0xff, command);
1478                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1479
1480                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1481                 return ERROR_FLASH_OPERATION_FAILED;
1482         }
1483
1484         return ERROR_OK;
1485 }
1486
1487 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1488 {
1489         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1490         target_t *target = bank->target;
1491         u8 command[8];
1492
1493         /* Calculate buffer size and boundary mask */
1494         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1495         u32 buffermask = buffersize-1;
1496         u32 bufferwsize;
1497
1498         /* Check for valid range */
1499         if (address & buffermask)
1500         {
1501                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1502                 return ERROR_FLASH_OPERATION_FAILED;
1503         }
1504         switch(bank->chip_width)
1505         {
1506         case 4 : bufferwsize = buffersize / 4; break;
1507         case 2 : bufferwsize = buffersize / 2; break;
1508         case 1 : bufferwsize = buffersize; break;
1509         default:
1510                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1511                 return ERROR_FLASH_OPERATION_FAILED;
1512         }
1513
1514         /* Check for valid size */
1515         if (wordcount > bufferwsize)
1516         {
1517                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1518                 return ERROR_FLASH_OPERATION_FAILED;
1519         }
1520
1521         /* Write to flash buffer */
1522         cfi_intel_clear_status_register(bank);
1523
1524         /* Initiate buffer operation _*/
1525         cfi_command(bank, 0xE8, command);
1526         target->type->write_memory(target, address, bank->bus_width, 1, command);
1527         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1528         {
1529                 cfi_command(bank, 0xff, command);
1530                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1531
1532                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1533                 return ERROR_FLASH_OPERATION_FAILED;
1534         }
1535
1536         /* Write buffer wordcount-1 and data words */
1537         cfi_command(bank, bufferwsize-1, command);
1538         target->type->write_memory(target, address, bank->bus_width, 1, command);
1539
1540         target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1541
1542         /* Commit write operation */
1543         cfi_command(bank, 0xd0, command);
1544         target->type->write_memory(target, address, bank->bus_width, 1, command);
1545         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1546         {
1547                 cfi_command(bank, 0xff, command);
1548                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1549
1550                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1551                 return ERROR_FLASH_OPERATION_FAILED;
1552         }
1553
1554         return ERROR_OK;
1555 }
1556
1557 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1558 {
1559         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1560         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1561         target_t *target = bank->target;
1562         u8 command[8];
1563
1564         cfi_command(bank, 0xaa, command);
1565         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1566
1567         cfi_command(bank, 0x55, command);
1568         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1569
1570         cfi_command(bank, 0xa0, command);
1571         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1572
1573         target->type->write_memory(target, address, bank->bus_width, 1, word);
1574
1575         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1576         {
1577                 cfi_command(bank, 0xf0, command);
1578                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1579
1580                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1581                 return ERROR_FLASH_OPERATION_FAILED;
1582         }
1583
1584         return ERROR_OK;
1585 }
1586
1587 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1588 {
1589         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1590
1591         switch(cfi_info->pri_id)
1592         {
1593                 case 1:
1594                 case 3:
1595                         return cfi_intel_write_word(bank, word, address);
1596                         break;
1597                 case 2:
1598                         return cfi_spansion_write_word(bank, word, address);
1599                         break;
1600                 default:
1601                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1602                         break;
1603         }
1604
1605         return ERROR_FLASH_OPERATION_FAILED;
1606 }
1607
1608 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1609 {
1610         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1611
1612         switch(cfi_info->pri_id)
1613         {
1614                 case 1:
1615                 case 3:
1616                         return cfi_intel_write_words(bank, word, wordcount, address);
1617                         break;
1618                 case 2:
1619                         /* return cfi_spansion_write_words(bank, word, address); */
1620                         LOG_ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
1621                         break;
1622                 default:
1623                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1624                         break;
1625         }
1626
1627         return ERROR_FLASH_OPERATION_FAILED;
1628 }
1629
1630 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1631 {
1632         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1633         target_t *target = bank->target;
1634         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1635         u32 write_p, copy_p;
1636         int align;      /* number of unaligned bytes */
1637         int blk_count; /* number of bus_width bytes for block copy */
1638         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1639         int i;
1640         int retval;
1641
1642         if (bank->target->state != TARGET_HALTED)
1643                 return ERROR_TARGET_NOT_HALTED;
1644
1645         if (offset + count > bank->size)
1646                 return ERROR_FLASH_DST_OUT_OF_BANK;
1647
1648         if (cfi_info->qry[0] != 'Q')
1649                 return ERROR_FLASH_BANK_NOT_PROBED;
1650
1651         /* start at the first byte of the first word (bus_width size) */
1652         write_p = address & ~(bank->bus_width - 1);
1653         if ((align = address - write_p) != 0)
1654         {
1655                 LOG_INFO("Fixup %d unaligned head bytes", align );
1656
1657                 for (i = 0; i < bank->bus_width; i++)
1658                         current_word[i] = 0;
1659                 copy_p = write_p;
1660
1661                 /* copy bytes before the first write address */
1662                 for (i = 0; i < align; ++i, ++copy_p)
1663                 {
1664                         u8 byte;
1665                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1666                         cfi_add_byte(bank, current_word, byte);
1667                 }
1668
1669                 /* add bytes from the buffer */
1670                 for (; (i < bank->bus_width) && (count > 0); i++)
1671                 {
1672                         cfi_add_byte(bank, current_word, *buffer++);
1673                         count--;
1674                         copy_p++;
1675                 }
1676
1677                 /* if the buffer is already finished, copy bytes after the last write address */
1678                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1679                 {
1680                         u8 byte;
1681                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1682                         cfi_add_byte(bank, current_word, byte);
1683                 }
1684
1685                 retval = cfi_write_word(bank, current_word, write_p);
1686                 if (retval != ERROR_OK)
1687                         return retval;
1688                 write_p = copy_p;
1689         }
1690
1691         /* handle blocks of bus_size aligned bytes */
1692         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1693         switch(cfi_info->pri_id)
1694         {
1695                 /* try block writes (fails without working area) */
1696                 case 1:
1697                 case 3:
1698                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1699                         break;
1700                 case 2:
1701                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1702                         break;
1703                 default:
1704                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1705                         retval = ERROR_FLASH_OPERATION_FAILED;
1706                         break;
1707         }
1708         if (retval == ERROR_OK)
1709         {
1710                 /* Increment pointers and decrease count on succesful block write */
1711                 buffer += blk_count;
1712                 write_p += blk_count;
1713                 count -= blk_count;
1714         }
1715         else
1716         {
1717                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1718                 {
1719                         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1720                         u32 buffermask = buffersize-1;
1721                         u32 bufferwsize;
1722
1723                         switch(bank->chip_width)
1724                         {
1725                         case 4 : bufferwsize = buffersize / 4; break;
1726                         case 2 : bufferwsize = buffersize / 2; break;
1727                         case 1 : bufferwsize = buffersize; break;
1728                         default:
1729                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1730                                 return ERROR_FLASH_OPERATION_FAILED;
1731                         }
1732
1733                         /* fall back to memory writes */
1734                         while (count >= bank->bus_width)
1735                         {
1736                                 if ((write_p & 0xff) == 0)
1737                                 {
1738                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1739                                 }
1740                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1741                                 {
1742                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1743                                         if (retval != ERROR_OK)
1744                                                 return retval;
1745
1746                                         buffer += buffersize;
1747                                         write_p += buffersize;
1748                                         count -= buffersize;
1749                                 }
1750                                 else
1751                                 {
1752                                         for (i = 0; i < bank->bus_width; i++)
1753                                                 current_word[i] = 0;
1754
1755                                         for (i = 0; i < bank->bus_width; i++)
1756                                         {
1757                                                 cfi_add_byte(bank, current_word, *buffer++);
1758                                         }
1759
1760                                         retval = cfi_write_word(bank, current_word, write_p);
1761                                         if (retval != ERROR_OK)
1762                                                 return retval;
1763
1764                                         write_p += bank->bus_width;
1765                                         count -= bank->bus_width;
1766                                 }
1767                         }
1768                 }
1769                 else
1770                         return retval;
1771         }
1772
1773         /* return to read array mode, so we can read from flash again for padding */
1774         cfi_command(bank, 0xf0, current_word);
1775         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1776         cfi_command(bank, 0xff, current_word);
1777         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1778
1779         /* handle unaligned tail bytes */
1780         if (count > 0)
1781         {
1782                 LOG_INFO("Fixup %d unaligned tail bytes", count );
1783
1784                 copy_p = write_p;
1785                 for (i = 0; i < bank->bus_width; i++)
1786                         current_word[i] = 0;
1787
1788                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1789                 {
1790                         cfi_add_byte(bank, current_word, *buffer++);
1791                         count--;
1792                 }
1793                 for (; i < bank->bus_width; ++i, ++copy_p)
1794                 {
1795                         u8 byte;
1796                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1797                         cfi_add_byte(bank, current_word, byte);
1798                 }
1799                 retval = cfi_write_word(bank, current_word, write_p);
1800                 if (retval != ERROR_OK)
1801                         return retval;
1802         }
1803
1804         /* return to read array mode */
1805         cfi_command(bank, 0xf0, current_word);
1806         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1807         cfi_command(bank, 0xff, current_word);
1808         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1809
1810         return ERROR_OK;
1811 }
1812
1813 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1814 {
1815         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1816         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1817
1818         pri_ext->_reversed_geometry = 1;
1819 }
1820
1821 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1822 {
1823         int i;
1824         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1825         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1826
1827         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1828         {
1829                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
1830
1831                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1832                 {
1833                         int j = (cfi_info->num_erase_regions - 1) - i;
1834                         u32 swap;
1835
1836                         swap = cfi_info->erase_region_info[i];
1837                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1838                         cfi_info->erase_region_info[j] = swap;
1839                 }
1840         }
1841 }
1842
1843 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1844 {
1845         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1846         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1847         cfi_unlock_addresses_t *unlock_addresses = param;
1848
1849         pri_ext->_unlock1 = unlock_addresses->unlock1;
1850         pri_ext->_unlock2 = unlock_addresses->unlock2;
1851 }
1852
1853 int cfi_probe(struct flash_bank_s *bank)
1854 {
1855         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1856         target_t *target = bank->target;
1857         u8 command[8];
1858         int num_sectors = 0;
1859         int i;
1860         int sector = 0;
1861         u32 offset = 0;
1862         u32 unlock1 = 0x555;
1863         u32 unlock2 = 0x2aa;
1864
1865         if (bank->target->state != TARGET_HALTED)
1866         {
1867                 return ERROR_TARGET_NOT_HALTED;
1868         }
1869
1870         cfi_info->probed = 0;
1871
1872         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1873          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1874          */
1875         if (cfi_info->jedec_probe)
1876         {
1877                 unlock1 = 0x5555;
1878                 unlock2 = 0x2aaa;
1879         }
1880
1881         /* switch to read identifier codes mode ("AUTOSELECT") */
1882         cfi_command(bank, 0xaa, command);
1883         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1884         cfi_command(bank, 0x55, command);
1885         target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1886         cfi_command(bank, 0x90, command);
1887         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1888
1889         if (bank->chip_width == 1)
1890         {
1891                 u8 manufacturer, device_id;
1892                 target_read_u8(target, bank->base + 0x0, &manufacturer);
1893                 target_read_u8(target, bank->base + 0x1, &device_id);
1894                 cfi_info->manufacturer = manufacturer;
1895                 cfi_info->device_id = device_id;
1896         }
1897         else if (bank->chip_width == 2)
1898         {
1899                 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1900                 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1901         }
1902
1903         /* switch back to read array mode */
1904         cfi_command(bank, 0xf0, command);
1905         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1906         cfi_command(bank, 0xff, command);
1907         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1908
1909         cfi_fixup(bank, cfi_jedec_fixups);
1910
1911         /* query only if this is a CFI compatible flash,
1912          * otherwise the relevant info has already been filled in
1913          */
1914         if (cfi_info->not_cfi == 0)
1915         {
1916                 /* enter CFI query mode
1917                  * according to JEDEC Standard No. 68.01,
1918                  * a single bus sequence with address = 0x55, data = 0x98 should put
1919                  * the device into CFI query mode.
1920                  *
1921                  * SST flashes clearly violate this, and we will consider them incompatbile for now
1922                  */
1923                 cfi_command(bank, 0x98, command);
1924                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1925
1926                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1927                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1928                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1929
1930                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1931
1932                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1933                 {
1934                         cfi_command(bank, 0xf0, command);
1935                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1936                         cfi_command(bank, 0xff, command);
1937                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1938                         return ERROR_FLASH_BANK_INVALID;
1939                 }
1940
1941                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1942                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1943                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1944                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1945
1946                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1947
1948                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1949                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1950                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1951                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1952                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1953                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1954                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1955                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1956                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1957                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1958                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1959                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1960
1961                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1962                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1963                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1964                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1965                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1966                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1967                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1968                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1969                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1970                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1971                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1972
1973                 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1974                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1975                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1976                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1977
1978                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1979
1980                 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1981                 {
1982                         LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1983                 }
1984
1985                 if (cfi_info->num_erase_regions)
1986                 {
1987                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
1988                         for (i = 0; i < cfi_info->num_erase_regions; i++)
1989                         {
1990                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
1991                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
1992                         }
1993                 }
1994                 else
1995                 {
1996                         cfi_info->erase_region_info = NULL;
1997                 }
1998
1999                 /* We need to read the primary algorithm extended query table before calculating
2000                  * the sector layout to be able to apply fixups
2001                  */
2002                 switch(cfi_info->pri_id)
2003                 {
2004                         /* Intel command set (standard and extended) */
2005                         case 0x0001:
2006                         case 0x0003:
2007                                 cfi_read_intel_pri_ext(bank);
2008                                 break;
2009                         /* AMD/Spansion, Atmel, ... command set */
2010                         case 0x0002:
2011                                 cfi_read_0002_pri_ext(bank);
2012                                 break;
2013                         default:
2014                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2015                                 break;
2016                 }
2017
2018                 /* return to read array mode
2019                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2020                  */
2021                 cfi_command(bank, 0xf0, command);
2022                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2023                 cfi_command(bank, 0xff, command);
2024                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2025         }
2026
2027         /* apply fixups depending on the primary command set */
2028         switch(cfi_info->pri_id)
2029         {
2030                 /* Intel command set (standard and extended) */
2031                 case 0x0001:
2032                 case 0x0003:
2033                         cfi_fixup(bank, cfi_0001_fixups);
2034                         break;
2035                 /* AMD/Spansion, Atmel, ... command set */
2036                 case 0x0002:
2037                         cfi_fixup(bank, cfi_0002_fixups);
2038                         break;
2039                 default:
2040                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2041                         break;
2042         }
2043
2044         if (cfi_info->num_erase_regions == 0)
2045         {
2046                 /* a device might have only one erase block, spanning the whole device */
2047                 bank->num_sectors = 1;
2048                 bank->sectors = malloc(sizeof(flash_sector_t));
2049
2050                 bank->sectors[sector].offset = 0x0;
2051                 bank->sectors[sector].size = bank->size;
2052                 bank->sectors[sector].is_erased = -1;
2053                 bank->sectors[sector].is_protected = -1;
2054         }
2055         else
2056         {
2057                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2058                 {
2059                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2060                 }
2061
2062                 bank->num_sectors = num_sectors;
2063                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2064
2065                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2066                 {
2067                         int j;
2068                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2069                         {
2070                                 bank->sectors[sector].offset = offset;
2071                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2072                                 offset += bank->sectors[sector].size;
2073                                 bank->sectors[sector].is_erased = -1;
2074                                 bank->sectors[sector].is_protected = -1;
2075                                 sector++;
2076                         }
2077                 }
2078         }
2079
2080         cfi_info->probed = 1;
2081
2082         return ERROR_OK;
2083 }
2084
2085 int cfi_auto_probe(struct flash_bank_s *bank)
2086 {
2087         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2088         if (cfi_info->probed)
2089                 return ERROR_OK;
2090         return cfi_probe(bank);
2091 }
2092
2093
2094 int cfi_intel_protect_check(struct flash_bank_s *bank)
2095 {
2096         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2097         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2098         target_t *target = bank->target;
2099         u8 command[CFI_MAX_BUS_WIDTH];
2100         int i;
2101
2102         /* check if block lock bits are supported on this device */
2103         if (!(pri_ext->blk_status_reg_mask & 0x1))
2104                 return ERROR_FLASH_OPERATION_FAILED;
2105
2106         cfi_command(bank, 0x90, command);
2107         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2108
2109         for (i = 0; i < bank->num_sectors; i++)
2110         {
2111                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2112
2113                 if (block_status & 1)
2114                         bank->sectors[i].is_protected = 1;
2115                 else
2116                         bank->sectors[i].is_protected = 0;
2117         }
2118
2119         cfi_command(bank, 0xff, command);
2120         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2121
2122         return ERROR_OK;
2123 }
2124
2125 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2126 {
2127         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2128         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2129         target_t *target = bank->target;
2130         u8 command[8];
2131         int i;
2132
2133         cfi_command(bank, 0xaa, command);
2134         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2135
2136         cfi_command(bank, 0x55, command);
2137         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2138
2139         cfi_command(bank, 0x90, command);
2140         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2141
2142         for (i = 0; i < bank->num_sectors; i++)
2143         {
2144                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2145
2146                 if (block_status & 1)
2147                         bank->sectors[i].is_protected = 1;
2148                 else
2149                         bank->sectors[i].is_protected = 0;
2150         }
2151
2152         cfi_command(bank, 0xf0, command);
2153         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2154
2155         return ERROR_OK;
2156 }
2157
2158 int cfi_protect_check(struct flash_bank_s *bank)
2159 {
2160         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2161
2162         if (bank->target->state != TARGET_HALTED)
2163         {
2164                 return ERROR_TARGET_NOT_HALTED;
2165         }
2166
2167         if (cfi_info->qry[0] != 'Q')
2168                 return ERROR_FLASH_BANK_NOT_PROBED;
2169
2170         switch(cfi_info->pri_id)
2171         {
2172                 case 1:
2173                 case 3:
2174                         return cfi_intel_protect_check(bank);
2175                         break;
2176                 case 2:
2177                         return cfi_spansion_protect_check(bank);
2178                         break;
2179                 default:
2180                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2181                         break;
2182         }
2183
2184         return ERROR_OK;
2185 }
2186
2187 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2188 {
2189         int printed;
2190         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2191
2192         if (cfi_info->qry[0] == (char)-1)
2193         {
2194                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2195                 return ERROR_OK;
2196         }
2197
2198         if (cfi_info->not_cfi == 0)
2199         printed = snprintf(buf, buf_size, "\ncfi information:\n");
2200         else
2201                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2202         buf += printed;
2203         buf_size -= printed;
2204
2205         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2206                 cfi_info->manufacturer, cfi_info->device_id);
2207         buf += printed;
2208         buf_size -= printed;
2209
2210         if (cfi_info->not_cfi == 0)
2211         {
2212         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2213         buf += printed;
2214         buf_size -= printed;
2215
2216                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2217                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2218         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2219         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2220         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2221         buf += printed;
2222         buf_size -= printed;
2223
2224                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2225                                    1 << cfi_info->word_write_timeout_typ,
2226                                    1 << cfi_info->buf_write_timeout_typ,
2227                                    1 << cfi_info->block_erase_timeout_typ,
2228                                    1 << cfi_info->chip_erase_timeout_typ);
2229         buf += printed;
2230         buf_size -= printed;
2231
2232                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2233                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2234                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2235                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2236                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2237         buf += printed;
2238         buf_size -= printed;
2239
2240                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2241                                    1 << cfi_info->dev_size,
2242                                    cfi_info->interface_desc,
2243                                    cfi_info->max_buf_write_size);
2244         buf += printed;
2245         buf_size -= printed;
2246
2247         switch(cfi_info->pri_id)
2248         {
2249                 case 1:
2250                 case 3:
2251                         cfi_intel_info(bank, buf, buf_size);
2252                         break;
2253                 case 2:
2254                         cfi_spansion_info(bank, buf, buf_size);
2255                         break;
2256                 default:
2257                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2258                         break;
2259         }
2260         }
2261
2262         return ERROR_OK;
2263 }