git.sur5r.net Git - openocd/blob - src/flash/cfi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   This program is free software; you can redistribute it and/or modify  *
   6  *   it under the terms of the GNU General Public License as published by  *
   7  *   the Free Software Foundation; either version 2 of the License, or     *
   8  *   (at your option) any later version.                                   *
   9  *                                                                         *
  10  *   This program is distributed in the hope that it will be useful,       *
  11  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  12  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  13  *   GNU General Public License for more details.                          *
  14  *                                                                         *
  15  *   You should have received a copy of the GNU General Public License     *
  16  *   along with this program; if not, write to the                         *
  17  *   Free Software Foundation, Inc.,                                       *
  18  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  19  ***************************************************************************/
  20 #ifdef HAVE_CONFIG_H
  21 #include "config.h"
  22 #endif
  23
  24 #include "replacements.h"
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28
  29 #include "flash.h"
  30 #include "target.h"
  31 #include "log.h"
  32 #include "armv4_5.h"
  33 #include "algorithm.h"
  34 #include "binarybuffer.h"
  35 #include "types.h"
  36
  37 #include <stdlib.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40
  41 int cfi_register_commands(struct command_context_s *cmd_ctx);
  42 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  43 int cfi_erase(struct flash_bank_s *bank, int first, int last);
  44 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  45 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  46 int cfi_probe(struct flash_bank_s *bank);
  47 int cfi_auto_probe(struct flash_bank_s *bank);
  48 int cfi_protect_check(struct flash_bank_s *bank);
  49 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  50
  51 int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  52
  53 #define CFI_MAX_BUS_WIDTH       4
  54 #define CFI_MAX_CHIP_WIDTH      4
  55
  56 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  57 #define CFI_MAX_INTEL_CODESIZE 256
  58
  59 flash_driver_t cfi_flash =
  60 {
  61         .name = "cfi",
  62         .register_commands = cfi_register_commands,
  63         .flash_bank_command = cfi_flash_bank_command,
  64         .erase = cfi_erase,
  65         .protect = cfi_protect,
  66         .write = cfi_write,
  67         .probe = cfi_probe,
  68         .auto_probe = cfi_auto_probe,
  69         .erase_check = default_flash_blank_check,
  70         .protect_check = cfi_protect_check,
  71         .info = cfi_info
  72 };
  73
  74 cfi_unlock_addresses_t cfi_unlock_addresses[] =
  75 {
  76         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  77         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  78 };
  79
  80 /* CFI fixups foward declarations */
  81 void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  82 void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  83 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  84
  85 /* fixup after identifying JEDEC manufactuer and ID */
  86 cfi_fixup_t cfi_jedec_fixups[] = {
  87         {CFI_MFR_SST, 0x00D4, cfi_fixup_non_cfi, NULL},
  88         {CFI_MFR_SST, 0x00D5, cfi_fixup_non_cfi, NULL},
  89         {CFI_MFR_SST, 0x00D6, cfi_fixup_non_cfi, NULL},
  90         {CFI_MFR_SST, 0x00D7, cfi_fixup_non_cfi, NULL},
  91         {CFI_MFR_SST, 0x2780, cfi_fixup_non_cfi, NULL},
  92         {CFI_MFR_ST, 0x00D5, cfi_fixup_non_cfi, NULL},
  93         {CFI_MFR_ST, 0x00D6, cfi_fixup_non_cfi, NULL},
  94         {CFI_MFR_AMD, 0x2223, cfi_fixup_non_cfi, NULL},
  95         {CFI_MFR_AMD, 0x22ab, cfi_fixup_non_cfi, NULL},
  96         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_non_cfi, NULL},
  97         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_non_cfi, NULL},
  98         {CFI_MFR_MX, 0x225b, cfi_fixup_non_cfi, NULL},
  99         {0, 0, NULL, NULL}
 100 };
 101
 102 /* fixup after reading cmdset 0002 primary query table */
 103 cfi_fixup_t cfi_0002_fixups[] = {
 104         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 105         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 106         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 107         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 108         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 109         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
 110         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 111         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
 112         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
 113         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
 114         {0, 0, NULL, NULL}
 115 };
 116
 117 /* fixup after reading cmdset 0001 primary query table */
 118 cfi_fixup_t cfi_0001_fixups[] = {
 119         {0, 0, NULL, NULL}
 120 };
 121
 122 void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
 123 {
 124         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 125         cfi_fixup_t *f;
 126
 127         for (f = fixups; f->fixup; f++)
 128         {
 129                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 130                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 131                 {
 132                         f->fixup(bank, f->param);
 133                 }
 134         }
 135 }
 136
 137 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 138 __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 139 {
 140         /* while the sector list isn't built, only accesses to sector 0 work */
 141         if (sector == 0)
 142                 return bank->base + offset * bank->bus_width;
 143         else
 144         {
 145                 if (!bank->sectors)
 146                 {
 147                         LOG_ERROR("BUG: sector list not yet built");
 148                         exit(-1);
 149                 }
 150                 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
 151         }
 152
 153 }
 154
 155 void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 156 {
 157         int i;
 158
 159         /* clear whole buffer, to ensure bits that exceed the bus_width
 160          * are set to zero
 161          */
 162         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 163                 cmd_buf[i] = 0;
 164
 165         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 166         {
 167                 for (i = bank->bus_width; i > 0; i--)
 168                 {
 169                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 170                 }
 171         }
 172         else
 173         {
 174                 for (i = 1; i <= bank->bus_width; i++)
 175                 {
 176                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 177                 }
 178         }
 179 }
 180
 181 /* read unsigned 8-bit value from the bank
 182  * flash banks are expected to be made of similar chips
 183  * the query result should be the same for all
 184  */
 185 u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 186 {
 187         target_t *target = bank->target;
 188         u8 data[CFI_MAX_BUS_WIDTH];
 189
 190         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 191
 192         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 193                 return data[0];
 194         else
 195                 return data[bank->bus_width - 1];
 196 }
 197
 198 /* read unsigned 8-bit value from the bank
 199  * in case of a bank made of multiple chips,
 200  * the individual values are ORed
 201  */
 202 u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 203 {
 204         target_t *target = bank->target;
 205         u8 data[CFI_MAX_BUS_WIDTH];
 206         int i;
 207
 208         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 209
 210         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 211         {
 212                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 213                         data[0] |= data[i];
 214
 215                 return data[0];
 216         }
 217         else
 218         {
 219                 u8 value = 0;
 220                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 221                         value |= data[bank->bus_width - 1 - i];
 222
 223                 return value;
 224         }
 225 }
 226
 227 u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 228 {
 229         target_t *target = bank->target;
 230         u8 data[CFI_MAX_BUS_WIDTH * 2];
 231
 232         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 233
 234         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 235                 return data[0] | data[bank->bus_width] << 8;
 236         else
 237                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 238 }
 239
 240 u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 241 {
 242         target_t *target = bank->target;
 243         u8 data[CFI_MAX_BUS_WIDTH * 4];
 244
 245         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 246
 247         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 248                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 249         else
 250                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 251                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 252 }
 253
 254 void cfi_intel_clear_status_register(flash_bank_t *bank)
 255 {
 256         target_t *target = bank->target;
 257         u8 command[8];
 258
 259         if (target->state != TARGET_HALTED)
 260         {
 261                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 262                 exit(-1);
 263         }
 264
 265         cfi_command(bank, 0x50, command);
 266         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 267 }
 268
 269 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 270 {
 271         u8 status;
 272
 273         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 274         {
 275                 LOG_DEBUG("status: 0x%x", status);
 276                 usleep(1000);
 277         }
 278
 279         /* mask out bit 0 (reserved) */
 280         status = status & 0xfe;
 281
 282         LOG_DEBUG("status: 0x%x", status);
 283
 284         if ((status & 0x80) != 0x80)
 285         {
 286                 LOG_ERROR("timeout while waiting for WSM to become ready");
 287         }
 288         else if (status != 0x80)
 289         {
 290                 LOG_ERROR("status register: 0x%x", status);
 291                 if (status & 0x2)
 292                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 293                 if (status & 0x4)
 294                         LOG_ERROR("Program suspended");
 295                 if (status & 0x8)
 296                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 297                 if (status & 0x10)
 298                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 299                 if (status & 0x20)
 300                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 301                 if (status & 0x40)
 302                         LOG_ERROR("Block Erase Suspended");
 303
 304                 cfi_intel_clear_status_register(bank);
 305         }
 306
 307         return status;
 308 }
 309
 310 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 311 {
 312         u8 status, oldstatus;
 313
 314         oldstatus = cfi_get_u8(bank, 0, 0x0);
 315
 316         do {
 317                 status = cfi_get_u8(bank, 0, 0x0);
 318                 if ((status ^ oldstatus) & 0x40) {
 319                         if (status & 0x20) {
 320                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 321                                 status = cfi_get_u8(bank, 0, 0x0);
 322                                 if ((status ^ oldstatus) & 0x40) {
 323                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 324                                         return(ERROR_FLASH_OPERATION_FAILED);
 325                                 } else {
 326                                         LOG_DEBUG("status: 0x%x", status);
 327                                         return(ERROR_OK);
 328                                 }
 329                         }
 330                 } else {
 331                         LOG_DEBUG("status: 0x%x", status);
 332                         return(ERROR_OK);
 333                 }
 334
 335                 oldstatus = status;
 336                 usleep(1000);
 337         } while (timeout-- > 0);
 338
 339         LOG_ERROR("timeout, status: 0x%x", status);
 340
 341         return(ERROR_FLASH_BUSY);
 342 }
 343
 344 int cfi_read_intel_pri_ext(flash_bank_t *bank)
 345 {
 346         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 347         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 348         target_t *target = bank->target;
 349         u8 command[8];
 350
 351         cfi_info->pri_ext = pri_ext;
 352
 353         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 354         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 355         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 356
 357         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 358         {
 359                 cfi_command(bank, 0xf0, command);
 360                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 361                 cfi_command(bank, 0xff, command);
 362                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 363                 LOG_ERROR("Could not read bank flash bank information");
 364                 return ERROR_FLASH_BANK_INVALID;
 365         }
 366
 367         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 368         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 369
 370         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 371
 372         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 373         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 374         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 375
 376         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 377
 378         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 379         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 380
 381         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 382                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 383                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 384
 385         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 386         if (pri_ext->num_protection_fields != 1)
 387         {
 388                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 389         }
 390
 391         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 392         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 393         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 394
 395         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 396
 397         return ERROR_OK;
 398 }
 399
 400 int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 401 {
 402         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 403         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 404         target_t *target = bank->target;
 405         u8 command[8];
 406
 407         cfi_info->pri_ext = pri_ext;
 408
 409         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 410         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 411         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 412
 413         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 414         {
 415                 cfi_command(bank, 0xf0, command);
 416                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 417                 LOG_ERROR("Could not read spansion bank information");
 418                 return ERROR_FLASH_BANK_INVALID;
 419         }
 420
 421         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 422         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 423
 424         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 425
 426         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 427         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 428         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 429         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 430         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 431         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 432         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 433         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 434         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 435         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 436         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 437
 438         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 439               pri_ext->EraseSuspend, pri_ext->BlkProt);
 440
 441         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 442               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 443
 444         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 445
 446
 447         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 448                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 449                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 450
 451         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 452
 453         /* default values for implementation specific workarounds */
 454         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 455         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 456         pri_ext->_reversed_geometry = 0;
 457
 458         return ERROR_OK;
 459 }
 460
 461 int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 462 {
 463         cfi_atmel_pri_ext_t atmel_pri_ext;
 464         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 465         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 466         target_t *target = bank->target;
 467         u8 command[8];
 468
 469         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 470          * but a different primary extended query table.
 471          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 472          */
 473
 474         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 475
 476         cfi_info->pri_ext = pri_ext;
 477
 478         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 479         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 480         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 481
 482         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 483         {
 484                 cfi_command(bank, 0xf0, command);
 485                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 486                 LOG_ERROR("Could not read atmel bank information");
 487                 return ERROR_FLASH_BANK_INVALID;
 488         }
 489
 490         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 491         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 492         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 493
 494         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 495         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 496
 497         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 498
 499         pri_ext->major_version = atmel_pri_ext.major_version;
 500         pri_ext->minor_version = atmel_pri_ext.minor_version;
 501
 502         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 503         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 504         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 505         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 506
 507         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 508                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 509
 510         if (atmel_pri_ext.features & 0x02)
 511                 pri_ext->EraseSuspend = 2;
 512
 513         if (atmel_pri_ext.bottom_boot)
 514                 pri_ext->TopBottom = 2;
 515         else
 516                 pri_ext->TopBottom = 3;
 517
 518         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 519         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 520
 521         return ERROR_OK;
 522 }
 523
 524 int cfi_read_0002_pri_ext(flash_bank_t *bank)
 525 {
 526         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 527
 528         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 529         {
 530                 return cfi_read_atmel_pri_ext(bank);
 531         }
 532         else
 533         {
 534                 return cfi_read_spansion_pri_ext(bank);
 535         }
 536 }
 537
 538 int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 539 {
 540         int printed;
 541         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 542         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 543
 544         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 545         buf += printed;
 546         buf_size -= printed;
 547
 548         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 549                            pri_ext->pri[1], pri_ext->pri[2],
 550                            pri_ext->major_version, pri_ext->minor_version);
 551         buf += printed;
 552         buf_size -= printed;
 553
 554         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 555                            (pri_ext->SiliconRevision) >> 2,
 556                            (pri_ext->SiliconRevision) & 0x03);
 557         buf += printed;
 558         buf_size -= printed;
 559
 560         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 561                            pri_ext->EraseSuspend,
 562                            pri_ext->BlkProt);
 563         buf += printed;
 564         buf_size -= printed;
 565
 566         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 567                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 568                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 569
 570         return ERROR_OK;
 571 }
 572
 573 int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 574 {
 575         int printed;
 576         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 577         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 578
 579         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 580         buf += printed;
 581         buf_size -= printed;
 582
 583         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 584         buf += printed;
 585         buf_size -= printed;
 586
 587         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 588         buf += printed;
 589         buf_size -= printed;
 590
 591         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 592                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 593                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 594         buf += printed;
 595         buf_size -= printed;
 596
 597         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 598
 599         return ERROR_OK;
 600 }
 601
 602 int cfi_register_commands(struct command_context_s *cmd_ctx)
 603 {
 604         /*command_t *cfi_cmd = */
 605         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 606         /*
 607         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 608                                          "print part id of cfi flash bank <num>");
 609         */
 610         return ERROR_OK;
 611 }
 612
 613 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 614  */
 615 int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 616 {
 617         cfi_flash_bank_t *cfi_info;
 618         int i;
 619
 620         if (argc < 6)
 621         {
 622                 LOG_WARNING("incomplete flash_bank cfi configuration");
 623                 return ERROR_FLASH_BANK_INVALID;
 624         }
 625
 626         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 627                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 628         {
 629                 LOG_ERROR("chip and bus width have to specified in bytes");
 630                 return ERROR_FLASH_BANK_INVALID;
 631         }
 632
 633         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 634         cfi_info->probed = 0;
 635         bank->driver_priv = cfi_info;
 636
 637         cfi_info->write_algorithm = NULL;
 638
 639         cfi_info->x16_as_x8 = 0;
 640         cfi_info->jedec_probe = 0;
 641         cfi_info->not_cfi = 0;
 642
 643         for (i = 6; i < argc; i++)
 644         {
 645                 if (strcmp(args[i], "x16_as_x8") == 0)
 646                 {
 647                         cfi_info->x16_as_x8 = 1;
 648                 }
 649                 else if (strcmp(args[i], "jedec_probe") == 0)
 650                 {
 651                         cfi_info->jedec_probe = 1;
 652                 }
 653         }
 654
 655         cfi_info->write_algorithm = NULL;
 656
 657         /* bank wasn't probed yet */
 658         cfi_info->qry[0] = -1;
 659
 660         return ERROR_OK;
 661 }
 662
 663 int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 664 {
 665         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 666         target_t *target = bank->target;
 667         u8 command[8];
 668         int i;
 669
 670         cfi_intel_clear_status_register(bank);
 671
 672         for (i = first; i <= last; i++)
 673         {
 674                 cfi_command(bank, 0x20, command);
 675                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 676
 677                 cfi_command(bank, 0xd0, command);
 678                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 679
 680                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 681                         bank->sectors[i].is_erased = 1;
 682                 else
 683                 {
 684                         cfi_command(bank, 0xff, command);
 685                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 686
 687                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 688                         return ERROR_FLASH_OPERATION_FAILED;
 689                 }
 690         }
 691
 692         cfi_command(bank, 0xff, command);
 693         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 694
 695         return ERROR_OK;
 696 }
 697
 698 int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 699 {
 700         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 701         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 702         target_t *target = bank->target;
 703         u8 command[8];
 704         int i;
 705
 706         for (i = first; i <= last; i++)
 707         {
 708                 cfi_command(bank, 0xaa, command);
 709                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 710
 711                 cfi_command(bank, 0x55, command);
 712                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 713
 714                 cfi_command(bank, 0x80, command);
 715                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 716
 717                 cfi_command(bank, 0xaa, command);
 718                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
 719
 720                 cfi_command(bank, 0x55, command);
 721                 target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
 722
 723                 cfi_command(bank, 0x30, command);
 724                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 725
 726                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 727                         bank->sectors[i].is_erased = 1;
 728                 else
 729                 {
 730                         cfi_command(bank, 0xf0, command);
 731                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 732
 733                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 734                         return ERROR_FLASH_OPERATION_FAILED;
 735                 }
 736         }
 737
 738         cfi_command(bank, 0xf0, command);
 739         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 740
 741         return ERROR_OK;
 742 }
 743
 744 int cfi_erase(struct flash_bank_s *bank, int first, int last)
 745 {
 746         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 747
 748         if (bank->target->state != TARGET_HALTED)
 749         {
 750                 return ERROR_TARGET_NOT_HALTED;
 751         }
 752
 753         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 754         {
 755                 return ERROR_FLASH_SECTOR_INVALID;
 756         }
 757
 758         if (cfi_info->qry[0] != 'Q')
 759                 return ERROR_FLASH_BANK_NOT_PROBED;
 760
 761         switch(cfi_info->pri_id)
 762         {
 763                 case 1:
 764                 case 3:
 765                         return cfi_intel_erase(bank, first, last);
 766                         break;
 767                 case 2:
 768                         return cfi_spansion_erase(bank, first, last);
 769                         break;
 770                 default:
 771                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 772                         break;
 773         }
 774
 775         return ERROR_OK;
 776 }
 777
 778 int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 779 {
 780         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 781         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 782         target_t *target = bank->target;
 783         u8 command[8];
 784         int retry = 0;
 785         int i;
 786
 787         /* if the device supports neither legacy lock/unlock (bit 3) nor
 788          * instant individual block locking (bit 5).
 789          */
 790         if (!(pri_ext->feature_support & 0x28))
 791                 return ERROR_FLASH_OPERATION_FAILED;
 792
 793         cfi_intel_clear_status_register(bank);
 794
 795         for (i = first; i <= last; i++)
 796         {
 797                 cfi_command(bank, 0x60, command);
 798                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 799                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 800                 if (set)
 801                 {
 802                         cfi_command(bank, 0x01, command);
 803                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 804                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 805                         bank->sectors[i].is_protected = 1;
 806                 }
 807                 else
 808                 {
 809                         cfi_command(bank, 0xd0, command);
 810                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 811                         target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 812                         bank->sectors[i].is_protected = 0;
 813                 }
 814
 815                 /* instant individual block locking doesn't require reading of the status register */
 816                 if (!(pri_ext->feature_support & 0x20))
 817                 {
 818                         /* Clear lock bits operation may take up to 1.4s */
 819                         cfi_intel_wait_status_busy(bank, 1400);
 820                 }
 821                 else
 822                 {
 823                         u8 block_status;
 824                         /* read block lock bit, to verify status */
 825                         cfi_command(bank, 0x90, command);
 826                         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 827                         block_status = cfi_get_u8(bank, i, 0x2);
 828
 829                         if ((block_status & 0x1) != set)
 830                         {
 831                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 832                                 cfi_command(bank, 0x70, command);
 833                                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
 834                                 cfi_intel_wait_status_busy(bank, 10);
 835
 836                                 if (retry > 10)
 837                                         return ERROR_FLASH_OPERATION_FAILED;
 838                                 else
 839                                 {
 840                                         i--;
 841                                         retry++;
 842                                 }
 843                         }
 844                 }
 845         }
 846
 847         /* if the device doesn't support individual block lock bits set/clear,
 848          * all blocks have been unlocked in parallel, so we set those that should be protected
 849          */
 850         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 851         {
 852                 for (i = 0; i < bank->num_sectors; i++)
 853                 {
 854                         if (bank->sectors[i].is_protected == 1)
 855                         {
 856                                 cfi_intel_clear_status_register(bank);
 857
 858                                 cfi_command(bank, 0x60, command);
 859                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 860
 861                                 cfi_command(bank, 0x01, command);
 862                                 target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command);
 863
 864                                 cfi_intel_wait_status_busy(bank, 100);
 865                         }
 866                 }
 867         }
 868
 869         cfi_command(bank, 0xff, command);
 870         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 871
 872         return ERROR_OK;
 873 }
 874
 875 int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 876 {
 877         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 878
 879         if (bank->target->state != TARGET_HALTED)
 880         {
 881                 return ERROR_TARGET_NOT_HALTED;
 882         }
 883
 884         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 885         {
 886                 return ERROR_FLASH_SECTOR_INVALID;
 887         }
 888
 889         if (cfi_info->qry[0] != 'Q')
 890                 return ERROR_FLASH_BANK_NOT_PROBED;
 891
 892         switch(cfi_info->pri_id)
 893         {
 894                 case 1:
 895                 case 3:
 896                         cfi_intel_protect(bank, set, first, last);
 897                         break;
 898                 default:
 899                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 900                         break;
 901         }
 902
 903         return ERROR_OK;
 904 }
 905
 906 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 907 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 908 {
 909         /* target_t *target = bank->target; */
 910
 911         int i;
 912
 913         /* NOTE:
 914          * The data to flash must not be changed in endian! We write a bytestrem in
 915          * target byte order already. Only the control and status byte lane of the flash
 916          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 917          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 918          */
 919
 920 #if 0
 921         if (target->endianness == TARGET_LITTLE_ENDIAN)
 922         {
 923 #endif
 924                 /* shift bytes */
 925                 for (i = 0; i < bank->bus_width - 1; i++)
 926                         word[i] = word[i + 1];
 927                 word[bank->bus_width - 1] = byte;
 928 #if 0
 929         }
 930         else
 931         {
 932                 /* shift bytes */
 933                 for (i = bank->bus_width - 1; i > 0; i--)
 934                         word[i] = word[i - 1];
 935                 word[0] = byte;
 936         }
 937 #endif
 938 }
 939
 940 /* Convert code image to target endian */
 941 /* FIXME create general block conversion fcts in target.c?) */
 942 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
 943 {
 944         u32 i;
 945         for (i=0; i< count; i++)
 946         {
 947                 target_buffer_set_u32(target, dest, *src);
 948                 dest+=4;
 949                 src++;
 950         }
 951 }
 952
 953 u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
 954 {
 955         target_t *target = bank->target;
 956
 957         u8 buf[CFI_MAX_BUS_WIDTH];
 958         cfi_command(bank, cmd, buf);
 959         switch (bank->bus_width)
 960         {
 961         case 1 :
 962                 return buf[0];
 963                 break;
 964         case 2 :
 965                 return target_buffer_get_u16(target, buf);
 966                 break;
 967         case 4 :
 968                 return target_buffer_get_u32(target, buf);
 969                 break;
 970         default :
 971                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
 972                 return 0;
 973         }
 974 }
 975
 976 int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
 977 {
 978         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 979         target_t *target = bank->target;
 980         reg_param_t reg_params[7];
 981         armv4_5_algorithm_t armv4_5_info;
 982         working_area_t *source;
 983         u32 buffer_size = 32768;
 984         u32 write_command_val, busy_pattern_val, error_pattern_val;
 985
 986         /* algorithm register usage:
 987          * r0: source address (in RAM)
 988          * r1: target address (in Flash)
 989          * r2: count
 990          * r3: flash write command
 991          * r4: status byte (returned to host)
 992          * r5: busy test pattern
 993          * r6: error test pattern
 994          */
 995
 996         static const u32 word_32_code[] = {
 997                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
 998                 0xe5813000,   /*                str r3, [r1] */
 999                 0xe5814000,   /*                str r4, [r1] */
1000                 0xe5914000,   /* busy:  ldr r4, [r1] */
1001                 0xe0047005,   /*                and r7, r4, r5 */
1002                 0xe1570005,   /*                cmp r7, r5 */
1003                 0x1afffffb,   /*                bne busy */
1004                 0xe1140006,   /*                tst r4, r6 */
1005                 0x1a000003,   /*                bne done */
1006                 0xe2522001,   /*                subs r2, r2, #1 */
1007                 0x0a000001,   /*                beq done */
1008                 0xe2811004,   /*                add r1, r1 #4 */
1009                 0xeafffff2,   /*                b loop */
1010                 0xeafffffe    /* done:  b -2 */
1011         };
1012
1013         static const u32 word_16_code[] = {
1014                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1015                 0xe1c130b0,   /*                strh r3, [r1] */
1016                 0xe1c140b0,   /*                strh r4, [r1] */
1017                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1018                 0xe0047005,   /*                and r7, r4, r5 */
1019                 0xe1570005,   /*                cmp r7, r5 */
1020                 0x1afffffb,   /*                bne busy */
1021                 0xe1140006,   /*                tst r4, r6 */
1022                 0x1a000003,   /*                bne done */
1023                 0xe2522001,   /*                subs r2, r2, #1 */
1024                 0x0a000001,   /*                beq done */
1025                 0xe2811002,   /*                add r1, r1 #2 */
1026                 0xeafffff2,   /*                b loop */
1027                 0xeafffffe    /* done:  b -2 */
1028         };
1029
1030         static const u32 word_8_code[] = {
1031                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1032                 0xe5c13000,   /*                strb r3, [r1] */
1033                 0xe5c14000,   /*                strb r4, [r1] */
1034                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1035                 0xe0047005,   /*                and r7, r4, r5 */
1036                 0xe1570005,   /*                cmp r7, r5 */
1037                 0x1afffffb,   /*                bne busy */
1038                 0xe1140006,   /*                tst r4, r6 */
1039                 0x1a000003,   /*                bne done */
1040                 0xe2522001,   /*                subs r2, r2, #1 */
1041                 0x0a000001,   /*                beq done */
1042                 0xe2811001,   /*                add r1, r1 #1 */
1043                 0xeafffff2,   /*                b loop */
1044                 0xeafffffe    /* done:  b -2 */
1045         };
1046         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1047         const u32 *target_code_src;
1048         int target_code_size;
1049         int retval = ERROR_OK;
1050
1051
1052         cfi_intel_clear_status_register(bank);
1053
1054         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1055         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1056         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1057
1058         /* If we are setting up the write_algorith, we need target_code_src */
1059         /* if not we only need target_code_size.                                                                                                                */
1060         /*                                                                                                                                                                                                                                                                      */
1061         /* However, we don't want to create multiple code paths, so we                  */
1062         /* do the unecessary evaluation of target_code_src, which the                   */
1063         /* compiler will probably nicely optimize away if not needed                            */
1064
1065         /* prepare algorithm code for target endian */
1066         switch (bank->bus_width)
1067         {
1068         case 1 :
1069                 target_code_src = word_8_code;
1070                 target_code_size = sizeof(word_8_code);
1071                 break;
1072         case 2 :
1073                 target_code_src = word_16_code;
1074                 target_code_size = sizeof(word_16_code);
1075                 break;
1076         case 4 :
1077                 target_code_src = word_32_code;
1078                 target_code_size = sizeof(word_32_code);
1079                 break;
1080         default:
1081                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1082                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1083         }
1084
1085         /* flash write code */
1086         if (!cfi_info->write_algorithm)
1087         {
1088                 if ( target_code_size > sizeof(target_code) )
1089                 {
1090                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1091                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1092                 }
1093                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1094
1095                 /* Get memory for block write handler */
1096                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1097                 if (retval != ERROR_OK)
1098                 {
1099                         LOG_WARNING("No working area available, can't do block memory writes");
1100                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1101                 };
1102
1103                 /* write algorithm code to working area */
1104                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1105                 if (retval != ERROR_OK)
1106                 {
1107                         LOG_ERROR("Unable to write block write code to target");
1108                         goto cleanup;
1109                 }
1110         }
1111
1112         /* Get a workspace buffer for the data to flash starting with 32k size.
1113            Half size until buffer would be smaller 256 Bytem then fail back */
1114         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1115         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1116         {
1117                 buffer_size /= 2;
1118                 if (buffer_size <= 256)
1119                 {
1120                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1121                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1122                         goto cleanup;
1123                 }
1124         };
1125
1126         /* setup algo registers */
1127         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1128         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1129         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1130         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1131         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1132         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1133         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1134
1135         /* prepare command and status register patterns */
1136         write_command_val = cfi_command_val(bank, 0x40);
1137         busy_pattern_val  = cfi_command_val(bank, 0x80);
1138         error_pattern_val = cfi_command_val(bank, 0x7e);
1139
1140         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1141
1142         /* Programming main loop */
1143         while (count > 0)
1144         {
1145                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1146                 u32 wsm_error;
1147
1148                 target_write_buffer(target, source->address, thisrun_count, buffer);
1149
1150                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1151                 buf_set_u32(reg_params[1].value, 0, 32, address);
1152                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1153
1154                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1155                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1156                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1157
1158                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1159
1160                 /* Execute algorithm, assume breakpoint for last instruction */
1161                 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1162                         cfi_info->write_algorithm->address,
1163                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1164                         10000, /* 10s should be enough for max. 32k of data */
1165                         &armv4_5_info);
1166
1167                 /* On failure try a fall back to direct word writes */
1168                 if (retval != ERROR_OK)
1169                 {
1170                         cfi_intel_clear_status_register(bank);
1171                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1172                         retval = ERROR_FLASH_OPERATION_FAILED;
1173                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1174                         /* FIXME To allow fall back or recovery, we must save the actual status
1175                            somewhere, so that a higher level code can start recovery. */
1176                         goto cleanup;
1177                 }
1178
1179                 /* Check return value from algo code */
1180                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1181                 if (wsm_error)
1182                 {
1183                         /* read status register (outputs debug inforation) */
1184                         cfi_intel_wait_status_busy(bank, 100);
1185                         cfi_intel_clear_status_register(bank);
1186                         retval = ERROR_FLASH_OPERATION_FAILED;
1187                         goto cleanup;
1188                 }
1189
1190                 buffer += thisrun_count;
1191                 address += thisrun_count;
1192                 count -= thisrun_count;
1193         }
1194
1195         /* free up resources */
1196 cleanup:
1197         if (source)
1198                 target_free_working_area(target, source);
1199
1200         if (cfi_info->write_algorithm)
1201         {
1202                 target_free_working_area(target, cfi_info->write_algorithm);
1203                 cfi_info->write_algorithm = NULL;
1204         }
1205
1206         destroy_reg_param(&reg_params[0]);
1207         destroy_reg_param(&reg_params[1]);
1208         destroy_reg_param(&reg_params[2]);
1209         destroy_reg_param(&reg_params[3]);
1210         destroy_reg_param(&reg_params[4]);
1211         destroy_reg_param(&reg_params[5]);
1212         destroy_reg_param(&reg_params[6]);
1213
1214         return retval;
1215 }
1216
1217 int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1218 {
1219         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1220         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1221         target_t *target = bank->target;
1222         reg_param_t reg_params[10];
1223         armv4_5_algorithm_t armv4_5_info;
1224         working_area_t *source;
1225         u32 buffer_size = 32768;
1226         u32 status;
1227         int retval;
1228         int exit_code = ERROR_OK;
1229
1230         /* input parameters - */
1231         /*      R0 = source address */
1232         /*      R1 = destination address */
1233         /*      R2 = number of writes */
1234         /*      R3 = flash write command */
1235         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1236         /* output parameters - */
1237         /*      R5 = 0x80 ok 0x00 bad */
1238         /* temp registers - */
1239         /*      R6 = value read from flash to test status */
1240         /*      R7 = holding register */
1241         /* unlock registers - */
1242         /*  R8 = unlock1_addr */
1243         /*  R9 = unlock1_cmd */
1244         /*  R10 = unlock2_addr */
1245         /*  R11 = unlock2_cmd */
1246
1247         static const u32 word_32_code[] = {
1248                                                 /* 00008100 <sp_32_code>:               */
1249                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1250                 0xe5889000,     /* str  r9, [r8]                                */
1251                 0xe58ab000,     /* str  r11, [r10]                              */
1252                 0xe5883000,     /* str  r3, [r8]                                */
1253                 0xe5815000,     /* str  r5, [r1]                                */
1254                 0xe1a00000,     /* nop                                                  */
1255                                                 /*                                                              */
1256                                                 /* 00008110 <sp_32_busy>:               */
1257                 0xe5916000,     /* ldr  r6, [r1]                                */
1258                 0xe0257006,     /* eor  r7, r5, r6                              */
1259                 0xe0147007,     /* ands r7, r4, r7                              */
1260                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1261                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1262                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1263                 0xe5916000,     /* ldr  r6, [r1]                                */
1264                 0xe0257006,     /* eor  r7, r5, r6                              */
1265                 0xe0147007,     /* ands r7, r4, r7                              */
1266                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1267                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1268                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1269                                                 /*                                                              */
1270                                 /* 00008140 <sp_32_cont>:                               */
1271                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1272                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1273                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1274                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1275                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1276                                                 /*                                                              */
1277                                                 /* 00008154 <sp_32_done>:               */
1278                 0xeafffffe              /* b    8154 <sp_32_done>               */
1279                 };
1280
1281                 static const u32 word_16_code[] = {
1282                                 /* 00008158 <sp_16_code>:              */
1283                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1284                 0xe1c890b0,     /* strh r9, [r8]                                */
1285                 0xe1cab0b0,     /* strh r11, [r10]                              */
1286                 0xe1c830b0,     /* strh r3, [r8]                                */
1287                 0xe1c150b0,     /* strh r5, [r1]                       */
1288                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1289                                 /*                                     */
1290                                 /* 00008168 <sp_16_busy>:              */
1291                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1292                 0xe0257006,     /* eor  r7, r5, r6                     */
1293                 0xe0147007,     /* ands r7, r4, r7                     */
1294                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1295                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1296                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1297                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1298                 0xe0257006,     /* eor  r7, r5, r6                     */
1299                 0xe0147007,     /* ands r7, r4, r7                     */
1300                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1301                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1302                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1303                                 /*                                     */
1304                                 /* 00008198 <sp_16_cont>:              */
1305                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1306                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1307                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1308                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1309                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1310                                 /*                                     */
1311                                 /* 000081ac <sp_16_done>:              */
1312                 0xeafffffe      /* b    81ac <sp_16_done>              */
1313                 };
1314
1315                 static const u32 word_8_code[] = {
1316                                 /* 000081b0 <sp_16_code_end>:          */
1317                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1318                 0xe5c89000,     /* strb r9, [r8]                                */
1319                 0xe5cab000,     /* strb r11, [r10]                              */
1320                 0xe5c83000,     /* strb r3, [r8]                                */
1321                 0xe5c15000,     /* strb r5, [r1]                       */
1322                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1323                                 /*                                     */
1324                                 /* 000081c0 <sp_8_busy>:               */
1325                 0xe5d16000,     /* ldrb r6, [r1]                       */
1326                 0xe0257006,     /* eor  r7, r5, r6                     */
1327                 0xe0147007,     /* ands r7, r4, r7                     */
1328                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1329                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1330                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1331                 0xe5d16000,     /* ldrb r6, [r1]                       */
1332                 0xe0257006,     /* eor  r7, r5, r6                     */
1333                 0xe0147007,     /* ands r7, r4, r7                     */
1334                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1335                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1336                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1337                                 /*                                     */
1338                                 /* 000081f0 <sp_8_cont>:               */
1339                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1340                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1341                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1342                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1343                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1344                                 /*                                     */
1345                                 /* 00008204 <sp_8_done>:               */
1346                 0xeafffffe      /* b    8204 <sp_8_done>               */
1347         };
1348
1349         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1350         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1351         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1352
1353         /* flash write code */
1354         if (!cfi_info->write_algorithm)
1355         {
1356                 u8 *target_code;
1357                 int target_code_size;
1358                 const u32 *src;
1359
1360                 /* convert bus-width dependent algorithm code to correct endiannes */
1361                 switch (bank->bus_width)
1362                 {
1363                 case 1:
1364                         src = word_8_code;
1365                         target_code_size = sizeof(word_8_code);
1366                         break;
1367                 case 2:
1368                         src = word_16_code;
1369                         target_code_size = sizeof(word_16_code);
1370                         break;
1371                 case 4:
1372                         src = word_32_code;
1373                         target_code_size = sizeof(word_32_code);
1374                         break;
1375                 default:
1376                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1377                         return ERROR_FLASH_OPERATION_FAILED;
1378                 }
1379                 target_code = malloc(target_code_size);
1380                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1381
1382                 /* allocate working area */
1383                 retval=target_alloc_working_area(target, target_code_size,
1384                                 &cfi_info->write_algorithm);
1385                 if (retval != ERROR_OK)
1386                         return retval;
1387
1388                 /* write algorithm code to working area */
1389                 target_write_buffer(target, cfi_info->write_algorithm->address,
1390                                     target_code_size, target_code);
1391
1392                 free(target_code);
1393         }
1394         /* the following code still assumes target code is fixed 24*4 bytes */
1395
1396         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1397         {
1398                 buffer_size /= 2;
1399                 if (buffer_size <= 256)
1400                 {
1401                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1402                         if (cfi_info->write_algorithm)
1403                                 target_free_working_area(target, cfi_info->write_algorithm);
1404
1405                         LOG_WARNING("not enough working area available, can't do block memory writes");
1406                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1407                 }
1408         };
1409
1410         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1411         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1412         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1413         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1414         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1415         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1416         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1417         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1418         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1419         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1420
1421         while (count > 0)
1422         {
1423                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1424
1425                 target_write_buffer(target, source->address, thisrun_count, buffer);
1426
1427                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1428                 buf_set_u32(reg_params[1].value, 0, 32, address);
1429                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1430                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1431                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1432                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1433                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1434                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1435                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1436
1437                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1438                                                      cfi_info->write_algorithm->address,
1439                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1440                                                      10000, &armv4_5_info);
1441
1442                 status = buf_get_u32(reg_params[5].value, 0, 32);
1443
1444                 if ((retval != ERROR_OK) || status != 0x80)
1445                 {
1446                         LOG_DEBUG("status: 0x%x", status);
1447                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1448                         break;
1449                 }
1450
1451                 buffer += thisrun_count;
1452                 address += thisrun_count;
1453                 count -= thisrun_count;
1454         }
1455
1456         target_free_working_area(target, source);
1457
1458         destroy_reg_param(&reg_params[0]);
1459         destroy_reg_param(&reg_params[1]);
1460         destroy_reg_param(&reg_params[2]);
1461         destroy_reg_param(&reg_params[3]);
1462         destroy_reg_param(&reg_params[4]);
1463         destroy_reg_param(&reg_params[5]);
1464         destroy_reg_param(&reg_params[6]);
1465         destroy_reg_param(&reg_params[7]);
1466         destroy_reg_param(&reg_params[8]);
1467         destroy_reg_param(&reg_params[9]);
1468
1469         return exit_code;
1470 }
1471
1472 int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1473 {
1474         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1475         target_t *target = bank->target;
1476         u8 command[8];
1477
1478         cfi_intel_clear_status_register(bank);
1479         cfi_command(bank, 0x40, command);
1480         target->type->write_memory(target, address, bank->bus_width, 1, command);
1481
1482         target->type->write_memory(target, address, bank->bus_width, 1, word);
1483
1484         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1485         {
1486                 cfi_command(bank, 0xff, command);
1487                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1488
1489                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1490                 return ERROR_FLASH_OPERATION_FAILED;
1491         }
1492
1493         return ERROR_OK;
1494 }
1495
1496 int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1497 {
1498         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1499         target_t *target = bank->target;
1500         u8 command[8];
1501
1502         /* Calculate buffer size and boundary mask */
1503         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1504         u32 buffermask = buffersize-1;
1505         u32 bufferwsize;
1506
1507         /* Check for valid range */
1508         if (address & buffermask)
1509         {
1510                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1511                 return ERROR_FLASH_OPERATION_FAILED;
1512         }
1513         switch(bank->chip_width)
1514         {
1515         case 4 : bufferwsize = buffersize / 4; break;
1516         case 2 : bufferwsize = buffersize / 2; break;
1517         case 1 : bufferwsize = buffersize; break;
1518         default:
1519                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1520                 return ERROR_FLASH_OPERATION_FAILED;
1521         }
1522
1523         /* Check for valid size */
1524         if (wordcount > bufferwsize)
1525         {
1526                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1527                 return ERROR_FLASH_OPERATION_FAILED;
1528         }
1529
1530         /* Write to flash buffer */
1531         cfi_intel_clear_status_register(bank);
1532
1533         /* Initiate buffer operation _*/
1534         cfi_command(bank, 0xE8, command);
1535         target->type->write_memory(target, address, bank->bus_width, 1, command);
1536         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1537         {
1538                 cfi_command(bank, 0xff, command);
1539                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1540
1541                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1542                 return ERROR_FLASH_OPERATION_FAILED;
1543         }
1544
1545         /* Write buffer wordcount-1 and data words */
1546         cfi_command(bank, bufferwsize-1, command);
1547         target->type->write_memory(target, address, bank->bus_width, 1, command);
1548
1549         target->type->write_memory(target, address, bank->bus_width, bufferwsize, word);
1550
1551         /* Commit write operation */
1552         cfi_command(bank, 0xd0, command);
1553         target->type->write_memory(target, address, bank->bus_width, 1, command);
1554         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1555         {
1556                 cfi_command(bank, 0xff, command);
1557                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1558
1559                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1560                 return ERROR_FLASH_OPERATION_FAILED;
1561         }
1562
1563         return ERROR_OK;
1564 }
1565
1566 int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1567 {
1568         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1569         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1570         target_t *target = bank->target;
1571         u8 command[8];
1572
1573         cfi_command(bank, 0xaa, command);
1574         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1575
1576         cfi_command(bank, 0x55, command);
1577         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
1578
1579         cfi_command(bank, 0xa0, command);
1580         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
1581
1582         target->type->write_memory(target, address, bank->bus_width, 1, word);
1583
1584         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1585         {
1586                 cfi_command(bank, 0xf0, command);
1587                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1588
1589                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1590                 return ERROR_FLASH_OPERATION_FAILED;
1591         }
1592
1593         return ERROR_OK;
1594 }
1595
1596 int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1597 {
1598         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1599
1600         switch(cfi_info->pri_id)
1601         {
1602                 case 1:
1603                 case 3:
1604                         return cfi_intel_write_word(bank, word, address);
1605                         break;
1606                 case 2:
1607                         return cfi_spansion_write_word(bank, word, address);
1608                         break;
1609                 default:
1610                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1611                         break;
1612         }
1613
1614         return ERROR_FLASH_OPERATION_FAILED;
1615 }
1616
1617 int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1618 {
1619         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1620
1621         switch(cfi_info->pri_id)
1622         {
1623                 case 1:
1624                 case 3:
1625                         return cfi_intel_write_words(bank, word, wordcount, address);
1626                         break;
1627                 case 2:
1628                         /* return cfi_spansion_write_words(bank, word, address); */
1629                         LOG_ERROR("cfi primary command set %i unimplemented - FIXME", cfi_info->pri_id);
1630                         break;
1631                 default:
1632                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1633                         break;
1634         }
1635
1636         return ERROR_FLASH_OPERATION_FAILED;
1637 }
1638
1639 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1640 {
1641         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1642         target_t *target = bank->target;
1643         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1644         u32 write_p, copy_p;
1645         int align;      /* number of unaligned bytes */
1646         int blk_count; /* number of bus_width bytes for block copy */
1647         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1648         int i;
1649         int retval;
1650
1651         if (bank->target->state != TARGET_HALTED)
1652                 return ERROR_TARGET_NOT_HALTED;
1653
1654         if (offset + count > bank->size)
1655                 return ERROR_FLASH_DST_OUT_OF_BANK;
1656
1657         if (cfi_info->qry[0] != 'Q')
1658                 return ERROR_FLASH_BANK_NOT_PROBED;
1659
1660         /* start at the first byte of the first word (bus_width size) */
1661         write_p = address & ~(bank->bus_width - 1);
1662         if ((align = address - write_p) != 0)
1663         {
1664                 LOG_INFO("Fixup %d unaligned head bytes", align );
1665
1666                 for (i = 0; i < bank->bus_width; i++)
1667                         current_word[i] = 0;
1668                 copy_p = write_p;
1669
1670                 /* copy bytes before the first write address */
1671                 for (i = 0; i < align; ++i, ++copy_p)
1672                 {
1673                         u8 byte;
1674                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1675                         cfi_add_byte(bank, current_word, byte);
1676                 }
1677
1678                 /* add bytes from the buffer */
1679                 for (; (i < bank->bus_width) && (count > 0); i++)
1680                 {
1681                         cfi_add_byte(bank, current_word, *buffer++);
1682                         count--;
1683                         copy_p++;
1684                 }
1685
1686                 /* if the buffer is already finished, copy bytes after the last write address */
1687                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1688                 {
1689                         u8 byte;
1690                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1691                         cfi_add_byte(bank, current_word, byte);
1692                 }
1693
1694                 retval = cfi_write_word(bank, current_word, write_p);
1695                 if (retval != ERROR_OK)
1696                         return retval;
1697                 write_p = copy_p;
1698         }
1699
1700         /* handle blocks of bus_size aligned bytes */
1701         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1702         switch(cfi_info->pri_id)
1703         {
1704                 /* try block writes (fails without working area) */
1705                 case 1:
1706                 case 3:
1707                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1708                         break;
1709                 case 2:
1710                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1711                         break;
1712                 default:
1713                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1714                         retval = ERROR_FLASH_OPERATION_FAILED;
1715                         break;
1716         }
1717         if (retval == ERROR_OK)
1718         {
1719                 /* Increment pointers and decrease count on succesful block write */
1720                 buffer += blk_count;
1721                 write_p += blk_count;
1722                 count -= blk_count;
1723         }
1724         else
1725         {
1726                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1727                 {
1728                         u32 buffersize = 1UL << cfi_info->max_buf_write_size;
1729                         u32 buffermask = buffersize-1;
1730                         u32 bufferwsize;
1731
1732                         switch(bank->chip_width)
1733                         {
1734                         case 4 : bufferwsize = buffersize / 4; break;
1735                         case 2 : bufferwsize = buffersize / 2; break;
1736                         case 1 : bufferwsize = buffersize; break;
1737                         default:
1738                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1739                                 return ERROR_FLASH_OPERATION_FAILED;
1740                         }
1741
1742                         /* fall back to memory writes */
1743                         while (count >= bank->bus_width)
1744                         {
1745                                 int fallback;
1746                                 if ((write_p & 0xff) == 0)
1747                                 {
1748                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1749                                 }
1750                                 fallback = 1;
1751                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1752                                 {
1753                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1754                                         if (retval == ERROR_OK)
1755                                         {
1756                                                 buffer += buffersize;
1757                                                 write_p += buffersize;
1758                                                 count -= buffersize;
1759                                                 fallback=0;
1760                                         }
1761                                 }
1762                                 /* try the slow way? */
1763                                 if (fallback)
1764                                 {
1765                                         for (i = 0; i < bank->bus_width; i++)
1766                                                 current_word[i] = 0;
1767
1768                                         for (i = 0; i < bank->bus_width; i++)
1769                                         {
1770                                                 cfi_add_byte(bank, current_word, *buffer++);
1771                                         }
1772
1773                                         retval = cfi_write_word(bank, current_word, write_p);
1774                                         if (retval != ERROR_OK)
1775                                                 return retval;
1776
1777                                         write_p += bank->bus_width;
1778                                         count -= bank->bus_width;
1779                                 }
1780                         }
1781                 }
1782                 else
1783                         return retval;
1784         }
1785
1786         /* return to read array mode, so we can read from flash again for padding */
1787         cfi_command(bank, 0xf0, current_word);
1788         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1789         cfi_command(bank, 0xff, current_word);
1790         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1791
1792         /* handle unaligned tail bytes */
1793         if (count > 0)
1794         {
1795                 LOG_INFO("Fixup %d unaligned tail bytes", count );
1796
1797                 copy_p = write_p;
1798                 for (i = 0; i < bank->bus_width; i++)
1799                         current_word[i] = 0;
1800
1801                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
1802                 {
1803                         cfi_add_byte(bank, current_word, *buffer++);
1804                         count--;
1805                 }
1806                 for (; i < bank->bus_width; ++i, ++copy_p)
1807                 {
1808                         u8 byte;
1809                         target->type->read_memory(target, copy_p, 1, 1, &byte);
1810                         cfi_add_byte(bank, current_word, byte);
1811                 }
1812                 retval = cfi_write_word(bank, current_word, write_p);
1813                 if (retval != ERROR_OK)
1814                         return retval;
1815         }
1816
1817         /* return to read array mode */
1818         cfi_command(bank, 0xf0, current_word);
1819         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1820         cfi_command(bank, 0xff, current_word);
1821         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
1822
1823         return ERROR_OK;
1824 }
1825
1826 void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
1827 {
1828         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1829         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1830
1831         pri_ext->_reversed_geometry = 1;
1832 }
1833
1834 void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
1835 {
1836         int i;
1837         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1838         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1839
1840         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
1841         {
1842                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
1843
1844                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
1845                 {
1846                         int j = (cfi_info->num_erase_regions - 1) - i;
1847                         u32 swap;
1848
1849                         swap = cfi_info->erase_region_info[i];
1850                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
1851                         cfi_info->erase_region_info[j] = swap;
1852                 }
1853         }
1854 }
1855
1856 void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
1857 {
1858         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1859         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1860         cfi_unlock_addresses_t *unlock_addresses = param;
1861
1862         pri_ext->_unlock1 = unlock_addresses->unlock1;
1863         pri_ext->_unlock2 = unlock_addresses->unlock2;
1864 }
1865
1866 int cfi_probe(struct flash_bank_s *bank)
1867 {
1868         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1869         target_t *target = bank->target;
1870         u8 command[8];
1871         int num_sectors = 0;
1872         int i;
1873         int sector = 0;
1874         u32 offset = 0;
1875         u32 unlock1 = 0x555;
1876         u32 unlock2 = 0x2aa;
1877
1878         if (bank->target->state != TARGET_HALTED)
1879         {
1880                 return ERROR_TARGET_NOT_HALTED;
1881         }
1882
1883         cfi_info->probed = 0;
1884
1885         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
1886          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
1887          */
1888         if (cfi_info->jedec_probe)
1889         {
1890                 unlock1 = 0x5555;
1891                 unlock2 = 0x2aaa;
1892         }
1893
1894         /* switch to read identifier codes mode ("AUTOSELECT") */
1895         cfi_command(bank, 0xaa, command);
1896         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1897         cfi_command(bank, 0x55, command);
1898         target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command);
1899         cfi_command(bank, 0x90, command);
1900         target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command);
1901
1902         if (bank->chip_width == 1)
1903         {
1904                 u8 manufacturer, device_id;
1905                 target_read_u8(target, bank->base + 0x0, &manufacturer);
1906                 target_read_u8(target, bank->base + 0x1, &device_id);
1907                 cfi_info->manufacturer = manufacturer;
1908                 cfi_info->device_id = device_id;
1909         }
1910         else if (bank->chip_width == 2)
1911         {
1912                 target_read_u16(target, bank->base + 0x0, &cfi_info->manufacturer);
1913                 target_read_u16(target, bank->base + 0x2, &cfi_info->device_id);
1914         }
1915
1916         /* switch back to read array mode */
1917         cfi_command(bank, 0xf0, command);
1918         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1919         cfi_command(bank, 0xff, command);
1920         target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command);
1921
1922         cfi_fixup(bank, cfi_jedec_fixups);
1923
1924         /* query only if this is a CFI compatible flash,
1925          * otherwise the relevant info has already been filled in
1926          */
1927         if (cfi_info->not_cfi == 0)
1928         {
1929                 /* enter CFI query mode
1930                  * according to JEDEC Standard No. 68.01,
1931                  * a single bus sequence with address = 0x55, data = 0x98 should put
1932                  * the device into CFI query mode.
1933                  *
1934                  * SST flashes clearly violate this, and we will consider them incompatbile for now
1935                  */
1936                 cfi_command(bank, 0x98, command);
1937                 target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
1938
1939                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
1940                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
1941                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
1942
1943                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
1944
1945                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
1946                 {
1947                         cfi_command(bank, 0xf0, command);
1948                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1949                         cfi_command(bank, 0xff, command);
1950                         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
1951                         LOG_ERROR("Could not probe bank");
1952                         return ERROR_FLASH_BANK_INVALID;
1953                 }
1954
1955                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
1956                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
1957                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
1958                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
1959
1960                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
1961
1962                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
1963                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
1964                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
1965                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
1966                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
1967                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
1968                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
1969                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
1970                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
1971                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
1972                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
1973                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
1974
1975                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
1976                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
1977                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
1978                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
1979                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
1980                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
1981                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
1982                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
1983                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
1984                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
1985                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
1986
1987                 cfi_info->dev_size = cfi_query_u8(bank, 0, 0x27);
1988                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
1989                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
1990                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
1991
1992                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", 1 << cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
1993
1994                 if (((1 << cfi_info->dev_size) * bank->bus_width / bank->chip_width) != bank->size)
1995                 {
1996                         LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, 1 << cfi_info->dev_size);
1997                 }
1998
1999                 if (cfi_info->num_erase_regions)
2000                 {
2001                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2002                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2003                         {
2004                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2005                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2006                         }
2007                 }
2008                 else
2009                 {
2010                         cfi_info->erase_region_info = NULL;
2011                 }
2012
2013                 /* We need to read the primary algorithm extended query table before calculating
2014                  * the sector layout to be able to apply fixups
2015                  */
2016                 switch(cfi_info->pri_id)
2017                 {
2018                         /* Intel command set (standard and extended) */
2019                         case 0x0001:
2020                         case 0x0003:
2021                                 cfi_read_intel_pri_ext(bank);
2022                                 break;
2023                         /* AMD/Spansion, Atmel, ... command set */
2024                         case 0x0002:
2025                                 cfi_read_0002_pri_ext(bank);
2026                                 break;
2027                         default:
2028                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2029                                 break;
2030                 }
2031
2032                 /* return to read array mode
2033                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2034                  */
2035                 cfi_command(bank, 0xf0, command);
2036                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2037                 cfi_command(bank, 0xff, command);
2038                 target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2039         }
2040
2041         /* apply fixups depending on the primary command set */
2042         switch(cfi_info->pri_id)
2043         {
2044                 /* Intel command set (standard and extended) */
2045                 case 0x0001:
2046                 case 0x0003:
2047                         cfi_fixup(bank, cfi_0001_fixups);
2048                         break;
2049                 /* AMD/Spansion, Atmel, ... command set */
2050                 case 0x0002:
2051                         cfi_fixup(bank, cfi_0002_fixups);
2052                         break;
2053                 default:
2054                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2055                         break;
2056         }
2057
2058         if (cfi_info->num_erase_regions == 0)
2059         {
2060                 /* a device might have only one erase block, spanning the whole device */
2061                 bank->num_sectors = 1;
2062                 bank->sectors = malloc(sizeof(flash_sector_t));
2063
2064                 bank->sectors[sector].offset = 0x0;
2065                 bank->sectors[sector].size = bank->size;
2066                 bank->sectors[sector].is_erased = -1;
2067                 bank->sectors[sector].is_protected = -1;
2068         }
2069         else
2070         {
2071                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2072                 {
2073                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2074                 }
2075
2076                 bank->num_sectors = num_sectors;
2077                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2078
2079                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2080                 {
2081                         int j;
2082                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2083                         {
2084                                 bank->sectors[sector].offset = offset;
2085                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2086                                 offset += bank->sectors[sector].size;
2087                                 bank->sectors[sector].is_erased = -1;
2088                                 bank->sectors[sector].is_protected = -1;
2089                                 sector++;
2090                         }
2091                 }
2092         }
2093
2094         cfi_info->probed = 1;
2095
2096         return ERROR_OK;
2097 }
2098
2099 int cfi_auto_probe(struct flash_bank_s *bank)
2100 {
2101         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2102         if (cfi_info->probed)
2103                 return ERROR_OK;
2104         return cfi_probe(bank);
2105 }
2106
2107
2108 int cfi_intel_protect_check(struct flash_bank_s *bank)
2109 {
2110         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2111         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2112         target_t *target = bank->target;
2113         u8 command[CFI_MAX_BUS_WIDTH];
2114         int i;
2115
2116         /* check if block lock bits are supported on this device */
2117         if (!(pri_ext->blk_status_reg_mask & 0x1))
2118                 return ERROR_FLASH_OPERATION_FAILED;
2119
2120         cfi_command(bank, 0x90, command);
2121         target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command);
2122
2123         for (i = 0; i < bank->num_sectors; i++)
2124         {
2125                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2126
2127                 if (block_status & 1)
2128                         bank->sectors[i].is_protected = 1;
2129                 else
2130                         bank->sectors[i].is_protected = 0;
2131         }
2132
2133         cfi_command(bank, 0xff, command);
2134         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2135
2136         return ERROR_OK;
2137 }
2138
2139 int cfi_spansion_protect_check(struct flash_bank_s *bank)
2140 {
2141         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2142         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2143         target_t *target = bank->target;
2144         u8 command[8];
2145         int i;
2146
2147         cfi_command(bank, 0xaa, command);
2148         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2149
2150         cfi_command(bank, 0x55, command);
2151         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command);
2152
2153         cfi_command(bank, 0x90, command);
2154         target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command);
2155
2156         for (i = 0; i < bank->num_sectors; i++)
2157         {
2158                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2159
2160                 if (block_status & 1)
2161                         bank->sectors[i].is_protected = 1;
2162                 else
2163                         bank->sectors[i].is_protected = 0;
2164         }
2165
2166         cfi_command(bank, 0xf0, command);
2167         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2168
2169         return ERROR_OK;
2170 }
2171
2172 int cfi_protect_check(struct flash_bank_s *bank)
2173 {
2174         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2175
2176         if (bank->target->state != TARGET_HALTED)
2177         {
2178                 return ERROR_TARGET_NOT_HALTED;
2179         }
2180
2181         if (cfi_info->qry[0] != 'Q')
2182                 return ERROR_FLASH_BANK_NOT_PROBED;
2183
2184         switch(cfi_info->pri_id)
2185         {
2186                 case 1:
2187                 case 3:
2188                         return cfi_intel_protect_check(bank);
2189                         break;
2190                 case 2:
2191                         return cfi_spansion_protect_check(bank);
2192                         break;
2193                 default:
2194                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2195                         break;
2196         }
2197
2198         return ERROR_OK;
2199 }
2200
2201 int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2202 {
2203         int printed;
2204         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2205
2206         if (cfi_info->qry[0] == (char)-1)
2207         {
2208                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2209                 return ERROR_OK;
2210         }
2211
2212         if (cfi_info->not_cfi == 0)
2213         printed = snprintf(buf, buf_size, "\ncfi information:\n");
2214         else
2215                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2216         buf += printed;
2217         buf_size -= printed;
2218
2219         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2220                 cfi_info->manufacturer, cfi_info->device_id);
2221         buf += printed;
2222         buf_size -= printed;
2223
2224         if (cfi_info->not_cfi == 0)
2225         {
2226         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2227         buf += printed;
2228         buf_size -= printed;
2229
2230                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2231                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2232         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2233         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2234         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2235         buf += printed;
2236         buf_size -= printed;
2237
2238                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2239                                    1 << cfi_info->word_write_timeout_typ,
2240                                    1 << cfi_info->buf_write_timeout_typ,
2241                                    1 << cfi_info->block_erase_timeout_typ,
2242                                    1 << cfi_info->chip_erase_timeout_typ);
2243         buf += printed;
2244         buf_size -= printed;
2245
2246                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2247                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2248                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2249                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2250                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2251         buf += printed;
2252         buf_size -= printed;
2253
2254                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2255                                    1 << cfi_info->dev_size,
2256                                    cfi_info->interface_desc,
2257                                    cfi_info->max_buf_write_size);
2258         buf += printed;
2259         buf_size -= printed;
2260
2261         switch(cfi_info->pri_id)
2262         {
2263                 case 1:
2264                 case 3:
2265                         cfi_intel_info(bank, buf, buf_size);
2266                         break;
2267                 case 2:
2268                         cfi_spansion_info(bank, buf, buf_size);
2269                         break;
2270                 default:
2271                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2272                         break;
2273         }
2274         }
2275
2276         return ERROR_OK;
2277 }