git.sur5r.net Git - openocd/blob - src/flash/cfi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2005, 2007 by Dominic Rath                              *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *   Copyright (C) 2009 Michael Schwingen                                  *
   5  *   michael@schwingen.org                                                 *
   6  *                                                                         *
   7  *   This program is free software; you can redistribute it and/or modify  *
   8  *   it under the terms of the GNU General Public License as published by  *
   9  *   the Free Software Foundation; either version 2 of the License, or     *
  10  *   (at your option) any later version.                                   *
  11  *                                                                         *
  12  *   This program is distributed in the hope that it will be useful,       *
  13  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  14  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  15  *   GNU General Public License for more details.                          *
  16  *                                                                         *
  17  *   You should have received a copy of the GNU General Public License     *
  18  *   along with this program; if not, write to the                         *
  19  *   Free Software Foundation, Inc.,                                       *
  20  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  21  ***************************************************************************/
  22 #ifdef HAVE_CONFIG_H
  23 #include "config.h"
  24 #endif
  25
  26 #include "cfi.h"
  27 #include "non_cfi.h"
  28 #include "armv4_5.h"
  29 #include "binarybuffer.h"
  30
  31
  32 static int cfi_register_commands(struct command_context_s *cmd_ctx);
  33 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
  34 static int cfi_erase(struct flash_bank_s *bank, int first, int last);
  35 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last);
  36 static int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
  37 static int cfi_probe(struct flash_bank_s *bank);
  38 static int cfi_auto_probe(struct flash_bank_s *bank);
  39 static int cfi_protect_check(struct flash_bank_s *bank);
  40 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size);
  41
  42 //static int cfi_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
  43
  44 #define CFI_MAX_BUS_WIDTH       4
  45 #define CFI_MAX_CHIP_WIDTH      4
  46
  47 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
  48 #define CFI_MAX_INTEL_CODESIZE 256
  49
  50 flash_driver_t cfi_flash =
  51 {
  52         .name = "cfi",
  53         .register_commands = cfi_register_commands,
  54         .flash_bank_command = cfi_flash_bank_command,
  55         .erase = cfi_erase,
  56         .protect = cfi_protect,
  57         .write = cfi_write,
  58         .probe = cfi_probe,
  59         .auto_probe = cfi_auto_probe,
  60         .erase_check = default_flash_blank_check,
  61         .protect_check = cfi_protect_check,
  62         .info = cfi_info
  63 };
  64
  65 static cfi_unlock_addresses_t cfi_unlock_addresses[] =
  66 {
  67         [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
  68         [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
  69 };
  70
  71 /* CFI fixups foward declarations */
  72 static void cfi_fixup_0002_erase_regions(flash_bank_t *flash, void *param);
  73 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *flash, void *param);
  74 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
  75
  76 /* fixup after reading cmdset 0002 primary query table */
  77 static cfi_fixup_t cfi_0002_fixups[] = {
  78         {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  79         {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  80         {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  81         {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  82         {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  83         {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_atmel_reversed_erase_regions, NULL},
  84         {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
  85         {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  86         {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  87         {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
  88         {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
  89         {0, 0, NULL, NULL}
  90 };
  91
  92 /* fixup after reading cmdset 0001 primary query table */
  93 static cfi_fixup_t cfi_0001_fixups[] = {
  94         {0, 0, NULL, NULL}
  95 };
  96
  97 static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
  98 {
  99         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 100         cfi_fixup_t *f;
 101
 102         for (f = fixups; f->fixup; f++)
 103         {
 104                 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
 105                         ((f->id  == CFI_ID_ANY)  || (f->id  == cfi_info->device_id)))
 106                 {
 107                         f->fixup(bank, f->param);
 108                 }
 109         }
 110 }
 111
 112 /* inline u32 flash_address(flash_bank_t *bank, int sector, u32 offset) */
 113 static __inline__ u32 flash_address(flash_bank_t *bank, int sector, u32 offset)
 114 {
 115         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 116
 117         /* while the sector list isn't built, only accesses to sector 0 work */
 118         if (sector == 0)
 119                 return bank->base + (offset * bank->bus_width << cfi_info->x16_as_x8 );
 120         else
 121         {
 122                 if (!bank->sectors)
 123                 {
 124                         LOG_ERROR("BUG: sector list not yet built");
 125                         exit(-1);
 126                 }
 127                 return bank->base + bank->sectors[sector].offset + (offset * bank->bus_width << cfi_info->x16_as_x8 );
 128         }
 129
 130 }
 131
 132 static void cfi_command(flash_bank_t *bank, u8 cmd, u8 *cmd_buf)
 133 {
 134         int i;
 135
 136         /* clear whole buffer, to ensure bits that exceed the bus_width
 137          * are set to zero
 138          */
 139         for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
 140                 cmd_buf[i] = 0;
 141
 142         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 143         {
 144                 for (i = bank->bus_width; i > 0; i--)
 145                 {
 146                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 147                 }
 148         }
 149         else
 150         {
 151                 for (i = 1; i <= bank->bus_width; i++)
 152                 {
 153                         *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
 154                 }
 155         }
 156 }
 157
 158 /* read unsigned 8-bit value from the bank
 159  * flash banks are expected to be made of similar chips
 160  * the query result should be the same for all
 161  */
 162 static u8 cfi_query_u8(flash_bank_t *bank, int sector, u32 offset)
 163 {
 164         target_t *target = bank->target;
 165         u8 data[CFI_MAX_BUS_WIDTH];
 166
 167         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 168
 169         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 170                 return data[0];
 171         else
 172                 return data[bank->bus_width - 1];
 173 }
 174
 175 /* read unsigned 8-bit value from the bank
 176  * in case of a bank made of multiple chips,
 177  * the individual values are ORed
 178  */
 179 static u8 cfi_get_u8(flash_bank_t *bank, int sector, u32 offset)
 180 {
 181         target_t *target = bank->target;
 182         u8 data[CFI_MAX_BUS_WIDTH];
 183         int i;
 184
 185         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 1, data);
 186
 187         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 188         {
 189                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 190                         data[0] |= data[i];
 191
 192                 return data[0];
 193         }
 194         else
 195         {
 196                 u8 value = 0;
 197                 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
 198                         value |= data[bank->bus_width - 1 - i];
 199
 200                 return value;
 201         }
 202 }
 203
 204 static u16 cfi_query_u16(flash_bank_t *bank, int sector, u32 offset)
 205 {
 206         target_t *target = bank->target;
 207         u8 data[CFI_MAX_BUS_WIDTH * 2];
 208
 209         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 2, data);
 210
 211         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 212                 return data[0] | data[bank->bus_width] << 8;
 213         else
 214                 return data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
 215 }
 216
 217 static u32 cfi_query_u32(flash_bank_t *bank, int sector, u32 offset)
 218 {
 219         target_t *target = bank->target;
 220         u8 data[CFI_MAX_BUS_WIDTH * 4];
 221
 222         target->type->read_memory(target, flash_address(bank, sector, offset), bank->bus_width, 4, data);
 223
 224         if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
 225                 return data[0] | data[bank->bus_width] << 8 | data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
 226         else
 227                 return data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
 228                                 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
 229 }
 230
 231 static void cfi_intel_clear_status_register(flash_bank_t *bank)
 232 {
 233         target_t *target = bank->target;
 234         u8 command[8];
 235
 236         if (target->state != TARGET_HALTED)
 237         {
 238                 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
 239                 exit(-1);
 240         }
 241
 242         cfi_command(bank, 0x50, command);
 243         target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 244 }
 245
 246 u8 cfi_intel_wait_status_busy(flash_bank_t *bank, int timeout)
 247 {
 248         u8 status;
 249
 250         while ((!((status = cfi_get_u8(bank, 0, 0x0)) & 0x80)) && (timeout-- > 0))
 251         {
 252                 LOG_DEBUG("status: 0x%x", status);
 253                 alive_sleep(1);
 254         }
 255
 256         /* mask out bit 0 (reserved) */
 257         status = status & 0xfe;
 258
 259         LOG_DEBUG("status: 0x%x", status);
 260
 261         if ((status & 0x80) != 0x80)
 262         {
 263                 LOG_ERROR("timeout while waiting for WSM to become ready");
 264         }
 265         else if (status != 0x80)
 266         {
 267                 LOG_ERROR("status register: 0x%x", status);
 268                 if (status & 0x2)
 269                         LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
 270                 if (status & 0x4)
 271                         LOG_ERROR("Program suspended");
 272                 if (status & 0x8)
 273                         LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
 274                 if (status & 0x10)
 275                         LOG_ERROR("Program Error / Error in Setting Lock-Bit");
 276                 if (status & 0x20)
 277                         LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
 278                 if (status & 0x40)
 279                         LOG_ERROR("Block Erase Suspended");
 280
 281                 cfi_intel_clear_status_register(bank);
 282         }
 283
 284         return status;
 285 }
 286
 287 int cfi_spansion_wait_status_busy(flash_bank_t *bank, int timeout)
 288 {
 289         u8 status, oldstatus;
 290         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 291
 292         oldstatus = cfi_get_u8(bank, 0, 0x0);
 293
 294         do {
 295                 status = cfi_get_u8(bank, 0, 0x0);
 296                 if ((status ^ oldstatus) & 0x40) {
 297                         if (status & cfi_info->status_poll_mask & 0x20) {
 298                                 oldstatus = cfi_get_u8(bank, 0, 0x0);
 299                                 status = cfi_get_u8(bank, 0, 0x0);
 300                                 if ((status ^ oldstatus) & 0x40) {
 301                                         LOG_ERROR("dq5 timeout, status: 0x%x", status);
 302                                         return(ERROR_FLASH_OPERATION_FAILED);
 303                                 } else {
 304                                         LOG_DEBUG("status: 0x%x", status);
 305                                         return(ERROR_OK);
 306                                 }
 307                         }
 308                 } else { /* no toggle: finished, OK */
 309                         LOG_DEBUG("status: 0x%x", status);
 310                         return(ERROR_OK);
 311                 }
 312
 313                 oldstatus = status;
 314                 alive_sleep(1);
 315         } while (timeout-- > 0);
 316
 317         LOG_ERROR("timeout, status: 0x%x", status);
 318
 319         return(ERROR_FLASH_BUSY);
 320 }
 321
 322 static int cfi_read_intel_pri_ext(flash_bank_t *bank)
 323 {
 324         int retval;
 325         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 326         cfi_intel_pri_ext_t *pri_ext = malloc(sizeof(cfi_intel_pri_ext_t));
 327         target_t *target = bank->target;
 328         u8 command[8];
 329
 330         cfi_info->pri_ext = pri_ext;
 331
 332         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 333         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 334         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 335
 336         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 337         {
 338                 cfi_command(bank, 0xf0, command);
 339                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 340                 {
 341                         return retval;
 342                 }
 343                 cfi_command(bank, 0xff, command);
 344                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 345                 {
 346                         return retval;
 347                 }
 348                 LOG_ERROR("Could not read bank flash bank information");
 349                 return ERROR_FLASH_BANK_INVALID;
 350         }
 351
 352         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 353         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 354
 355         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 356
 357         pri_ext->feature_support = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5);
 358         pri_ext->suspend_cmd_support = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 359         pri_ext->blk_status_reg_mask = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa);
 360
 361         LOG_DEBUG("feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 362
 363         pri_ext->vcc_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc);
 364         pri_ext->vpp_optimal = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd);
 365
 366         LOG_DEBUG("Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x",
 367                   (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 368                   (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 369
 370         pri_ext->num_protection_fields = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe);
 371         if (pri_ext->num_protection_fields != 1)
 372         {
 373                 LOG_WARNING("expected one protection register field, but found %i", pri_ext->num_protection_fields);
 374         }
 375
 376         pri_ext->prot_reg_addr = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf);
 377         pri_ext->fact_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11);
 378         pri_ext->user_prot_reg_size = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12);
 379
 380         LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 381
 382         return ERROR_OK;
 383 }
 384
 385 static int cfi_read_spansion_pri_ext(flash_bank_t *bank)
 386 {
 387         int retval;
 388         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 389         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 390         target_t *target = bank->target;
 391         u8 command[8];
 392
 393         cfi_info->pri_ext = pri_ext;
 394
 395         pri_ext->pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 396         pri_ext->pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 397         pri_ext->pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 398
 399         if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
 400         {
 401                 cfi_command(bank, 0xf0, command);
 402                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 403                 {
 404                         return retval;
 405                 }
 406                 LOG_ERROR("Could not read spansion bank information");
 407                 return ERROR_FLASH_BANK_INVALID;
 408         }
 409
 410         pri_ext->major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 411         pri_ext->minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 412
 413         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 414
 415         pri_ext->SiliconRevision = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 416         pri_ext->EraseSuspend    = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 417         pri_ext->BlkProt         = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 418         pri_ext->TmpBlkUnprotect = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 419         pri_ext->BlkProtUnprot   = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9);
 420         pri_ext->SimultaneousOps = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10);
 421         pri_ext->BurstMode       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11);
 422         pri_ext->PageMode        = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12);
 423         pri_ext->VppMin          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13);
 424         pri_ext->VppMax          = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14);
 425         pri_ext->TopBottom       = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15);
 426
 427         LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x", pri_ext->SiliconRevision,
 428               pri_ext->EraseSuspend, pri_ext->BlkProt);
 429
 430         LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
 431               pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
 432
 433         LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
 434
 435
 436         LOG_DEBUG("Vpp min: %2.2d.%1.1d, Vpp max: %2.2d.%1.1x",
 437                   (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 438                   (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 439
 440         LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
 441
 442         /* default values for implementation specific workarounds */
 443         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 444         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 445         pri_ext->_reversed_geometry = 0;
 446
 447         return ERROR_OK;
 448 }
 449
 450 static int cfi_read_atmel_pri_ext(flash_bank_t *bank)
 451 {
 452         int retval;
 453         cfi_atmel_pri_ext_t atmel_pri_ext;
 454         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 455         cfi_spansion_pri_ext_t *pri_ext = malloc(sizeof(cfi_spansion_pri_ext_t));
 456         target_t *target = bank->target;
 457         u8 command[8];
 458
 459         /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
 460          * but a different primary extended query table.
 461          * We read the atmel table, and prepare a valid AMD/Spansion query table.
 462          */
 463
 464         memset(pri_ext, 0, sizeof(cfi_spansion_pri_ext_t));
 465
 466         cfi_info->pri_ext = pri_ext;
 467
 468         atmel_pri_ext.pri[0] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0);
 469         atmel_pri_ext.pri[1] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1);
 470         atmel_pri_ext.pri[2] = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2);
 471
 472         if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R') || (atmel_pri_ext.pri[2] != 'I'))
 473         {
 474                 cfi_command(bank, 0xf0, command);
 475                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 476                 {
 477                         return retval;
 478                 }
 479                 LOG_ERROR("Could not read atmel bank information");
 480                 return ERROR_FLASH_BANK_INVALID;
 481         }
 482
 483         pri_ext->pri[0] = atmel_pri_ext.pri[0];
 484         pri_ext->pri[1] = atmel_pri_ext.pri[1];
 485         pri_ext->pri[2] = atmel_pri_ext.pri[2];
 486
 487         atmel_pri_ext.major_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3);
 488         atmel_pri_ext.minor_version = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4);
 489
 490         LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0], atmel_pri_ext.pri[1], atmel_pri_ext.pri[2], atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
 491
 492         pri_ext->major_version = atmel_pri_ext.major_version;
 493         pri_ext->minor_version = atmel_pri_ext.minor_version;
 494
 495         atmel_pri_ext.features = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5);
 496         atmel_pri_ext.bottom_boot = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6);
 497         atmel_pri_ext.burst_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7);
 498         atmel_pri_ext.page_mode = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8);
 499
 500         LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
 501                 atmel_pri_ext.features, atmel_pri_ext.bottom_boot, atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
 502
 503         if (atmel_pri_ext.features & 0x02)
 504                 pri_ext->EraseSuspend = 2;
 505
 506         if (atmel_pri_ext.bottom_boot)
 507                 pri_ext->TopBottom = 2;
 508         else
 509                 pri_ext->TopBottom = 3;
 510
 511         pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
 512         pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
 513
 514         return ERROR_OK;
 515 }
 516
 517 static int cfi_read_0002_pri_ext(flash_bank_t *bank)
 518 {
 519         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 520
 521         if (cfi_info->manufacturer == CFI_MFR_ATMEL)
 522         {
 523                 return cfi_read_atmel_pri_ext(bank);
 524         }
 525         else
 526         {
 527                 return cfi_read_spansion_pri_ext(bank);
 528         }
 529 }
 530
 531 static int cfi_spansion_info(struct flash_bank_s *bank, char *buf, int buf_size)
 532 {
 533         int printed;
 534         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 535         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 536
 537         printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
 538         buf += printed;
 539         buf_size -= printed;
 540
 541         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
 542                            pri_ext->pri[1], pri_ext->pri[2],
 543                            pri_ext->major_version, pri_ext->minor_version);
 544         buf += printed;
 545         buf_size -= printed;
 546
 547         printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
 548                            (pri_ext->SiliconRevision) >> 2,
 549                            (pri_ext->SiliconRevision) & 0x03);
 550         buf += printed;
 551         buf_size -= printed;
 552
 553         printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
 554                            pri_ext->EraseSuspend,
 555                            pri_ext->BlkProt);
 556         buf += printed;
 557         buf_size -= printed;
 558
 559         printed = snprintf(buf, buf_size, "VppMin: %2.2d.%1.1x, VppMax: %2.2d.%1.1x\n",
 560                 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
 561                 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
 562
 563         return ERROR_OK;
 564 }
 565
 566 static int cfi_intel_info(struct flash_bank_s *bank, char *buf, int buf_size)
 567 {
 568         int printed;
 569         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 570         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 571
 572         printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
 573         buf += printed;
 574         buf_size -= printed;
 575
 576         printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0], pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
 577         buf += printed;
 578         buf_size -= printed;
 579
 580         printed = snprintf(buf, buf_size, "feature_support: 0x%x, suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n", pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
 581         buf += printed;
 582         buf_size -= printed;
 583
 584         printed = snprintf(buf, buf_size, "Vcc opt: %1.1x.%1.1x, Vpp opt: %1.1x.%1.1x\n",
 585                 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
 586                 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
 587         buf += printed;
 588         buf_size -= printed;
 589
 590         printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, factory pre-programmed: %i, user programmable: %i\n", pri_ext->num_protection_fields, pri_ext->prot_reg_addr, 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
 591
 592         return ERROR_OK;
 593 }
 594
 595 static int cfi_register_commands(struct command_context_s *cmd_ctx)
 596 {
 597         /*command_t *cfi_cmd = */
 598         register_command(cmd_ctx, NULL, "cfi", NULL, COMMAND_ANY, "flash bank cfi <base> <size> <chip_width> <bus_width> <targetNum> [jedec_probe/x16_as_x8]");
 599         /*
 600         register_command(cmd_ctx, cfi_cmd, "part_id", cfi_handle_part_id_command, COMMAND_EXEC,
 601                                          "print part id of cfi flash bank <num>");
 602         */
 603         return ERROR_OK;
 604 }
 605
 606 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
 607  */
 608 static int cfi_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 609 {
 610         cfi_flash_bank_t *cfi_info;
 611         int i;
 612         (void) cmd_ctx;
 613         (void) cmd;
 614
 615         if (argc < 6)
 616         {
 617                 LOG_WARNING("incomplete flash_bank cfi configuration");
 618                 return ERROR_FLASH_BANK_INVALID;
 619         }
 620
 621         if ((strtoul(args[4], NULL, 0) > CFI_MAX_CHIP_WIDTH)
 622                 || (strtoul(args[3], NULL, 0) > CFI_MAX_BUS_WIDTH))
 623         {
 624                 LOG_ERROR("chip and bus width have to specified in bytes");
 625                 return ERROR_FLASH_BANK_INVALID;
 626         }
 627
 628         cfi_info = malloc(sizeof(cfi_flash_bank_t));
 629         cfi_info->probed = 0;
 630         bank->driver_priv = cfi_info;
 631
 632         cfi_info->write_algorithm = NULL;
 633
 634         cfi_info->x16_as_x8 = 0;
 635         cfi_info->jedec_probe = 0;
 636         cfi_info->not_cfi = 0;
 637
 638         for (i = 6; i < argc; i++)
 639         {
 640                 if (strcmp(args[i], "x16_as_x8") == 0)
 641                 {
 642                         cfi_info->x16_as_x8 = 1;
 643                 }
 644                 else if (strcmp(args[i], "jedec_probe") == 0)
 645                 {
 646                         cfi_info->jedec_probe = 1;
 647                 }
 648         }
 649
 650         cfi_info->write_algorithm = NULL;
 651
 652         /* bank wasn't probed yet */
 653         cfi_info->qry[0] = -1;
 654
 655         return ERROR_OK;
 656 }
 657
 658 static int cfi_intel_erase(struct flash_bank_s *bank, int first, int last)
 659 {
 660         int retval;
 661         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 662         target_t *target = bank->target;
 663         u8 command[8];
 664         int i;
 665
 666         cfi_intel_clear_status_register(bank);
 667
 668         for (i = first; i <= last; i++)
 669         {
 670                 cfi_command(bank, 0x20, command);
 671                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 672                 {
 673                         return retval;
 674                 }
 675
 676                 cfi_command(bank, 0xd0, command);
 677                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 678                 {
 679                         return retval;
 680                 }
 681
 682                 if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == 0x80)
 683                         bank->sectors[i].is_erased = 1;
 684                 else
 685                 {
 686                         cfi_command(bank, 0xff, command);
 687                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 688                         {
 689                                 return retval;
 690                         }
 691
 692                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 693                         return ERROR_FLASH_OPERATION_FAILED;
 694                 }
 695         }
 696
 697         cfi_command(bank, 0xff, command);
 698         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 699
 700 }
 701
 702 static int cfi_spansion_erase(struct flash_bank_s *bank, int first, int last)
 703 {
 704         int retval;
 705         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 706         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
 707         target_t *target = bank->target;
 708         u8 command[8];
 709         int i;
 710
 711         for (i = first; i <= last; i++)
 712         {
 713                 cfi_command(bank, 0xaa, command);
 714                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 715                 {
 716                         return retval;
 717                 }
 718
 719                 cfi_command(bank, 0x55, command);
 720                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 721                 {
 722                         return retval;
 723                 }
 724
 725                 cfi_command(bank, 0x80, command);
 726                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 727                 {
 728                         return retval;
 729                 }
 730
 731                 cfi_command(bank, 0xaa, command);
 732                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
 733                 {
 734                         return retval;
 735                 }
 736
 737                 cfi_command(bank, 0x55, command);
 738                 if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
 739                 {
 740                         return retval;
 741                 }
 742
 743                 cfi_command(bank, 0x30, command);
 744                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 745                 {
 746                         return retval;
 747                 }
 748
 749                 if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->block_erase_timeout_typ)) == ERROR_OK)
 750                         bank->sectors[i].is_erased = 1;
 751                 else
 752                 {
 753                         cfi_command(bank, 0xf0, command);
 754                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 755                         {
 756                                 return retval;
 757                         }
 758
 759                         LOG_ERROR("couldn't erase block %i of flash bank at base 0x%x", i, bank->base);
 760                         return ERROR_FLASH_OPERATION_FAILED;
 761                 }
 762         }
 763
 764         cfi_command(bank, 0xf0, command);
 765         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 766 }
 767
 768 static int cfi_erase(struct flash_bank_s *bank, int first, int last)
 769 {
 770         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 771
 772         if (bank->target->state != TARGET_HALTED)
 773         {
 774                 LOG_ERROR("Target not halted");
 775                 return ERROR_TARGET_NOT_HALTED;
 776         }
 777
 778         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 779         {
 780                 return ERROR_FLASH_SECTOR_INVALID;
 781         }
 782
 783         if (cfi_info->qry[0] != 'Q')
 784                 return ERROR_FLASH_BANK_NOT_PROBED;
 785
 786         switch(cfi_info->pri_id)
 787         {
 788                 case 1:
 789                 case 3:
 790                         return cfi_intel_erase(bank, first, last);
 791                         break;
 792                 case 2:
 793                         return cfi_spansion_erase(bank, first, last);
 794                         break;
 795                 default:
 796                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
 797                         break;
 798         }
 799
 800         return ERROR_OK;
 801 }
 802
 803 static int cfi_intel_protect(struct flash_bank_s *bank, int set, int first, int last)
 804 {
 805         int retval;
 806         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 807         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
 808         target_t *target = bank->target;
 809         u8 command[8];
 810         int retry = 0;
 811         int i;
 812
 813         /* if the device supports neither legacy lock/unlock (bit 3) nor
 814          * instant individual block locking (bit 5).
 815          */
 816         if (!(pri_ext->feature_support & 0x28))
 817                 return ERROR_FLASH_OPERATION_FAILED;
 818
 819         cfi_intel_clear_status_register(bank);
 820
 821         for (i = first; i <= last; i++)
 822         {
 823                 cfi_command(bank, 0x60, command);
 824                 LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 825                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 826                 {
 827                         return retval;
 828                 }
 829                 if (set)
 830                 {
 831                         cfi_command(bank, 0x01, command);
 832                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 833                         if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 834                         {
 835                                 return retval;
 836                         }
 837                         bank->sectors[i].is_protected = 1;
 838                 }
 839                 else
 840                 {
 841                         cfi_command(bank, 0xd0, command);
 842                         LOG_DEBUG("address: 0x%4.4x, command: 0x%4.4x", flash_address(bank, i, 0x0), target_buffer_get_u32(target, command));
 843                         if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 844                         {
 845                                 return retval;
 846                         }
 847                         bank->sectors[i].is_protected = 0;
 848                 }
 849
 850                 /* instant individual block locking doesn't require reading of the status register */
 851                 if (!(pri_ext->feature_support & 0x20))
 852                 {
 853                         /* Clear lock bits operation may take up to 1.4s */
 854                         cfi_intel_wait_status_busy(bank, 1400);
 855                 }
 856                 else
 857                 {
 858                         u8 block_status;
 859                         /* read block lock bit, to verify status */
 860                         cfi_command(bank, 0x90, command);
 861                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 862                         {
 863                                 return retval;
 864                         }
 865                         block_status = cfi_get_u8(bank, i, 0x2);
 866
 867                         if ((block_status & 0x1) != set)
 868                         {
 869                                 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)", set, block_status);
 870                                 cfi_command(bank, 0x70, command);
 871                                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
 872                                 {
 873                                         return retval;
 874                                 }
 875                                 cfi_intel_wait_status_busy(bank, 10);
 876
 877                                 if (retry > 10)
 878                                         return ERROR_FLASH_OPERATION_FAILED;
 879                                 else
 880                                 {
 881                                         i--;
 882                                         retry++;
 883                                 }
 884                         }
 885                 }
 886         }
 887
 888         /* if the device doesn't support individual block lock bits set/clear,
 889          * all blocks have been unlocked in parallel, so we set those that should be protected
 890          */
 891         if ((!set) && (!(pri_ext->feature_support & 0x20)))
 892         {
 893                 for (i = 0; i < bank->num_sectors; i++)
 894                 {
 895                         if (bank->sectors[i].is_protected == 1)
 896                         {
 897                                 cfi_intel_clear_status_register(bank);
 898
 899                                 cfi_command(bank, 0x60, command);
 900                                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 901                                 {
 902                                         return retval;
 903                                 }
 904
 905                                 cfi_command(bank, 0x01, command);
 906                                 if((retval = target->type->write_memory(target, flash_address(bank, i, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
 907                                 {
 908                                         return retval;
 909                                 }
 910
 911                                 cfi_intel_wait_status_busy(bank, 100);
 912                         }
 913                 }
 914         }
 915
 916         cfi_command(bank, 0xff, command);
 917         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
 918 }
 919
 920 static int cfi_protect(struct flash_bank_s *bank, int set, int first, int last)
 921 {
 922         cfi_flash_bank_t *cfi_info = bank->driver_priv;
 923
 924         if (bank->target->state != TARGET_HALTED)
 925         {
 926                 LOG_ERROR("Target not halted");
 927                 return ERROR_TARGET_NOT_HALTED;
 928         }
 929
 930         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 931         {
 932                 return ERROR_FLASH_SECTOR_INVALID;
 933         }
 934
 935         if (cfi_info->qry[0] != 'Q')
 936                 return ERROR_FLASH_BANK_NOT_PROBED;
 937
 938         switch(cfi_info->pri_id)
 939         {
 940                 case 1:
 941                 case 3:
 942                         cfi_intel_protect(bank, set, first, last);
 943                         break;
 944                 default:
 945                         LOG_ERROR("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
 946                         break;
 947         }
 948
 949         return ERROR_OK;
 950 }
 951
 952 /* FIXME Replace this by a simple memcpy() - still unsure about sideeffects */
 953 static void cfi_add_byte(struct flash_bank_s *bank, u8 *word, u8 byte)
 954 {
 955         /* target_t *target = bank->target; */
 956
 957         int i;
 958
 959         /* NOTE:
 960          * The data to flash must not be changed in endian! We write a bytestrem in
 961          * target byte order already. Only the control and status byte lane of the flash
 962          * WSM is interpreted by the CPU in different ways, when read a u16 or u32
 963          * word (data seems to be in the upper or lower byte lane for u16 accesses).
 964          */
 965
 966 #if 0
 967         if (target->endianness == TARGET_LITTLE_ENDIAN)
 968         {
 969 #endif
 970                 /* shift bytes */
 971                 for (i = 0; i < bank->bus_width - 1; i++)
 972                         word[i] = word[i + 1];
 973                 word[bank->bus_width - 1] = byte;
 974 #if 0
 975         }
 976         else
 977         {
 978                 /* shift bytes */
 979                 for (i = bank->bus_width - 1; i > 0; i--)
 980                         word[i] = word[i - 1];
 981                 word[0] = byte;
 982         }
 983 #endif
 984 }
 985
 986 /* Convert code image to target endian */
 987 /* FIXME create general block conversion fcts in target.c?) */
 988 static void cfi_fix_code_endian(target_t *target, u8 *dest, const u32 *src, u32 count)
 989 {
 990         u32 i;
 991         for (i=0; i< count; i++)
 992         {
 993                 target_buffer_set_u32(target, dest, *src);
 994                 dest+=4;
 995                 src++;
 996         }
 997 }
 998
 999 static u32 cfi_command_val(flash_bank_t *bank, u8 cmd)
1000 {
1001         target_t *target = bank->target;
1002
1003         u8 buf[CFI_MAX_BUS_WIDTH];
1004         cfi_command(bank, cmd, buf);
1005         switch (bank->bus_width)
1006         {
1007         case 1 :
1008                 return buf[0];
1009                 break;
1010         case 2 :
1011                 return target_buffer_get_u16(target, buf);
1012                 break;
1013         case 4 :
1014                 return target_buffer_get_u32(target, buf);
1015                 break;
1016         default :
1017                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1018                 return 0;
1019         }
1020 }
1021
1022 static int cfi_intel_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1023 {
1024         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1025         target_t *target = bank->target;
1026         reg_param_t reg_params[7];
1027         armv4_5_algorithm_t armv4_5_info;
1028         working_area_t *source;
1029         u32 buffer_size = 32768;
1030         u32 write_command_val, busy_pattern_val, error_pattern_val;
1031
1032         /* algorithm register usage:
1033          * r0: source address (in RAM)
1034          * r1: target address (in Flash)
1035          * r2: count
1036          * r3: flash write command
1037          * r4: status byte (returned to host)
1038          * r5: busy test pattern
1039          * r6: error test pattern
1040          */
1041
1042         static const u32 word_32_code[] = {
1043                 0xe4904004,   /* loop:  ldr r4, [r0], #4 */
1044                 0xe5813000,   /*                str r3, [r1] */
1045                 0xe5814000,   /*                str r4, [r1] */
1046                 0xe5914000,   /* busy:  ldr r4, [r1] */
1047                 0xe0047005,   /*                and r7, r4, r5 */
1048                 0xe1570005,   /*                cmp r7, r5 */
1049                 0x1afffffb,   /*                bne busy */
1050                 0xe1140006,   /*                tst r4, r6 */
1051                 0x1a000003,   /*                bne done */
1052                 0xe2522001,   /*                subs r2, r2, #1 */
1053                 0x0a000001,   /*                beq done */
1054                 0xe2811004,   /*                add r1, r1 #4 */
1055                 0xeafffff2,   /*                b loop */
1056                 0xeafffffe    /* done:  b -2 */
1057         };
1058
1059         static const u32 word_16_code[] = {
1060                 0xe0d040b2,   /* loop:  ldrh r4, [r0], #2 */
1061                 0xe1c130b0,   /*                strh r3, [r1] */
1062                 0xe1c140b0,   /*                strh r4, [r1] */
1063                 0xe1d140b0,   /* busy   ldrh r4, [r1] */
1064                 0xe0047005,   /*                and r7, r4, r5 */
1065                 0xe1570005,   /*                cmp r7, r5 */
1066                 0x1afffffb,   /*                bne busy */
1067                 0xe1140006,   /*                tst r4, r6 */
1068                 0x1a000003,   /*                bne done */
1069                 0xe2522001,   /*                subs r2, r2, #1 */
1070                 0x0a000001,   /*                beq done */
1071                 0xe2811002,   /*                add r1, r1 #2 */
1072                 0xeafffff2,   /*                b loop */
1073                 0xeafffffe    /* done:  b -2 */
1074         };
1075
1076         static const u32 word_8_code[] = {
1077                 0xe4d04001,   /* loop:  ldrb r4, [r0], #1 */
1078                 0xe5c13000,   /*                strb r3, [r1] */
1079                 0xe5c14000,   /*                strb r4, [r1] */
1080                 0xe5d14000,   /* busy   ldrb r4, [r1] */
1081                 0xe0047005,   /*                and r7, r4, r5 */
1082                 0xe1570005,   /*                cmp r7, r5 */
1083                 0x1afffffb,   /*                bne busy */
1084                 0xe1140006,   /*                tst r4, r6 */
1085                 0x1a000003,   /*                bne done */
1086                 0xe2522001,   /*                subs r2, r2, #1 */
1087                 0x0a000001,   /*                beq done */
1088                 0xe2811001,   /*                add r1, r1 #1 */
1089                 0xeafffff2,   /*                b loop */
1090                 0xeafffffe    /* done:  b -2 */
1091         };
1092         u8 target_code[4*CFI_MAX_INTEL_CODESIZE];
1093         const u32 *target_code_src;
1094         u32 target_code_size;
1095         int retval = ERROR_OK;
1096
1097
1098         cfi_intel_clear_status_register(bank);
1099
1100         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1101         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1102         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1103
1104         /* If we are setting up the write_algorith, we need target_code_src */
1105         /* if not we only need target_code_size.                                                                                                                */
1106         /*                                                                                                                                                                                                                                                                      */
1107         /* However, we don't want to create multiple code paths, so we                  */
1108         /* do the unecessary evaluation of target_code_src, which the                   */
1109         /* compiler will probably nicely optimize away if not needed                            */
1110
1111         /* prepare algorithm code for target endian */
1112         switch (bank->bus_width)
1113         {
1114         case 1 :
1115                 target_code_src = word_8_code;
1116                 target_code_size = sizeof(word_8_code);
1117                 break;
1118         case 2 :
1119                 target_code_src = word_16_code;
1120                 target_code_size = sizeof(word_16_code);
1121                 break;
1122         case 4 :
1123                 target_code_src = word_32_code;
1124                 target_code_size = sizeof(word_32_code);
1125                 break;
1126         default:
1127                 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1128                 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1129         }
1130
1131         /* flash write code */
1132         if (!cfi_info->write_algorithm)
1133         {
1134                 if ( target_code_size > sizeof(target_code) )
1135                 {
1136                         LOG_WARNING("Internal error - target code buffer to small. Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1137                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1138                 }
1139                 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1140
1141                 /* Get memory for block write handler */
1142                 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1143                 if (retval != ERROR_OK)
1144                 {
1145                         LOG_WARNING("No working area available, can't do block memory writes");
1146                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1147                 };
1148
1149                 /* write algorithm code to working area */
1150                 retval = target_write_buffer(target, cfi_info->write_algorithm->address, target_code_size, target_code);
1151                 if (retval != ERROR_OK)
1152                 {
1153                         LOG_ERROR("Unable to write block write code to target");
1154                         goto cleanup;
1155                 }
1156         }
1157
1158         /* Get a workspace buffer for the data to flash starting with 32k size.
1159            Half size until buffer would be smaller 256 Bytem then fail back */
1160         /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1161         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1162         {
1163                 buffer_size /= 2;
1164                 if (buffer_size <= 256)
1165                 {
1166                         LOG_WARNING("no large enough working area available, can't do block memory writes");
1167                         retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1168                         goto cleanup;
1169                 }
1170         };
1171
1172         /* setup algo registers */
1173         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1174         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1175         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1176         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1177         init_reg_param(&reg_params[4], "r4", 32, PARAM_IN);
1178         init_reg_param(&reg_params[5], "r5", 32, PARAM_OUT);
1179         init_reg_param(&reg_params[6], "r6", 32, PARAM_OUT);
1180
1181         /* prepare command and status register patterns */
1182         write_command_val = cfi_command_val(bank, 0x40);
1183         busy_pattern_val  = cfi_command_val(bank, 0x80);
1184         error_pattern_val = cfi_command_val(bank, 0x7e);
1185
1186         LOG_INFO("Using target buffer at 0x%08x and of size 0x%04x", source->address, buffer_size );
1187
1188         /* Programming main loop */
1189         while (count > 0)
1190         {
1191                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1192                 u32 wsm_error;
1193
1194                 if((retval = target_write_buffer(target, source->address, thisrun_count, buffer)) != ERROR_OK)
1195                 {
1196                         goto cleanup;
1197                 }
1198
1199                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1200                 buf_set_u32(reg_params[1].value, 0, 32, address);
1201                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1202
1203                 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1204                 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1205                 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1206
1207                 LOG_INFO("Write 0x%04x bytes to flash at 0x%08x", thisrun_count, address );
1208
1209                 /* Execute algorithm, assume breakpoint for last instruction */
1210                 retval = target->type->run_algorithm(target, 0, NULL, 7, reg_params,
1211                         cfi_info->write_algorithm->address,
1212                         cfi_info->write_algorithm->address + target_code_size - sizeof(u32),
1213                         10000, /* 10s should be enough for max. 32k of data */
1214                         &armv4_5_info);
1215
1216                 /* On failure try a fall back to direct word writes */
1217                 if (retval != ERROR_OK)
1218                 {
1219                         cfi_intel_clear_status_register(bank);
1220                         LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1221                         retval = ERROR_FLASH_OPERATION_FAILED;
1222                         /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1223                         /* FIXME To allow fall back or recovery, we must save the actual status
1224                            somewhere, so that a higher level code can start recovery. */
1225                         goto cleanup;
1226                 }
1227
1228                 /* Check return value from algo code */
1229                 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1230                 if (wsm_error)
1231                 {
1232                         /* read status register (outputs debug inforation) */
1233                         cfi_intel_wait_status_busy(bank, 100);
1234                         cfi_intel_clear_status_register(bank);
1235                         retval = ERROR_FLASH_OPERATION_FAILED;
1236                         goto cleanup;
1237                 }
1238
1239                 buffer += thisrun_count;
1240                 address += thisrun_count;
1241                 count -= thisrun_count;
1242         }
1243
1244         /* free up resources */
1245 cleanup:
1246         if (source)
1247                 target_free_working_area(target, source);
1248
1249         if (cfi_info->write_algorithm)
1250         {
1251                 target_free_working_area(target, cfi_info->write_algorithm);
1252                 cfi_info->write_algorithm = NULL;
1253         }
1254
1255         destroy_reg_param(&reg_params[0]);
1256         destroy_reg_param(&reg_params[1]);
1257         destroy_reg_param(&reg_params[2]);
1258         destroy_reg_param(&reg_params[3]);
1259         destroy_reg_param(&reg_params[4]);
1260         destroy_reg_param(&reg_params[5]);
1261         destroy_reg_param(&reg_params[6]);
1262
1263         return retval;
1264 }
1265
1266 static int cfi_spansion_write_block(struct flash_bank_s *bank, u8 *buffer, u32 address, u32 count)
1267 {
1268         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1269         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1270         target_t *target = bank->target;
1271         reg_param_t reg_params[10];
1272         armv4_5_algorithm_t armv4_5_info;
1273         working_area_t *source;
1274         u32 buffer_size = 32768;
1275         u32 status;
1276         int retval, retvaltemp;
1277         int exit_code = ERROR_OK;
1278
1279         /* input parameters - */
1280         /*      R0 = source address */
1281         /*      R1 = destination address */
1282         /*      R2 = number of writes */
1283         /*      R3 = flash write command */
1284         /*      R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1285         /* output parameters - */
1286         /*      R5 = 0x80 ok 0x00 bad */
1287         /* temp registers - */
1288         /*      R6 = value read from flash to test status */
1289         /*      R7 = holding register */
1290         /* unlock registers - */
1291         /*  R8 = unlock1_addr */
1292         /*  R9 = unlock1_cmd */
1293         /*  R10 = unlock2_addr */
1294         /*  R11 = unlock2_cmd */
1295
1296         static const u32 word_32_code[] = {
1297                                                 /* 00008100 <sp_32_code>:               */
1298                 0xe4905004,             /* ldr  r5, [r0], #4                    */
1299                 0xe5889000,     /* str  r9, [r8]                                */
1300                 0xe58ab000,     /* str  r11, [r10]                              */
1301                 0xe5883000,     /* str  r3, [r8]                                */
1302                 0xe5815000,     /* str  r5, [r1]                                */
1303                 0xe1a00000,     /* nop                                                  */
1304                                                 /*                                                              */
1305                                                 /* 00008110 <sp_32_busy>:               */
1306                 0xe5916000,     /* ldr  r6, [r1]                                */
1307                 0xe0257006,     /* eor  r7, r5, r6                              */
1308                 0xe0147007,     /* ands r7, r4, r7                              */
1309                 0x0a000007,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1310                 0xe0166124,     /* ands r6, r6, r4, lsr #2              */
1311                 0x0afffff9,     /* beq  8110 <sp_32_busy> ;     b if DQ5 low */
1312                 0xe5916000,     /* ldr  r6, [r1]                                */
1313                 0xe0257006,     /* eor  r7, r5, r6                              */
1314                 0xe0147007,     /* ands r7, r4, r7                              */
1315                 0x0a000001,     /* beq  8140 <sp_32_cont> ; b if DQ7 == Data7 */
1316                 0xe3a05000,     /* mov  r5, #0  ; 0x0 - return 0x00, error */
1317                 0x1a000004,     /* bne  8154 <sp_32_done>               */
1318                                                 /*                                                              */
1319                                 /* 00008140 <sp_32_cont>:                               */
1320                 0xe2522001,     /* subs r2, r2, #1      ; 0x1           */
1321                 0x03a05080,     /* moveq        r5, #128        ; 0x80  */
1322                 0x0a000001,     /* beq  8154 <sp_32_done>               */
1323                 0xe2811004,     /* add  r1, r1, #4      ; 0x4           */
1324                 0xeaffffe8,     /* b    8100 <sp_32_code>               */
1325                                                 /*                                                              */
1326                                                 /* 00008154 <sp_32_done>:               */
1327                 0xeafffffe              /* b    8154 <sp_32_done>               */
1328                 };
1329
1330                 static const u32 word_16_code[] = {
1331                                 /* 00008158 <sp_16_code>:              */
1332                 0xe0d050b2,     /* ldrh r5, [r0], #2               */
1333                 0xe1c890b0,     /* strh r9, [r8]                                */
1334                 0xe1cab0b0,     /* strh r11, [r10]                              */
1335                 0xe1c830b0,     /* strh r3, [r8]                                */
1336                 0xe1c150b0,     /* strh r5, [r1]                       */
1337                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1338                                 /*                                     */
1339                                 /* 00008168 <sp_16_busy>:              */
1340                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1341                 0xe0257006,     /* eor  r7, r5, r6                     */
1342                 0xe0147007,     /* ands r7, r4, r7                     */
1343                 0x0a000007,     /* beq  8198 <sp_16_cont>              */
1344                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1345                 0x0afffff9,     /* beq  8168 <sp_16_busy>              */
1346                 0xe1d160b0,     /* ldrh r6, [r1]                       */
1347                 0xe0257006,     /* eor  r7, r5, r6                     */
1348                 0xe0147007,     /* ands r7, r4, r7                     */
1349                 0x0a000001,     /* beq  8198 <sp_16_cont>              */
1350                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1351                 0x1a000004,     /* bne  81ac <sp_16_done>              */
1352                                 /*                                     */
1353                                 /* 00008198 <sp_16_cont>:              */
1354                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1355                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1356                 0x0a000001,     /* beq  81ac <sp_16_done>              */
1357                 0xe2811002,     /* add  r1, r1, #2      ; 0x2          */
1358                 0xeaffffe8,     /* b    8158 <sp_16_code>              */
1359                                 /*                                     */
1360                                 /* 000081ac <sp_16_done>:              */
1361                 0xeafffffe      /* b    81ac <sp_16_done>              */
1362                 };
1363
1364                 static const u32 word_8_code[] = {
1365                                 /* 000081b0 <sp_16_code_end>:          */
1366                 0xe4d05001,     /* ldrb r5, [r0], #1                   */
1367                 0xe5c89000,     /* strb r9, [r8]                                */
1368                 0xe5cab000,     /* strb r11, [r10]                              */
1369                 0xe5c83000,     /* strb r3, [r8]                                */
1370                 0xe5c15000,     /* strb r5, [r1]                       */
1371                 0xe1a00000,     /* nop                  (mov r0,r0)    */
1372                                 /*                                     */
1373                                 /* 000081c0 <sp_8_busy>:               */
1374                 0xe5d16000,     /* ldrb r6, [r1]                       */
1375                 0xe0257006,     /* eor  r7, r5, r6                     */
1376                 0xe0147007,     /* ands r7, r4, r7                     */
1377                 0x0a000007,     /* beq  81f0 <sp_8_cont>               */
1378                 0xe0166124,     /* ands r6, r6, r4, lsr #2             */
1379                 0x0afffff9,     /* beq  81c0 <sp_8_busy>               */
1380                 0xe5d16000,     /* ldrb r6, [r1]                       */
1381                 0xe0257006,     /* eor  r7, r5, r6                     */
1382                 0xe0147007,     /* ands r7, r4, r7                     */
1383                 0x0a000001,     /* beq  81f0 <sp_8_cont>               */
1384                 0xe3a05000,     /* mov  r5, #0  ; 0x0                  */
1385                 0x1a000004,     /* bne  8204 <sp_8_done>               */
1386                                 /*                                     */
1387                                 /* 000081f0 <sp_8_cont>:               */
1388                 0xe2522001,     /* subs r2, r2, #1      ; 0x1          */
1389                 0x03a05080,     /* moveq        r5, #128        ; 0x80 */
1390                 0x0a000001,     /* beq  8204 <sp_8_done>               */
1391                 0xe2811001,     /* add  r1, r1, #1      ; 0x1          */
1392                 0xeaffffe8,     /* b    81b0 <sp_16_code_end>          */
1393                                 /*                                     */
1394                                 /* 00008204 <sp_8_done>:               */
1395                 0xeafffffe      /* b    8204 <sp_8_done>               */
1396         };
1397
1398         armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
1399         armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
1400         armv4_5_info.core_state = ARMV4_5_STATE_ARM;
1401
1402         /* flash write code */
1403         if (!cfi_info->write_algorithm)
1404         {
1405                 u8 *target_code;
1406                 int target_code_size;
1407                 const u32 *src;
1408
1409                 /* convert bus-width dependent algorithm code to correct endiannes */
1410                 switch (bank->bus_width)
1411                 {
1412                 case 1:
1413                         src = word_8_code;
1414                         target_code_size = sizeof(word_8_code);
1415                         break;
1416                 case 2:
1417                         src = word_16_code;
1418                         target_code_size = sizeof(word_16_code);
1419                         break;
1420                 case 4:
1421                         src = word_32_code;
1422                         target_code_size = sizeof(word_32_code);
1423                         break;
1424                 default:
1425                         LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1426                         return ERROR_FLASH_OPERATION_FAILED;
1427                 }
1428                 target_code = malloc(target_code_size);
1429                 cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
1430
1431                 /* allocate working area */
1432                 retval=target_alloc_working_area(target, target_code_size,
1433                                 &cfi_info->write_algorithm);
1434                 if (retval != ERROR_OK)
1435                 {
1436                         free(target_code);
1437                         return retval;
1438                 }
1439
1440                 /* write algorithm code to working area */
1441                 if((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1442                                     target_code_size, target_code)) != ERROR_OK)
1443                 {
1444                         free(target_code);
1445                         return retval;
1446                 }
1447
1448                 free(target_code);
1449         }
1450         /* the following code still assumes target code is fixed 24*4 bytes */
1451
1452         while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
1453         {
1454                 buffer_size /= 2;
1455                 if (buffer_size <= 256)
1456                 {
1457                         /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
1458                         if (cfi_info->write_algorithm)
1459                                 target_free_working_area(target, cfi_info->write_algorithm);
1460
1461                         LOG_WARNING("not enough working area available, can't do block memory writes");
1462                         return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1463                 }
1464         };
1465
1466         init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1467         init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1468         init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
1469         init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
1470         init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
1471         init_reg_param(&reg_params[5], "r5", 32, PARAM_IN);
1472         init_reg_param(&reg_params[6], "r8", 32, PARAM_OUT);
1473         init_reg_param(&reg_params[7], "r9", 32, PARAM_OUT);
1474         init_reg_param(&reg_params[8], "r10", 32, PARAM_OUT);
1475         init_reg_param(&reg_params[9], "r11", 32, PARAM_OUT);
1476
1477         while (count > 0)
1478         {
1479                 u32 thisrun_count = (count > buffer_size) ? buffer_size : count;
1480
1481                 retvaltemp = target_write_buffer(target, source->address, thisrun_count, buffer);
1482
1483                 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1484                 buf_set_u32(reg_params[1].value, 0, 32, address);
1485                 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1486                 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1487                 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1488                 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1489                 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1490                 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1491                 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1492
1493                 retval = target->type->run_algorithm(target, 0, NULL, 10, reg_params,
1494                                                      cfi_info->write_algorithm->address,
1495                                                      cfi_info->write_algorithm->address + ((24 * 4) - 4),
1496                                                      10000, &armv4_5_info);
1497
1498                 status = buf_get_u32(reg_params[5].value, 0, 32);
1499
1500                 if ((retval != ERROR_OK) || (retvaltemp != ERROR_OK) || status != 0x80)
1501                 {
1502                         LOG_DEBUG("status: 0x%x", status);
1503                         exit_code = ERROR_FLASH_OPERATION_FAILED;
1504                         break;
1505                 }
1506
1507                 buffer += thisrun_count;
1508                 address += thisrun_count;
1509                 count -= thisrun_count;
1510         }
1511
1512         target_free_working_area(target, source);
1513
1514         destroy_reg_param(&reg_params[0]);
1515         destroy_reg_param(&reg_params[1]);
1516         destroy_reg_param(&reg_params[2]);
1517         destroy_reg_param(&reg_params[3]);
1518         destroy_reg_param(&reg_params[4]);
1519         destroy_reg_param(&reg_params[5]);
1520         destroy_reg_param(&reg_params[6]);
1521         destroy_reg_param(&reg_params[7]);
1522         destroy_reg_param(&reg_params[8]);
1523         destroy_reg_param(&reg_params[9]);
1524
1525         return exit_code;
1526 }
1527
1528 static int cfi_intel_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1529 {
1530         int retval;
1531         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1532         target_t *target = bank->target;
1533         u8 command[8];
1534
1535         cfi_intel_clear_status_register(bank);
1536         cfi_command(bank, 0x40, command);
1537         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1538         {
1539                 return retval;
1540         }
1541
1542         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1543         {
1544                 return retval;
1545         }
1546
1547         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != 0x80)
1548         {
1549                 cfi_command(bank, 0xff, command);
1550                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1551                 {
1552                         return retval;
1553                 }
1554
1555                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1556                 return ERROR_FLASH_OPERATION_FAILED;
1557         }
1558
1559         return ERROR_OK;
1560 }
1561
1562 static int cfi_intel_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1563 {
1564         int retval;
1565         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1566         target_t *target = bank->target;
1567         u8 command[8];
1568
1569         /* Calculate buffer size and boundary mask */
1570         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1571         u32 buffermask = buffersize-1;
1572         u32 bufferwsize;
1573
1574         /* Check for valid range */
1575         if (address & buffermask)
1576         {
1577                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1578                 return ERROR_FLASH_OPERATION_FAILED;
1579         }
1580         switch(bank->chip_width)
1581         {
1582         case 4 : bufferwsize = buffersize / 4; break;
1583         case 2 : bufferwsize = buffersize / 2; break;
1584         case 1 : bufferwsize = buffersize; break;
1585         default:
1586                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1587                 return ERROR_FLASH_OPERATION_FAILED;
1588         }
1589
1590         bufferwsize/=(bank->bus_width / bank->chip_width);
1591
1592
1593         /* Check for valid size */
1594         if (wordcount > bufferwsize)
1595         {
1596                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1597                 return ERROR_FLASH_OPERATION_FAILED;
1598         }
1599
1600         /* Write to flash buffer */
1601         cfi_intel_clear_status_register(bank);
1602
1603         /* Initiate buffer operation _*/
1604         cfi_command(bank, 0xE8, command);
1605         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1606         {
1607                 return retval;
1608         }
1609         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1610         {
1611                 cfi_command(bank, 0xff, command);
1612                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1613                 {
1614                         return retval;
1615                 }
1616
1617                 LOG_ERROR("couldn't start buffer write operation at base 0x%x, address %x", bank->base, address);
1618                 return ERROR_FLASH_OPERATION_FAILED;
1619         }
1620
1621         /* Write buffer wordcount-1 and data words */
1622         cfi_command(bank, bufferwsize-1, command);
1623         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1624         {
1625                 return retval;
1626         }
1627
1628         if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1629         {
1630                 return retval;
1631         }
1632
1633         /* Commit write operation */
1634         cfi_command(bank, 0xd0, command);
1635         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1636         {
1637                 return retval;
1638         }
1639         if (cfi_intel_wait_status_busy(bank, 1000 * (1 << cfi_info->buf_write_timeout_max)) != 0x80)
1640         {
1641                 cfi_command(bank, 0xff, command);
1642                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1643                 {
1644                         return retval;
1645                 }
1646
1647                 LOG_ERROR("Buffer write at base 0x%x, address %x failed.", bank->base, address);
1648                 return ERROR_FLASH_OPERATION_FAILED;
1649         }
1650
1651         return ERROR_OK;
1652 }
1653
1654 static int cfi_spansion_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1655 {
1656         int retval;
1657         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1658         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1659         target_t *target = bank->target;
1660         u8 command[8];
1661
1662         cfi_command(bank, 0xaa, command);
1663         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1664         {
1665                 return retval;
1666         }
1667
1668         cfi_command(bank, 0x55, command);
1669         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1670         {
1671                 return retval;
1672         }
1673
1674         cfi_command(bank, 0xa0, command);
1675         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1676         {
1677                 return retval;
1678         }
1679
1680         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1681         {
1682                 return retval;
1683         }
1684
1685         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1686         {
1687                 cfi_command(bank, 0xf0, command);
1688                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1689                 {
1690                         return retval;
1691                 }
1692
1693                 LOG_ERROR("couldn't write word at base 0x%x, address %x", bank->base, address);
1694                 return ERROR_FLASH_OPERATION_FAILED;
1695         }
1696
1697         return ERROR_OK;
1698 }
1699
1700 static int cfi_spansion_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1701 {
1702         int retval;
1703         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1704         target_t *target = bank->target;
1705         u8 command[8];
1706         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
1707
1708         /* Calculate buffer size and boundary mask */
1709         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1710         u32 buffermask = buffersize-1;
1711         u32 bufferwsize;
1712
1713         /* Check for valid range */
1714         if (address & buffermask)
1715         {
1716                 LOG_ERROR("Write address at base 0x%x, address %x not aligned to 2^%d boundary", bank->base, address, cfi_info->max_buf_write_size);
1717                 return ERROR_FLASH_OPERATION_FAILED;
1718         }
1719         switch(bank->chip_width)
1720         {
1721         case 4 : bufferwsize = buffersize / 4; break;
1722         case 2 : bufferwsize = buffersize / 2; break;
1723         case 1 : bufferwsize = buffersize; break;
1724         default:
1725                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1726                 return ERROR_FLASH_OPERATION_FAILED;
1727         }
1728
1729         bufferwsize/=(bank->bus_width / bank->chip_width);
1730
1731         /* Check for valid size */
1732         if (wordcount > bufferwsize)
1733         {
1734                 LOG_ERROR("Number of data words %d exceeds available buffersize %d", wordcount, buffersize);
1735                 return ERROR_FLASH_OPERATION_FAILED;
1736         }
1737
1738         // Unlock
1739         cfi_command(bank, 0xaa, command);
1740         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
1741         {
1742                 return retval;
1743         }
1744
1745         cfi_command(bank, 0x55, command);
1746         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
1747         {
1748                 return retval;
1749         }
1750
1751         // Buffer load command
1752         cfi_command(bank, 0x25, command);
1753         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1754         {
1755                 return retval;
1756         }
1757
1758         /* Write buffer wordcount-1 and data words */
1759         cfi_command(bank, bufferwsize-1, command);
1760         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1761         {
1762                 return retval;
1763         }
1764
1765         if((retval = target->type->write_memory(target, address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1766         {
1767                 return retval;
1768         }
1769
1770         /* Commit write operation */
1771         cfi_command(bank, 0x29, command);
1772         if((retval = target->type->write_memory(target, address, bank->bus_width, 1, command)) != ERROR_OK)
1773         {
1774                 return retval;
1775         }
1776
1777         if (cfi_spansion_wait_status_busy(bank, 1000 * (1 << cfi_info->word_write_timeout_max)) != ERROR_OK)
1778         {
1779                 cfi_command(bank, 0xf0, command);
1780                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
1781                 {
1782                         return retval;
1783                 }
1784
1785                 LOG_ERROR("couldn't write block at base 0x%x, address %x, size %x", bank->base, address, bufferwsize);
1786                 return ERROR_FLASH_OPERATION_FAILED;
1787         }
1788
1789         return ERROR_OK;
1790 }
1791
1792 static int cfi_write_word(struct flash_bank_s *bank, u8 *word, u32 address)
1793 {
1794         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1795
1796         switch(cfi_info->pri_id)
1797         {
1798                 case 1:
1799                 case 3:
1800                         return cfi_intel_write_word(bank, word, address);
1801                         break;
1802                 case 2:
1803                         return cfi_spansion_write_word(bank, word, address);
1804                         break;
1805                 default:
1806                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1807                         break;
1808         }
1809
1810         return ERROR_FLASH_OPERATION_FAILED;
1811 }
1812
1813 static int cfi_write_words(struct flash_bank_s *bank, u8 *word, u32 wordcount, u32 address)
1814 {
1815         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1816
1817         switch(cfi_info->pri_id)
1818         {
1819                 case 1:
1820                 case 3:
1821                         return cfi_intel_write_words(bank, word, wordcount, address);
1822                         break;
1823                 case 2:
1824                         return cfi_spansion_write_words(bank, word, wordcount, address);
1825                         break;
1826                 default:
1827                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1828                         break;
1829         }
1830
1831         return ERROR_FLASH_OPERATION_FAILED;
1832 }
1833
1834 int cfi_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
1835 {
1836         cfi_flash_bank_t *cfi_info = bank->driver_priv;
1837         target_t *target = bank->target;
1838         u32 address = bank->base + offset;      /* address of first byte to be programmed */
1839         u32 write_p, copy_p;
1840         int align;      /* number of unaligned bytes */
1841         int blk_count; /* number of bus_width bytes for block copy */
1842         u8 current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
1843         int i;
1844         int retval;
1845
1846         if (bank->target->state != TARGET_HALTED)
1847         {
1848                 LOG_ERROR("Target not halted");
1849                 return ERROR_TARGET_NOT_HALTED;
1850         }
1851
1852         if (offset + count > bank->size)
1853                 return ERROR_FLASH_DST_OUT_OF_BANK;
1854
1855         if (cfi_info->qry[0] != 'Q')
1856                 return ERROR_FLASH_BANK_NOT_PROBED;
1857
1858         /* start at the first byte of the first word (bus_width size) */
1859         write_p = address & ~(bank->bus_width - 1);
1860         if ((align = address - write_p) != 0)
1861         {
1862                 LOG_INFO("Fixup %d unaligned head bytes", align );
1863
1864                 for (i = 0; i < bank->bus_width; i++)
1865                         current_word[i] = 0;
1866                 copy_p = write_p;
1867
1868                 /* copy bytes before the first write address */
1869                 for (i = 0; i < align; ++i, ++copy_p)
1870                 {
1871                         u8 byte;
1872                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1873                         {
1874                                 return retval;
1875                         }
1876                         cfi_add_byte(bank, current_word, byte);
1877                 }
1878
1879                 /* add bytes from the buffer */
1880                 for (; (i < bank->bus_width) && (count > 0); i++)
1881                 {
1882                         cfi_add_byte(bank, current_word, *buffer++);
1883                         count--;
1884                         copy_p++;
1885                 }
1886
1887                 /* if the buffer is already finished, copy bytes after the last write address */
1888                 for (; (count == 0) && (i < bank->bus_width); ++i, ++copy_p)
1889                 {
1890                         u8 byte;
1891                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
1892                         {
1893                                 return retval;
1894                         }
1895                         cfi_add_byte(bank, current_word, byte);
1896                 }
1897
1898                 retval = cfi_write_word(bank, current_word, write_p);
1899                 if (retval != ERROR_OK)
1900                         return retval;
1901                 write_p = copy_p;
1902         }
1903
1904         /* handle blocks of bus_size aligned bytes */
1905         blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
1906         switch(cfi_info->pri_id)
1907         {
1908                 /* try block writes (fails without working area) */
1909                 case 1:
1910                 case 3:
1911                         retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
1912                         break;
1913                 case 2:
1914                         retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
1915                         break;
1916                 default:
1917                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1918                         retval = ERROR_FLASH_OPERATION_FAILED;
1919                         break;
1920         }
1921         if (retval == ERROR_OK)
1922         {
1923                 /* Increment pointers and decrease count on succesful block write */
1924                 buffer += blk_count;
1925                 write_p += blk_count;
1926                 count -= blk_count;
1927         }
1928         else
1929         {
1930                 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
1931                 {
1932                         //adjust buffersize for chip width
1933                         u32 buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1934                         u32 buffermask = buffersize-1;
1935                         u32 bufferwsize;
1936
1937                         switch(bank->chip_width)
1938                         {
1939                         case 4 : bufferwsize = buffersize / 4; break;
1940                         case 2 : bufferwsize = buffersize / 2; break;
1941                         case 1 : bufferwsize = buffersize; break;
1942                         default:
1943                                 LOG_ERROR("Unsupported chip width %d", bank->chip_width);
1944                                 return ERROR_FLASH_OPERATION_FAILED;
1945                         }
1946
1947                         bufferwsize/=(bank->bus_width / bank->chip_width);
1948
1949                         /* fall back to memory writes */
1950                         while (count >= (u32)bank->bus_width)
1951                         {
1952                                 int fallback;
1953                                 if ((write_p & 0xff) == 0)
1954                                 {
1955                                         LOG_INFO("Programming at %08x, count %08x bytes remaining", write_p, count);
1956                                 }
1957                                 fallback = 1;
1958                                 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
1959                                 {
1960                                         retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
1961                                         if (retval == ERROR_OK)
1962                                         {
1963                                                 buffer += buffersize;
1964                                                 write_p += buffersize;
1965                                                 count -= buffersize;
1966                                                 fallback=0;
1967                                         }
1968                                 }
1969                                 /* try the slow way? */
1970                                 if (fallback)
1971                                 {
1972                                         for (i = 0; i < bank->bus_width; i++)
1973                                                 current_word[i] = 0;
1974
1975                                         for (i = 0; i < bank->bus_width; i++)
1976                                         {
1977                                                 cfi_add_byte(bank, current_word, *buffer++);
1978                                         }
1979
1980                                         retval = cfi_write_word(bank, current_word, write_p);
1981                                         if (retval != ERROR_OK)
1982                                                 return retval;
1983
1984                                         write_p += bank->bus_width;
1985                                         count -= bank->bus_width;
1986                                 }
1987                         }
1988                 }
1989                 else
1990                         return retval;
1991         }
1992
1993         /* return to read array mode, so we can read from flash again for padding */
1994         cfi_command(bank, 0xf0, current_word);
1995         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
1996         {
1997                 return retval;
1998         }
1999         cfi_command(bank, 0xff, current_word);
2000         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2001         {
2002                 return retval;
2003         }
2004
2005         /* handle unaligned tail bytes */
2006         if (count > 0)
2007         {
2008                 LOG_INFO("Fixup %d unaligned tail bytes", count );
2009
2010                 copy_p = write_p;
2011                 for (i = 0; i < bank->bus_width; i++)
2012                         current_word[i] = 0;
2013
2014                 for (i = 0; (i < bank->bus_width) && (count > 0); ++i, ++copy_p)
2015                 {
2016                         cfi_add_byte(bank, current_word, *buffer++);
2017                         count--;
2018                 }
2019                 for (; i < bank->bus_width; ++i, ++copy_p)
2020                 {
2021                         u8 byte;
2022                         if((retval = target->type->read_memory(target, copy_p, 1, 1, &byte)) != ERROR_OK)
2023                         {
2024                                 return retval;
2025                         }
2026                         cfi_add_byte(bank, current_word, byte);
2027                 }
2028                 retval = cfi_write_word(bank, current_word, write_p);
2029                 if (retval != ERROR_OK)
2030                         return retval;
2031         }
2032
2033         /* return to read array mode */
2034         cfi_command(bank, 0xf0, current_word);
2035         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word)) != ERROR_OK)
2036         {
2037                 return retval;
2038         }
2039         cfi_command(bank, 0xff, current_word);
2040         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, current_word);
2041 }
2042
2043 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *bank, void *param)
2044 {
2045         (void) param;
2046         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2047         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2048
2049         pri_ext->_reversed_geometry = 1;
2050 }
2051
2052 static void cfi_fixup_0002_erase_regions(flash_bank_t *bank, void *param)
2053 {
2054         int i;
2055         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2056         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2057         (void) param;
2058
2059         if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2060         {
2061                 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2062
2063                 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2064                 {
2065                         int j = (cfi_info->num_erase_regions - 1) - i;
2066                         u32 swap;
2067
2068                         swap = cfi_info->erase_region_info[i];
2069                         cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2070                         cfi_info->erase_region_info[j] = swap;
2071                 }
2072         }
2073 }
2074
2075 static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
2076 {
2077         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2078         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2079         cfi_unlock_addresses_t *unlock_addresses = param;
2080
2081         pri_ext->_unlock1 = unlock_addresses->unlock1;
2082         pri_ext->_unlock2 = unlock_addresses->unlock2;
2083 }
2084
2085 static int cfi_probe(struct flash_bank_s *bank)
2086 {
2087         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2088         target_t *target = bank->target;
2089         u8 command[8];
2090         int num_sectors = 0;
2091         int i;
2092         int sector = 0;
2093         u32 unlock1 = 0x555;
2094         u32 unlock2 = 0x2aa;
2095         int retval;
2096
2097         if (bank->target->state != TARGET_HALTED)
2098         {
2099                 LOG_ERROR("Target not halted");
2100                 return ERROR_TARGET_NOT_HALTED;
2101         }
2102
2103         cfi_info->probed = 0;
2104
2105         /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2106          * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2107          */
2108         if (cfi_info->jedec_probe)
2109         {
2110                 unlock1 = 0x5555;
2111                 unlock2 = 0x2aaa;
2112         }
2113
2114         /* switch to read identifier codes mode ("AUTOSELECT") */
2115         cfi_command(bank, 0xaa, command);
2116         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2117         {
2118                 return retval;
2119         }
2120         cfi_command(bank, 0x55, command);
2121         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2122         {
2123                 return retval;
2124         }
2125         cfi_command(bank, 0x90, command);
2126         if((retval = target->type->write_memory(target, flash_address(bank, 0, unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2127         {
2128                 return retval;
2129         }
2130
2131         if (bank->chip_width == 1)
2132         {
2133                 u8 manufacturer, device_id;
2134                 if((retval = target_read_u8(target, flash_address(bank, 0, 0x00), &manufacturer)) != ERROR_OK)
2135                 {
2136                         return retval;
2137                 }
2138                 if((retval = target_read_u8(target, flash_address(bank, 0, 0x01), &device_id)) != ERROR_OK)
2139                 {
2140                         return retval;
2141                 }
2142                 cfi_info->manufacturer = manufacturer;
2143                 cfi_info->device_id = device_id;
2144         }
2145         else if (bank->chip_width == 2)
2146         {
2147                 if((retval = target_read_u16(target, flash_address(bank, 0, 0x00), &cfi_info->manufacturer)) != ERROR_OK)
2148                 {
2149                         return retval;
2150                 }
2151                 if((retval = target_read_u16(target, flash_address(bank, 0, 0x02), &cfi_info->device_id)) != ERROR_OK)
2152                 {
2153                         return retval;
2154                 }
2155         }
2156
2157         LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x", cfi_info->manufacturer, cfi_info->device_id);
2158         /* switch back to read array mode */
2159         cfi_command(bank, 0xf0, command);
2160         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2161         {
2162                 return retval;
2163         }
2164         cfi_command(bank, 0xff, command);
2165         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x00), bank->bus_width, 1, command)) != ERROR_OK)
2166         {
2167                 return retval;
2168         }
2169
2170         /* check device/manufacturer ID for known non-CFI flashes. */
2171         cfi_fixup_non_cfi(bank);
2172
2173         /* query only if this is a CFI compatible flash,
2174          * otherwise the relevant info has already been filled in
2175          */
2176         if (cfi_info->not_cfi == 0)
2177         {
2178                 /* enter CFI query mode
2179                  * according to JEDEC Standard No. 68.01,
2180                  * a single bus sequence with address = 0x55, data = 0x98 should put
2181                  * the device into CFI query mode.
2182                  *
2183                  * SST flashes clearly violate this, and we will consider them incompatbile for now
2184                  */
2185                 cfi_command(bank, 0x98, command);
2186                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2187                 {
2188                         return retval;
2189                 }
2190
2191                 cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
2192                 cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
2193                 cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
2194
2195                 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2196
2197                 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2198                 {
2199                         cfi_command(bank, 0xf0, command);
2200                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2201                         {
2202                                 return retval;
2203                         }
2204                         cfi_command(bank, 0xff, command);
2205                         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2206                         {
2207                                 return retval;
2208                         }
2209                         LOG_ERROR("Could not probe bank: no QRY");
2210                         return ERROR_FLASH_BANK_INVALID;
2211                 }
2212
2213                 cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
2214                 cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);
2215                 cfi_info->alt_id = cfi_query_u16(bank, 0, 0x17);
2216                 cfi_info->alt_addr = cfi_query_u16(bank, 0, 0x19);
2217
2218                 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2219
2220                 cfi_info->vcc_min = cfi_query_u8(bank, 0, 0x1b);
2221                 cfi_info->vcc_max = cfi_query_u8(bank, 0, 0x1c);
2222                 cfi_info->vpp_min = cfi_query_u8(bank, 0, 0x1d);
2223                 cfi_info->vpp_max = cfi_query_u8(bank, 0, 0x1e);
2224                 cfi_info->word_write_timeout_typ = cfi_query_u8(bank, 0, 0x1f);
2225                 cfi_info->buf_write_timeout_typ = cfi_query_u8(bank, 0, 0x20);
2226                 cfi_info->block_erase_timeout_typ = cfi_query_u8(bank, 0, 0x21);
2227                 cfi_info->chip_erase_timeout_typ = cfi_query_u8(bank, 0, 0x22);
2228                 cfi_info->word_write_timeout_max = cfi_query_u8(bank, 0, 0x23);
2229                 cfi_info->buf_write_timeout_max = cfi_query_u8(bank, 0, 0x24);
2230                 cfi_info->block_erase_timeout_max = cfi_query_u8(bank, 0, 0x25);
2231                 cfi_info->chip_erase_timeout_max = cfi_query_u8(bank, 0, 0x26);
2232
2233                 LOG_DEBUG("Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x",
2234                         (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2235                         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2236                         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2237                         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2238                 LOG_DEBUG("typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u", 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2239                         1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2240                 LOG_DEBUG("max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u", (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2241                         (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2242                         (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2243                         (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2244
2245                 cfi_info->dev_size = 1<<cfi_query_u8(bank, 0, 0x27);
2246                 cfi_info->interface_desc = cfi_query_u16(bank, 0, 0x28);
2247                 cfi_info->max_buf_write_size = cfi_query_u16(bank, 0, 0x2a);
2248                 cfi_info->num_erase_regions = cfi_query_u8(bank, 0, 0x2c);
2249
2250                 LOG_DEBUG("size: 0x%x, interface desc: %i, max buffer write size: %x", cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2251
2252                 if (cfi_info->num_erase_regions)
2253                 {
2254                         cfi_info->erase_region_info = malloc(4 * cfi_info->num_erase_regions);
2255                         for (i = 0; i < cfi_info->num_erase_regions; i++)
2256                         {
2257                                 cfi_info->erase_region_info[i] = cfi_query_u32(bank, 0, 0x2d + (4 * i));
2258                                 LOG_DEBUG("erase region[%i]: %i blocks of size 0x%x", i, (cfi_info->erase_region_info[i] & 0xffff) + 1, (cfi_info->erase_region_info[i] >> 16) * 256);
2259                         }
2260                 }
2261                 else
2262                 {
2263                         cfi_info->erase_region_info = NULL;
2264                 }
2265
2266                 /* We need to read the primary algorithm extended query table before calculating
2267                  * the sector layout to be able to apply fixups
2268                  */
2269                 switch(cfi_info->pri_id)
2270                 {
2271                         /* Intel command set (standard and extended) */
2272                         case 0x0001:
2273                         case 0x0003:
2274                                 cfi_read_intel_pri_ext(bank);
2275                                 break;
2276                         /* AMD/Spansion, Atmel, ... command set */
2277                         case 0x0002:
2278                                 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2279                                 cfi_read_0002_pri_ext(bank);
2280                                 break;
2281                         default:
2282                                 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2283                                 break;
2284                 }
2285
2286                 /* return to read array mode
2287                  * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2288                  */
2289                 cfi_command(bank, 0xf0, command);
2290                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2291                 {
2292                         return retval;
2293                 }
2294                 cfi_command(bank, 0xff, command);
2295                 if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
2296                 {
2297                         return retval;
2298                 }
2299         } /* end CFI case */
2300
2301         /* apply fixups depending on the primary command set */
2302         switch(cfi_info->pri_id)
2303         {
2304                 /* Intel command set (standard and extended) */
2305                 case 0x0001:
2306                 case 0x0003:
2307                         cfi_fixup(bank, cfi_0001_fixups);
2308                         break;
2309                 /* AMD/Spansion, Atmel, ... command set */
2310                 case 0x0002:
2311                         cfi_fixup(bank, cfi_0002_fixups);
2312                         break;
2313                 default:
2314                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2315                         break;
2316         }
2317
2318         if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2319         {
2320                 LOG_WARNING("configuration specifies 0x%x size, but a 0x%x size flash was found", bank->size, cfi_info->dev_size);
2321         }
2322
2323         if (cfi_info->num_erase_regions == 0)
2324         {
2325                 /* a device might have only one erase block, spanning the whole device */
2326                 bank->num_sectors = 1;
2327                 bank->sectors = malloc(sizeof(flash_sector_t));
2328
2329                 bank->sectors[sector].offset = 0x0;
2330                 bank->sectors[sector].size = bank->size;
2331                 bank->sectors[sector].is_erased = -1;
2332                 bank->sectors[sector].is_protected = -1;
2333         }
2334         else
2335         {
2336                 u32 offset = 0;
2337
2338                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2339                 {
2340                         num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2341                 }
2342
2343                 bank->num_sectors = num_sectors;
2344                 bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
2345
2346                 for (i = 0; i < cfi_info->num_erase_regions; i++)
2347                 {
2348                         u32 j;
2349                         for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2350                         {
2351                                 bank->sectors[sector].offset = offset;
2352                                 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256) * bank->bus_width / bank->chip_width;
2353                                 offset += bank->sectors[sector].size;
2354                                 bank->sectors[sector].is_erased = -1;
2355                                 bank->sectors[sector].is_protected = -1;
2356                                 sector++;
2357                         }
2358                 }
2359                 if (offset != cfi_info->dev_size)
2360                 {
2361                         LOG_WARNING("CFI size is 0x%x, but total sector size is 0x%x", cfi_info->dev_size, offset);
2362                 }
2363         }
2364
2365         cfi_info->probed = 1;
2366
2367         return ERROR_OK;
2368 }
2369
2370 static int cfi_auto_probe(struct flash_bank_s *bank)
2371 {
2372         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2373         if (cfi_info->probed)
2374                 return ERROR_OK;
2375         return cfi_probe(bank);
2376 }
2377
2378
2379 static int cfi_intel_protect_check(struct flash_bank_s *bank)
2380 {
2381         int retval;
2382         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2383         cfi_intel_pri_ext_t *pri_ext = cfi_info->pri_ext;
2384         target_t *target = bank->target;
2385         u8 command[CFI_MAX_BUS_WIDTH];
2386         int i;
2387
2388         /* check if block lock bits are supported on this device */
2389         if (!(pri_ext->blk_status_reg_mask & 0x1))
2390                 return ERROR_FLASH_OPERATION_FAILED;
2391
2392         cfi_command(bank, 0x90, command);
2393         if((retval = target->type->write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
2394         {
2395                 return retval;
2396         }
2397
2398         for (i = 0; i < bank->num_sectors; i++)
2399         {
2400                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2401
2402                 if (block_status & 1)
2403                         bank->sectors[i].is_protected = 1;
2404                 else
2405                         bank->sectors[i].is_protected = 0;
2406         }
2407
2408         cfi_command(bank, 0xff, command);
2409         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2410 }
2411
2412 static int cfi_spansion_protect_check(struct flash_bank_s *bank)
2413 {
2414         int retval;
2415         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2416         cfi_spansion_pri_ext_t *pri_ext = cfi_info->pri_ext;
2417         target_t *target = bank->target;
2418         u8 command[8];
2419         int i;
2420
2421         cfi_command(bank, 0xaa, command);
2422         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2423         {
2424                 return retval;
2425         }
2426
2427         cfi_command(bank, 0x55, command);
2428         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock2), bank->bus_width, 1, command)) != ERROR_OK)
2429         {
2430                 return retval;
2431         }
2432
2433         cfi_command(bank, 0x90, command);
2434         if((retval = target->type->write_memory(target, flash_address(bank, 0, pri_ext->_unlock1), bank->bus_width, 1, command)) != ERROR_OK)
2435         {
2436                 return retval;
2437         }
2438
2439         for (i = 0; i < bank->num_sectors; i++)
2440         {
2441                 u8 block_status = cfi_get_u8(bank, i, 0x2);
2442
2443                 if (block_status & 1)
2444                         bank->sectors[i].is_protected = 1;
2445                 else
2446                         bank->sectors[i].is_protected = 0;
2447         }
2448
2449         cfi_command(bank, 0xf0, command);
2450         return target->type->write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command);
2451 }
2452
2453 static int cfi_protect_check(struct flash_bank_s *bank)
2454 {
2455         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2456
2457         if (bank->target->state != TARGET_HALTED)
2458         {
2459                 LOG_ERROR("Target not halted");
2460                 return ERROR_TARGET_NOT_HALTED;
2461         }
2462
2463         if (cfi_info->qry[0] != 'Q')
2464                 return ERROR_FLASH_BANK_NOT_PROBED;
2465
2466         switch(cfi_info->pri_id)
2467         {
2468                 case 1:
2469                 case 3:
2470                         return cfi_intel_protect_check(bank);
2471                         break;
2472                 case 2:
2473                         return cfi_spansion_protect_check(bank);
2474                         break;
2475                 default:
2476                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2477                         break;
2478         }
2479
2480         return ERROR_OK;
2481 }
2482
2483 static int cfi_info(struct flash_bank_s *bank, char *buf, int buf_size)
2484 {
2485         int printed;
2486         cfi_flash_bank_t *cfi_info = bank->driver_priv;
2487
2488         if (cfi_info->qry[0] == (char)-1)
2489         {
2490                 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2491                 return ERROR_OK;
2492         }
2493
2494         if (cfi_info->not_cfi == 0)
2495                 printed = snprintf(buf, buf_size, "\ncfi information:\n");
2496         else
2497                 printed = snprintf(buf, buf_size, "\nnon-cfi flash:\n");
2498         buf += printed;
2499         buf_size -= printed;
2500
2501         printed = snprintf(buf, buf_size, "\nmfr: 0x%4.4x, id:0x%4.4x\n",
2502                 cfi_info->manufacturer, cfi_info->device_id);
2503         buf += printed;
2504         buf_size -= printed;
2505
2506         if (cfi_info->not_cfi == 0)
2507         {
2508         printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2509         buf += printed;
2510         buf_size -= printed;
2511
2512                 printed = snprintf(buf, buf_size, "Vcc min: %1.1x.%1.1x, Vcc max: %1.1x.%1.1x, Vpp min: %1.1x.%1.1x, Vpp max: %1.1x.%1.1x\n",
2513                                    (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2514         (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2515         (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2516         (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2517         buf += printed;
2518         buf_size -= printed;
2519
2520                 printed = snprintf(buf, buf_size, "typ. word write timeout: %u, typ. buf write timeout: %u, typ. block erase timeout: %u, typ. chip erase timeout: %u\n",
2521                                    1 << cfi_info->word_write_timeout_typ,
2522                                    1 << cfi_info->buf_write_timeout_typ,
2523                                    1 << cfi_info->block_erase_timeout_typ,
2524                                    1 << cfi_info->chip_erase_timeout_typ);
2525         buf += printed;
2526         buf_size -= printed;
2527
2528                 printed = snprintf(buf, buf_size, "max. word write timeout: %u, max. buf write timeout: %u, max. block erase timeout: %u, max. chip erase timeout: %u\n",
2529                                    (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2530                   (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2531                   (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2532                   (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2533         buf += printed;
2534         buf_size -= printed;
2535
2536                 printed = snprintf(buf, buf_size, "size: 0x%x, interface desc: %i, max buffer write size: %x\n",
2537                                    cfi_info->dev_size,
2538                                    cfi_info->interface_desc,
2539                                    1 << cfi_info->max_buf_write_size);
2540         buf += printed;
2541         buf_size -= printed;
2542
2543         switch(cfi_info->pri_id)
2544         {
2545                 case 1:
2546                 case 3:
2547                         cfi_intel_info(bank, buf, buf_size);
2548                         break;
2549                 case 2:
2550                         cfi_spansion_info(bank, buf, buf_size);
2551                         break;
2552                 default:
2553                         LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2554                         break;
2555         }
2556         }
2557
2558         return ERROR_OK;
2559 }