git.sur5r.net Git - openocd/blob - src/flash/davinci_nand.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by David Brownell                                  *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /*
  21  * DaVinci family NAND controller support for OpenOCD.
  22  *
  23  * This driver uses hardware ECC (1-bit or 4-bit) unless
  24  * the chip is accessed in "raw" mode.
  25  */
  26
  27 #ifdef HAVE_CONFIG_H
  28 #include "config.h"
  29 #endif
  30
  31 #include "nand.h"
  32
  33
  34 enum ecc {
  35         HWECC1,         /* all controllers support 1-bit ECC */
  36         HWECC4,         /* newer chips also have 4-bit ECC hardware */
  37         HWECC4_INFIX,   /* avoid this layout, except maybe for boot code */
  38 };
  39
  40 struct davinci_nand {
  41         target_t        *target;
  42
  43         u8              chipsel;        /* chipselect 0..3 == CS2..CS5 */
  44         u8              eccmode;
  45
  46         /* Async EMIF controller base */
  47         u32             aemif;
  48
  49         /* NAND chip addresses */
  50         u32             data;           /* without CLE or ALE */
  51         u32             cmd;            /* with CLE */
  52         u32             addr;           /* with ALE */
  53
  54         /* page i/o for the relevant flavor of hardware ECC */
  55         int (*read_page)(struct nand_device_s *nand, u32 page,
  56                         u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  57         int (*write_page)(struct nand_device_s *nand, u32 page,
  58                         u8 *data, u32 data_size, u8 *oob, u32 oob_size);
  59 };
  60
  61 #define NANDFCR         0x60            /* flash control register */
  62 #define NANDFSR         0x64            /* flash status register */
  63 #define NANDFECC        0x70            /* 1-bit ECC data, CS0, 1st of 4 */
  64 #define NAND4BITECCLOAD 0xbc            /* 4-bit ECC, load saved values */
  65 #define NAND4BITECC     0xc0            /* 4-bit ECC data, 1st of 4 */
  66 #define NANDERRADDR     0xd0            /* 4-bit ECC err addr, 1st of 2 */
  67 #define NANDERRVAL      0xd8            /* 4-bit ECC err value, 1st of 2 */
  68
  69 static int halted(target_t *target, const char *label)
  70 {
  71         if (target->state == TARGET_HALTED)
  72                 return true;
  73
  74         LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
  75         return false;
  76 }
  77
  78 static int davinci_register_commands(struct command_context_s *cmd_ctx)
  79 {
  80         return ERROR_OK;
  81 }
  82
  83 static int davinci_init(struct nand_device_s *nand)
  84 {
  85         struct davinci_nand *info = nand->controller_priv;
  86         target_t *target = info->target;
  87         u32 nandfcr;
  88
  89         if (!halted(target, "init"))
  90                 return ERROR_NAND_OPERATION_FAILED;
  91
  92         /* We require something else to have configured AEMIF to talk
  93          * to NAND chip in this range (including timings and width).
  94          */
  95         target_read_u32(target, info->aemif + NANDFCR, &nandfcr);
  96         if (!(nandfcr & (1 << info->chipsel))) {
  97                 LOG_ERROR("chip address %08x not NAND-enabled?", info->data);
  98                 return ERROR_NAND_OPERATION_FAILED;
  99         }
 100
 101         /* REVISIT verify:  AxCR must be in 8-bit mode, since that's all we
 102          * tested.  16 bit support should work too; but not with 4-bit ECC.
 103          */
 104
 105         return ERROR_OK;
 106 }
 107
 108 static int davinci_reset(struct nand_device_s *nand)
 109 {
 110         return ERROR_OK;
 111 }
 112
 113 static int davinci_nand_ready(struct nand_device_s *nand, int timeout)
 114 {
 115         struct davinci_nand *info = nand->controller_priv;
 116         target_t *target = info->target;
 117         u32 nandfsr;
 118
 119         /* NOTE: return code is zero/error, else success; not ERROR_* */
 120
 121         if (!halted(target, "ready"))
 122                 return 0;
 123
 124         do {
 125                 target_read_u32(target, info->aemif + NANDFSR, &nandfsr);
 126
 127                 if (nandfsr & 0x01)
 128                         return 1;
 129
 130                 alive_sleep(1);
 131         } while (timeout-- > 0);
 132
 133         return 0;
 134 }
 135
 136 static int davinci_command(struct nand_device_s *nand, u8 command)
 137 {
 138         struct davinci_nand *info = nand->controller_priv;
 139         target_t *target = info->target;
 140
 141         if (!halted(target, "command"))
 142                 return ERROR_NAND_OPERATION_FAILED;
 143
 144         target_write_u8(target, info->cmd, command);
 145         return ERROR_OK;
 146 }
 147
 148 static int davinci_address(struct nand_device_s *nand, u8 address)
 149 {
 150         struct davinci_nand *info = nand->controller_priv;
 151         target_t *target = info->target;
 152
 153         if (!halted(target, "address"))
 154                 return ERROR_NAND_OPERATION_FAILED;
 155
 156         target_write_u8(target, info->addr, address);
 157         return ERROR_OK;
 158 }
 159
 160 static int davinci_write_data(struct nand_device_s *nand, u16 data)
 161 {
 162         struct davinci_nand *info = nand->controller_priv;
 163         target_t *target = info->target;
 164
 165         if (!halted(target, "write_data"))
 166                 return ERROR_NAND_OPERATION_FAILED;
 167
 168         target_write_u8(target, info->data, data);
 169         return ERROR_OK;
 170 }
 171
 172 static int davinci_read_data(struct nand_device_s *nand, void *data)
 173 {
 174         struct davinci_nand *info = nand->controller_priv;
 175         target_t *target = info->target;
 176
 177         if (!halted(target, "read_data"))
 178                 return ERROR_NAND_OPERATION_FAILED;
 179
 180         target_read_u8(target, info->data, data);
 181         return ERROR_OK;
 182 }
 183
 184 /* REVISIT a bit of native code should let block I/O be MUCH faster */
 185
 186 static int davinci_read_block_data(struct nand_device_s *nand,
 187                 u8 *data, int data_size)
 188 {
 189         struct davinci_nand *info = nand->controller_priv;
 190         target_t *target = info->target;
 191         u32 nfdata = info->data;
 192         u32 tmp;
 193
 194         if (!halted(target, "read_block"))
 195                 return ERROR_NAND_OPERATION_FAILED;
 196
 197         while (data_size >= 4) {
 198                 target_read_u32(target, nfdata, &tmp);
 199
 200                 data[0] = tmp;
 201                 data[1] = tmp >> 8;
 202                 data[2] = tmp >> 16;
 203                 data[3] = tmp >> 24;
 204
 205                 data_size -= 4;
 206                 data += 4;
 207         }
 208
 209         while (data_size > 0) {
 210                 target_read_u8(target, nfdata, data);
 211
 212                 data_size -= 1;
 213                 data += 1;
 214         }
 215
 216         return ERROR_OK;
 217 }
 218
 219 static int davinci_write_block_data(struct nand_device_s *nand,
 220                 u8 *data, int data_size)
 221 {
 222         struct davinci_nand *info = nand->controller_priv;
 223         target_t *target = info->target;
 224         u32 nfdata = info->data;
 225         u32 tmp;
 226
 227         if (!halted(target, "write_block"))
 228                 return ERROR_NAND_OPERATION_FAILED;
 229
 230         while (data_size >= 4) {
 231                 tmp = le_to_h_u32(data);
 232                 target_write_u32(target, nfdata, tmp);
 233
 234                 data_size -= 4;
 235                 data += 4;
 236         }
 237
 238         while (data_size > 0) {
 239                 target_write_u8(target, nfdata, *data);
 240
 241                 data_size -= 1;
 242                 data += 1;
 243         }
 244
 245         return ERROR_OK;
 246 }
 247
 248 static int davinci_write_page(struct nand_device_s *nand, u32 page,
 249                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 250 {
 251         struct davinci_nand *info = nand->controller_priv;
 252         u8 *ooballoc = NULL;
 253         int status;
 254
 255         if (!nand->device)
 256                 return ERROR_NAND_DEVICE_NOT_PROBED;
 257         if (!halted(info->target, "write_page"))
 258                 return ERROR_NAND_OPERATION_FAILED;
 259
 260         /* Always write both data and OOB ... we are not "raw" I/O! */
 261         if (!data)
 262                 return ERROR_NAND_OPERATION_FAILED;
 263
 264         /* If we're not given OOB, write 0xff where we don't write ECC codes. */
 265         switch (nand->page_size) {
 266         case 512:
 267                 oob_size = 16;
 268                 break;
 269         case 2048:
 270                 oob_size = 64;
 271                 break;
 272         case 4096:
 273                 oob_size = 128;
 274                 break;
 275         default:
 276                 return ERROR_NAND_OPERATION_FAILED;
 277         }
 278         if (!oob) {
 279                 ooballoc = malloc(oob_size);
 280                 if (ooballoc)
 281                         return ERROR_NAND_OPERATION_FAILED;
 282                 oob = ooballoc;
 283                 memset(oob, 0x0ff, oob_size);
 284         }
 285
 286         status = info->write_page(nand, page, data, data_size, oob, oob_size);
 287         free(ooballoc);
 288         return status;
 289 }
 290
 291 static int davinci_read_page(struct nand_device_s *nand, u32 page,
 292                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 293 {
 294         struct davinci_nand *info = nand->controller_priv;
 295
 296         if (!nand->device)
 297                 return ERROR_NAND_DEVICE_NOT_PROBED;
 298         if (!halted(info->target, "read_page"))
 299                 return ERROR_NAND_OPERATION_FAILED;
 300
 301         return info->read_page(nand, page, data, data_size, oob, oob_size);
 302 }
 303
 304 static void davinci_write_pagecmd(struct nand_device_s *nand, u8 cmd, u32 page)
 305 {
 306         struct davinci_nand *info = nand->controller_priv;
 307         target_t *target = info->target;
 308         int page3 = nand->address_cycles - (nand->page_size == 512);
 309
 310         /* write command ({page,otp}x{read,program} */
 311         target_write_u8(target, info->cmd, cmd);
 312
 313         /* column address (beginning-of-page) */
 314         target_write_u8(target, info->addr, 0);
 315         if (nand->page_size > 512)
 316                 target_write_u8(target, info->addr, 0);
 317
 318         /* page address */
 319         target_write_u8(target, info->addr, page);
 320         target_write_u8(target, info->addr, page >> 8);
 321         if (page3)
 322                 target_write_u8(target, info->addr, page >> 16);
 323         if (page3 == 2)
 324                 target_write_u8(target, info->addr, page >> 24);
 325 }
 326
 327 static int davinci_writepage_tail(struct nand_device_s *nand,
 328                 u8 *oob, u32 oob_size)
 329 {
 330         struct davinci_nand *info = nand->controller_priv;
 331         target_t *target = info->target;
 332         u8 status;
 333
 334         if (oob_size)
 335                 davinci_write_block_data(nand, oob, oob_size);
 336
 337         /* non-cachemode page program */
 338         target_write_u8(target, info->cmd, NAND_CMD_PAGEPROG);
 339
 340         if (!davinci_nand_ready(nand, 100))
 341                 return ERROR_NAND_OPERATION_TIMEOUT;
 342
 343         if (nand_read_status(nand, &status) != ERROR_OK) {
 344                 LOG_ERROR("couldn't read status");
 345                 return ERROR_NAND_OPERATION_FAILED;
 346         }
 347
 348         if (status & NAND_STATUS_FAIL) {
 349                 LOG_ERROR("write operation failed, status: 0x%02x", status);
 350                 return ERROR_NAND_OPERATION_FAILED;
 351         }
 352
 353         return ERROR_OK;
 354 }
 355
 356 /*
 357  * All DaVinci family chips support 1-bit ECC on a per-chipselect basis.
 358  */
 359 static int davinci_write_page_ecc1(struct nand_device_s *nand, u32 page,
 360                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 361 {
 362         unsigned oob_offset;
 363         struct davinci_nand *info = nand->controller_priv;
 364         target_t *target = info->target;
 365         const u32 fcr_addr = info->aemif + NANDFCR;
 366         const u32 ecc1_addr = info->aemif + NANDFECC + info->chipsel;
 367         u32 fcr, ecc1;
 368
 369         /* Write contiguous ECC bytes starting at specified offset.
 370          * NOTE: Linux reserves twice as many bytes as we need; and
 371          * for 16-bit OOB, those extra bytes are discontiguous.
 372          */
 373         switch (nand->page_size) {
 374         case 512:
 375                 oob_offset = 0;
 376                 break;
 377         case 2048:
 378                 oob_offset = 40;
 379                 break;
 380         default:
 381                 oob_offset = 80;
 382                 break;
 383         }
 384
 385         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 386
 387         /* scrub any old ECC state */
 388         target_read_u32(target, ecc1_addr, &ecc1);
 389
 390         target_read_u32(target, fcr_addr, &fcr);
 391         fcr |= 1 << (8 + info->chipsel);
 392
 393         do {
 394                 /* set "start csX 1bit ecc" bit */
 395                 target_write_u32(target, fcr_addr, fcr);
 396
 397                 /* write 512 bytes */
 398                 davinci_write_block_data(nand, data, 512);
 399                 data += 512;
 400                 data_size -= 512;
 401
 402                 /* read the ecc, pack to 3 bytes, and invert so the ecc
 403                  * in an erased block is correct
 404                  */
 405                 target_read_u32(target, ecc1_addr, &ecc1);
 406                 ecc1 = (ecc1 & 0x0fff) | ((ecc1 & 0x0fff0000) >> 4);
 407                 ecc1 = ~ecc1;
 408
 409                 /* save correct ECC code into oob data */
 410                 oob[oob_offset++] = (u8)(ecc1);
 411                 oob[oob_offset++] = (u8)(ecc1 >> 8);
 412                 oob[oob_offset++] = (u8)(ecc1 >> 16);
 413
 414         } while (data_size);
 415
 416         /* write OOB into spare area */
 417         return davinci_writepage_tail(nand, oob, oob_size);
 418 }
 419
 420 /*
 421  * Preferred "new style" ECC layout for use with 4-bit ECC.  This somewhat
 422  * slows down large page reads done with error correction (since the OOB
 423  * is read first, so its ECC data can be used incrementally), but the
 424  * manufacturer bad block markers are safe.  Contrast:  old "infix" style.
 425  */
 426 static int davinci_write_page_ecc4(struct nand_device_s *nand, u32 page,
 427                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 428 {
 429         static const u8 ecc512[] = {
 430                 0, 1, 2, 3, 4, /* 5== mfr badblock */
 431                 6, 7, /* 8..12 for BBT or JFFS2 */ 13, 14, 15,
 432         };
 433         static const u8 ecc2048[] = {
 434                 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
 435                 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
 436                 44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
 437                 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
 438         };
 439         static const u8 ecc4096[] = {
 440                  48,  49,  50,  51,  52,  53,  54,  55,  56,  57,
 441                  58,  59,  60,  61,  62,  63,  64,  65,  66,  67,
 442                  68,  69,  70,  71,  72,  73,  74,  75,  76,  77,
 443                  78,  79,  80,  81,  82,  83,  84,  85,  86,  87,
 444                  88,  89,  90,  91,  92,  93,  94,  95,  96,  97,
 445                  98,  99, 100, 101, 102, 103, 104, 105, 106, 107,
 446                 108, 109, 110, 111, 112, 113, 114, 115, 116, 117,
 447                 118, 119, 120, 121, 122, 123, 124, 125, 126, 127,
 448         };
 449
 450         struct davinci_nand *info = nand->controller_priv;
 451         const u8 *l;
 452         target_t *target = info->target;
 453         const u32 fcr_addr = info->aemif + NANDFCR;
 454         const u32 ecc4_addr = info->aemif + NAND4BITECC;
 455         u32 fcr, ecc4;
 456
 457         /* Use the same ECC layout Linux uses.  For small page chips
 458          * it's a bit cramped.
 459          *
 460          * NOTE:  at this writing, 4KB pages have issues in Linux
 461          * because they need more than 64 bytes of ECC data, which
 462          * the standard ECC logic can't handle.
 463          */
 464         switch (nand->page_size) {
 465         case 512:
 466                 l = ecc512;
 467                 break;
 468         case 2048:
 469                 l = ecc2048;
 470                 break;
 471         default:
 472                 l = ecc4096;
 473                 break;
 474         }
 475
 476         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 477
 478         /* scrub any old ECC state */
 479         target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
 480
 481         target_read_u32(target, fcr_addr, &fcr);
 482         fcr &= ~(0x03 << 4);
 483         fcr |= (1 << 12) | (info->chipsel << 4);
 484
 485         do {
 486                 u32 raw_ecc[4], *p;
 487                 int i;
 488
 489                 /* start 4bit ecc on csX */
 490                 target_write_u32(target, fcr_addr, fcr);
 491
 492                 /* write 512 bytes */
 493                 davinci_write_block_data(nand, data, 512);
 494                 data += 512;
 495                 data_size -= 512;
 496
 497                 /* read the ecc, then save it into 10 bytes in the oob */
 498                 for (i = 0; i < 4; i++) {
 499                         target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
 500                         raw_ecc[i] &= 0x03ff03ff;
 501                 }
 502                 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
 503                         oob[*l++] =   p[0]        & 0xff;
 504                         oob[*l++] = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 505                         oob[*l++] = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 506                         oob[*l++] = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 507                         oob[*l++] =  (p[1] >> 18) & 0xff;
 508                 }
 509
 510         } while (data_size);
 511
 512         /* write OOB into spare area */
 513         return davinci_writepage_tail(nand, oob, oob_size);
 514 }
 515
 516 /*
 517  * "Infix" OOB ... like Linux ECC_HW_SYNDROME.  Avoided because it trashes
 518  * manufacturer bad block markers, except on small page chips.  Once you
 519  * write to a page using this scheme, you need specialized code to update
 520  * it (code which ignores now-invalid bad block markers).
 521  *
 522  * This is needed *only* to support older firmware.  Older ROM Boot Loaders
 523  * need it to read their second stage loader (UBL) into SRAM, but from then
 524  * on the whole system can use the cleaner non-infix layouts.  Systems with
 525  * older second stage loaders (ABL/U-Boot, etc) or other system software
 526  * (MVL 4.x/5.x kernels, filesystems, etc) may need it more generally.
 527  */
 528 static int davinci_write_page_ecc4infix(struct nand_device_s *nand, u32 page,
 529                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 530 {
 531         struct davinci_nand *info = nand->controller_priv;
 532         target_t *target = info->target;
 533         const u32 fcr_addr = info->aemif + NANDFCR;
 534         const u32 ecc4_addr = info->aemif + NAND4BITECC;
 535         u32 fcr, ecc4;
 536
 537         davinci_write_pagecmd(nand, NAND_CMD_SEQIN, page);
 538
 539         /* scrub any old ECC state */
 540         target_read_u32(target, info->aemif + NANDERRVAL, &ecc4);
 541
 542         target_read_u32(target, fcr_addr, &fcr);
 543         fcr &= ~(0x03 << 4);
 544         fcr |= (1 << 12) | (info->chipsel << 4);
 545
 546         do {
 547                 u32 raw_ecc[4], *p;
 548                 u8 *l;
 549                 int i;
 550
 551                 /* start 4bit ecc on csX */
 552                 target_write_u32(target, fcr_addr, fcr);
 553
 554                 /* write 512 bytes */
 555                 davinci_write_block_data(nand, data, 512);
 556                 data += 512;
 557                 data_size -= 512;
 558
 559                 /* read the ecc */
 560                 for (i = 0; i < 4; i++) {
 561                         target_read_u32(target, ecc4_addr + 4 * i, &raw_ecc[i]);
 562                         raw_ecc[i] &= 0x03ff03ff;
 563                 }
 564
 565                 /* skip 6 bytes of prepad, then pack 10 packed ecc bytes */
 566                 for (i = 0, l = oob + 6, p = raw_ecc; i < 2; i++, p += 2) {
 567                         *l++ =   p[0]        & 0xff;
 568                         *l++ = ((p[0] >>  8) & 0x03) | ((p[0] >> 14) & 0xfc);
 569                         *l++ = ((p[0] >> 22) & 0x0f) | ((p[1] <<  4) & 0xf0);
 570                         *l++ = ((p[1] >>  4) & 0x3f) | ((p[1] >> 10) & 0xc0);
 571                         *l++ =  (p[1] >> 18) & 0xff;
 572                 }
 573
 574                 /* write this "out-of-band" data -- infix */
 575                 davinci_write_block_data(nand, oob, 16);
 576                 oob += 16;
 577                 oob_size -= 16;
 578
 579         } while (data_size);
 580
 581         /* the last data and OOB writes included the spare area */
 582         return davinci_writepage_tail(nand, NULL, 0);
 583 }
 584
 585 static int davinci_read_page_ecc4infix(struct nand_device_s *nand, u32 page,
 586                 u8 *data, u32 data_size, u8 *oob, u32 oob_size)
 587 {
 588         davinci_write_pagecmd(nand, NAND_CMD_READ0, page);
 589
 590         /* large page devices need a start command */
 591         if (nand->page_size > 512)
 592                 davinci_command(nand, NAND_CMD_READSTART);
 593
 594         if (!davinci_nand_ready(nand, 100))
 595                 return ERROR_NAND_OPERATION_TIMEOUT;
 596
 597         /* NOTE:  not bothering to compute and use ECC data for now */
 598
 599         do {
 600                 /* write 512 bytes */
 601                 davinci_read_block_data(nand, data, 512);
 602                 data += 512;
 603                 data_size -= 512;
 604
 605                 /* read this "out-of-band" data -- infix */
 606                 davinci_read_block_data(nand, oob, 16);
 607                 oob += 16;
 608                 oob_size -= 16;
 609         } while (data_size);
 610
 611         return ERROR_OK;
 612 }
 613
 614 static int davinci_nand_device_command(struct command_context_s *cmd_ctx,
 615                 char *cmd, char **argv, int argc,
 616                 struct nand_device_s *nand)
 617 {
 618         struct davinci_nand *info;
 619         target_t *target;
 620         unsigned long chip, aemif;
 621         enum ecc eccmode;
 622         int chipsel;
 623         char *ep;
 624
 625         /* arguments:
 626          *  - "davinci"
 627          *  - target
 628          *  - nand chip address
 629          *  - ecc mode
 630          *  - aemif address
 631          * Plus someday, optionally, ALE and CLE masks.
 632          */
 633         if (argc < 5) {
 634                 LOG_ERROR("parameters: %s target "
 635                                 "chip_addr hwecc_mode aemif_addr",
 636                                 argv[0]);
 637                 goto fail;
 638         }
 639
 640         target = get_target(argv[1]);
 641         if (!target) {
 642                 LOG_ERROR("invalid target %s", argv[1]);
 643                 goto fail;
 644         }
 645
 646         chip = strtoul(argv[2], &ep, 0);
 647         if (*ep || chip == 0 || chip == ULONG_MAX) {
 648                 LOG_ERROR("Invalid NAND chip address %s", argv[2]);
 649                 goto fail;
 650         }
 651
 652         if (strcmp(argv[3], "hwecc1") == 0)
 653                 eccmode = HWECC1;
 654         else if (strcmp(argv[3], "hwecc4") == 0)
 655                 eccmode = HWECC4;
 656         else if (strcmp(argv[3], "hwecc4_infix") == 0)
 657                 eccmode = HWECC4_INFIX;
 658         else {
 659                 LOG_ERROR("Invalid ecc mode %s", argv[3]);
 660                 goto fail;
 661         }
 662
 663         aemif = strtoul(argv[4], &ep, 0);
 664         if (*ep || chip == 0 || chip == ULONG_MAX) {
 665                 LOG_ERROR("Invalid AEMIF controller address %s", argv[4]);
 666                 goto fail;
 667         }
 668
 669         /* REVISIT what we'd *like* to do is look up valid ranges using
 670          * target-specific declarations, and not even need to pass the
 671          * AEMIF controller address.
 672          */
 673         if (aemif == 0x01e00000                 /* dm6446, dm357 */
 674                         || aemif == 0x01e10000  /* dm335, dm355 */
 675                         || aemif == 0x01d10000  /* dm365 */
 676                         ) {
 677                 if (chip < 0x0200000 || chip >= 0x0a000000) {
 678                         LOG_ERROR("NAND address %08lx out of range?", chip);
 679                         goto fail;
 680                 }
 681                 chipsel = (chip - 0x02000000) >> 21;
 682         } else {
 683                 LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
 684                 goto fail;
 685         }
 686
 687         info = calloc(1, sizeof *info);
 688         if (info == NULL)
 689                 goto fail;
 690
 691         info->target = target;
 692         info->eccmode = eccmode;
 693         info->chipsel = chipsel;
 694         info->aemif = aemif;
 695         info->data = chip;
 696         info->cmd = chip | 0x10;
 697         info->addr = chip | 0x08;
 698
 699         nand->controller_priv = info;
 700
 701         /* NOTE:  for now we don't do any error correction on read.
 702          * Nothing else in OpenOCD currently corrects read errors,
 703          * and in any case it's *writing* that we care most about.
 704          */
 705         info->read_page = nand_read_page_raw;
 706
 707         switch (eccmode) {
 708         case HWECC1:
 709                 /* ECC_HW, 1-bit corrections, 3 bytes ECC per 512 data bytes */
 710                 info->write_page = davinci_write_page_ecc1;
 711                 break;
 712         case HWECC4:
 713                 /* ECC_HW, 4-bit corrections, 10 bytes ECC per 512 data bytes */
 714                 info->write_page = davinci_write_page_ecc4;
 715                 break;
 716         case HWECC4_INFIX:
 717                 /* Same 4-bit ECC HW, with problematic page/ecc layout */
 718                 info->read_page = davinci_read_page_ecc4infix;
 719                 info->write_page = davinci_write_page_ecc4infix;
 720                 break;
 721         }
 722
 723         return ERROR_OK;
 724
 725 fail:
 726         return ERROR_NAND_OPERATION_FAILED;
 727 }
 728
 729 nand_flash_controller_t davinci_nand_controller = {
 730         .name                   = "davinci",
 731         .nand_device_command    = davinci_nand_device_command,
 732         .register_commands      = davinci_register_commands,
 733         .init                   = davinci_init,
 734         .reset                  = davinci_reset,
 735         .command                = davinci_command,
 736         .address                = davinci_address,
 737         .write_data             = davinci_write_data,
 738         .read_data              = davinci_read_data,
 739         .write_page             = davinci_write_page,
 740         .read_page              = davinci_read_page,
 741         .write_block_data       = davinci_write_block_data,
 742         .read_block_data        = davinci_read_block_data,
 743         .nand_ready             = davinci_nand_ready,
 744 };