1 /***************************************************************************
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2 * Copyright (C) 2007-2008 by unsik Kim <donari75@gmail.com> *
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4 * This program is free software; you can redistribute it and/or modify *
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5 * it under the terms of the GNU General Public License as published by *
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6 * the Free Software Foundation; either version 2 of the License, or *
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7 * (at your option) any later version. *
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9 * This program is distributed in the hope that it will be useful, *
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10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
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11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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12 * GNU General Public License for more details. *
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14 * You should have received a copy of the GNU General Public License *
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15 * along with this program; if not, write to the *
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16 * Free Software Foundation, Inc., *
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17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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18 ***************************************************************************/
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23 typedef unsigned long mg_io_uint32;
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24 typedef unsigned short mg_io_uint16;
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25 typedef unsigned char mg_io_uint8;
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27 typedef struct mflash_gpio_num_s
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31 } mflash_gpio_num_t;
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33 typedef struct mflash_gpio_drv_s
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36 int (*set_gpio_to_output) (mflash_gpio_num_t gpio);
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37 int (*set_gpio_output_val) (mflash_gpio_num_t gpio, u8 val);
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38 } mflash_gpio_drv_t;
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40 typedef struct _mg_io_type_drv_info {
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42 mg_io_uint16 general_configuration; // 00
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43 mg_io_uint16 number_of_cylinders; // 01
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44 mg_io_uint16 reserved1; // 02
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45 mg_io_uint16 number_of_heads; // 03
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46 mg_io_uint16 unformatted_bytes_per_track; // 04
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47 mg_io_uint16 unformatted_bytes_per_sector; // 05
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48 mg_io_uint16 sectors_per_track; // 06
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49 mg_io_uint8 vendor_unique1[6]; // 07/08/09
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51 mg_io_uint8 serial_number[20]; // 10~19
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53 mg_io_uint16 buffer_type; // 20
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54 mg_io_uint16 buffer_sector_size; // 21
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55 mg_io_uint16 number_of_ecc_bytes; // 22
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57 mg_io_uint8 firmware_revision[8]; // 23~26
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58 mg_io_uint8 model_number[40]; // 27
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60 mg_io_uint8 maximum_block_transfer; // 47 low byte
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61 mg_io_uint8 vendor_unique2; // 47 high byte
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62 mg_io_uint16 dword_io; // 48
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64 mg_io_uint16 capabilities; // 49
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65 mg_io_uint16 reserved2; // 50
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67 mg_io_uint8 vendor_unique3; // 51 low byte
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68 mg_io_uint8 pio_cycle_timing_mode; // 51 high byte
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69 mg_io_uint8 vendor_unique4; // 52 low byte
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70 mg_io_uint8 dma_cycle_timing_mode; // 52 high byte
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71 mg_io_uint16 translation_fields_valid; // 53 (low bit)
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72 mg_io_uint16 number_of_current_cylinders; // 54
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73 mg_io_uint16 number_of_current_heads; // 55
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74 mg_io_uint16 current_sectors_per_track; // 56
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75 mg_io_uint16 current_sector_capacity_lo; // 57 & 58
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76 mg_io_uint16 current_sector_capacity_hi; // 57 & 58
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77 mg_io_uint8 multi_sector_count; // 59 low
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78 mg_io_uint8 multi_sector_setting_valid; // 59 high (low bit)
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80 mg_io_uint16 total_user_addressable_sectors_lo; // 60 & 61
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81 mg_io_uint16 total_user_addressable_sectors_hi; // 60 & 61
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83 mg_io_uint8 single_dma_modes_supported; // 62 low byte
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84 mg_io_uint8 single_dma_transfer_active; // 62 high byte
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85 mg_io_uint8 multi_dma_modes_supported; // 63 low byte
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86 mg_io_uint8 multi_dma_transfer_active; // 63 high byte
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87 mg_io_uint16 adv_pio_mode;
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88 mg_io_uint16 min_dma_cyc;
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89 mg_io_uint16 recommend_dma_cyc;
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90 mg_io_uint16 min_pio_cyc_no_iordy;
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91 mg_io_uint16 min_pio_cyc_with_iordy;
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92 mg_io_uint8 reserved3[22];
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93 mg_io_uint16 major_ver_num;
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94 mg_io_uint16 minor_ver_num;
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95 mg_io_uint16 feature_cmd_set_suprt0;
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96 mg_io_uint16 feature_cmd_set_suprt1;
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97 mg_io_uint16 feature_cmd_set_suprt2;
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98 mg_io_uint16 feature_cmd_set_en0;
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99 mg_io_uint16 feature_cmd_set_en1;
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100 mg_io_uint16 feature_cmd_set_en2;
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101 mg_io_uint16 reserved4;
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102 mg_io_uint16 req_time_for_security_er_done;
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103 mg_io_uint16 req_time_for_enhan_security_er_done;
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104 mg_io_uint16 adv_pwr_mgm_lvl_val;
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105 mg_io_uint16 reserved5;
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106 mg_io_uint16 re_of_hw_rst;
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107 mg_io_uint8 reserved6[68];
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108 mg_io_uint16 security_stas;
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109 mg_io_uint8 vendor_uniq_bytes[62];
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110 mg_io_uint16 cfa_pwr_mode;
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111 mg_io_uint8 reserved7[186];
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113 mg_io_uint16 scts_per_secure_data_unit;
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114 mg_io_uint16 integrity_word;
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116 } mg_io_type_drv_info;
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118 typedef struct mg_drv_info_s {
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119 mg_io_type_drv_info drv_id;
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123 typedef struct mflash_bank_s
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129 mflash_gpio_num_t rst_pin;
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130 mflash_gpio_num_t wp_pin;
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131 mflash_gpio_num_t dpd_pin;
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133 mflash_gpio_drv_t *gpio_drv;
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135 mg_drv_info_t *drv_info;
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140 extern int mflash_register_commands(struct command_context_s *cmd_ctx);
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141 extern int mflash_init_drivers(struct command_context_s *cmd_ctx);
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143 #define MG_MFLASH_SECTOR_SIZE (0x200) //512Bytes = 2^9
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144 #define MG_MFLASH_SECTOR_SIZE_MASK (0x200-1)
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145 #define MG_MFLASH_SECTOR_SIZE_SHIFT (9)
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147 #define MG_BUFFER_OFFSET 0x8000
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148 #define MG_REG_OFFSET 0xC000
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149 #define MG_REG_FEATURE 0x2 // write case
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150 #define MG_REG_ERROR 0x2 // read case
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151 #define MG_REG_SECT_CNT 0x4
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152 #define MG_REG_SECT_NUM 0x6
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153 #define MG_REG_CYL_LOW 0x8
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154 #define MG_REG_CYL_HIGH 0xA
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155 #define MG_REG_DRV_HEAD 0xC
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156 #define MG_REG_COMMAND 0xE // write case
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157 #define MG_REG_STATUS 0xE // read case
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158 #define MG_REG_DRV_CTRL 0x10
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159 #define MG_REG_BURST_CTRL 0x12
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161 #define MG_OEM_DISK_WAIT_TIME_LONG 15000 // msec
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162 #define MG_OEM_DISK_WAIT_TIME_NORMAL 3000 // msec
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163 #define MG_OEM_DISK_WAIT_TIME_SHORT 1000 // msec
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165 typedef enum _mg_io_type_wait{
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167 mg_io_wait_bsy = 1,
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168 mg_io_wait_not_bsy = 2,
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169 mg_io_wait_rdy = 3,
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170 mg_io_wait_drq = 4, // wait for data request
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171 mg_io_wait_drq_noerr = 5, // wait for DRQ but ignore the error status bit
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172 mg_io_wait_rdy_noerr = 6 // wait for ready, but ignore error status bit
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176 //= "Status Register" bit masks.
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177 typedef enum _mg_io_type_rbit_status{
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179 mg_io_rbit_status_error = 0x01, // error bit in status register
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180 mg_io_rbit_status_corrected_error = 0x04, // corrected error in status register
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181 mg_io_rbit_status_data_req = 0x08, // data request bit in status register
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182 mg_io_rbit_status_seek_done = 0x10, // DSC - Drive Seek Complete
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183 mg_io_rbit_status_write_fault = 0x20, // DWF - Drive Write Fault
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184 mg_io_rbit_status_ready = 0x40,
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185 mg_io_rbit_status_busy = 0x80
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187 } mg_io_type_rbit_status;
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189 //= "Error Register" bit masks.
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190 typedef enum _mg_io_type_rbit_error{
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192 mg_io_rbit_err_general = 0x01,
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193 mg_io_rbit_err_aborted = 0x04,
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194 mg_io_rbit_err_bad_sect_num = 0x10,
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195 mg_io_rbit_err_uncorrectable = 0x40,
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196 mg_io_rbit_err_bad_block = 0x80
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198 } mg_io_type_rbit_error;
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200 //= "Device Control Register" bit.
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201 typedef enum _mg_io_type_rbit_devc{
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203 mg_io_rbit_devc_intr = 0x02,// interrupt enable bit (1:disable, 0:enable)
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204 mg_io_rbit_devc_srst = 0x04 // softwrae reset bit (1:assert, 0:de-assert)
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206 } mg_io_type_rbit_devc;
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208 // "Drive Select/Head Register" values.
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209 typedef enum _mg_io_type_rval_dev{
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211 mg_io_rval_dev_must_be_on = 0x80, // These 1 bits are always on
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212 mg_io_rval_dev_drv_master = (0x00 | mg_io_rval_dev_must_be_on),// Master
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213 mg_io_rval_dev_drv_slave0 = (0x10 | mg_io_rval_dev_must_be_on),// Slave0
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214 mg_io_rval_dev_drv_slave1 = (0x20 | mg_io_rval_dev_must_be_on),// Slave1
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215 mg_io_rval_dev_drv_slave2 = (0x30 | mg_io_rval_dev_must_be_on),// Slave2
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216 mg_io_rval_dev_lba_mode = (0x40 | mg_io_rval_dev_must_be_on)
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218 } mg_io_type_rval_dev;
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220 typedef enum _mg_io_type_cmd
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222 mg_io_cmd_read =0x20,
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223 mg_io_cmd_write =0x30,
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225 mg_io_cmd_setmul =0xC6,
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226 mg_io_cmd_readmul =0xC4,
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227 mg_io_cmd_writemul =0xC5,
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229 mg_io_cmd_idle =0x97,//0xE3
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230 mg_io_cmd_idle_immediate =0x95,//0xE1
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232 mg_io_cmd_setsleep =0x99,//0xE6
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233 mg_io_cmd_stdby =0x96,//0xE2
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234 mg_io_cmd_stdby_immediate =0x94,//0xE0
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236 mg_io_cmd_identify =0xEC,
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237 mg_io_cmd_set_feature =0xEF,
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239 mg_io_cmd_confirm_write =0x3C,
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240 mg_io_cmd_confirm_read =0x40,
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241 mg_io_cmd_wakeup =0xC3
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