1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2011 Bjarne Steinsbo <bsteinsbo@gmail.com> *
6 * Copyright (C) 2010 richard vegh <vegh.ricsi@gmail.com> *
7 * Copyright (C) 2010 Oyvind Harboe <oyvind.harboe@zylin.com> *
9 * Based on a combination of the lpc3180 driver and code from *
10 * uboot-2009.03-lpc32xx by Kevin Wells. *
11 * Any bugs are mine. --BSt *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
27 ***************************************************************************/
34 #include <target/target.h>
36 static int lpc32xx_reset(struct nand_device *nand);
37 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout);
38 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout);
39 extern int nand_correct_data(struct nand_device *nand, u_char *dat,
40 u_char *read_ecc, u_char *calc_ecc);
42 /* These are offset with the working area in IRAM when using DMA to
43 * read/write data to the SLC controller.
44 * - DMA descriptors will be put at start of working area,
45 * - Hardware generated ECC will be stored at ECC_OFFS
46 * - OOB wil be read/written from/to SPARE_OFFS
47 * - Actual page data will be read from/to DATA_OFFS
48 * There are unused holes between the used areas.
50 #define ECC_OFFS 0x120
51 #define SPARE_OFFS 0x140
52 #define DATA_OFFS 0x200
54 static int sp_ooblayout[] = {
55 10, 11, 12, 13, 14, 15
57 static int lp_ooblayout[] = {
58 40, 41, 42, 43, 44, 45,
59 46, 47, 48, 49, 50, 51,
60 52, 53, 54, 55, 56, 57,
61 58, 59, 60, 61, 62, 63
65 volatile uint32_t dma_src;
66 volatile uint32_t dma_dest;
67 volatile uint32_t next_lli;
68 volatile uint32_t next_ctrl;
71 static dmac_ll_t dmalist[(2048/256) * 2 + 1];
73 /* nand device lpc32xx <target#> <oscillator_frequency>
75 NAND_DEVICE_COMMAND_HANDLER(lpc32xx_nand_device_command)
78 return ERROR_COMMAND_SYNTAX_ERROR;
82 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], osc_freq);
84 struct lpc32xx_nand_controller *lpc32xx_info;
85 lpc32xx_info = malloc(sizeof(struct lpc32xx_nand_controller));
86 nand->controller_priv = lpc32xx_info;
88 lpc32xx_info->osc_freq = osc_freq;
90 if ((lpc32xx_info->osc_freq < 1000) || (lpc32xx_info->osc_freq > 20000))
91 LOG_WARNING("LPC32xx oscillator frequency should be between "
92 "1000 and 20000 kHz, was %i",
93 lpc32xx_info->osc_freq);
95 lpc32xx_info->selected_controller = LPC32xx_NO_CONTROLLER;
96 lpc32xx_info->sw_write_protection = 0;
97 lpc32xx_info->sw_wp_lower_bound = 0x0;
98 lpc32xx_info->sw_wp_upper_bound = 0x0;
103 static int lpc32xx_pll(int fclkin, uint32_t pll_ctrl)
105 int bypass = (pll_ctrl & 0x8000) >> 15;
106 int direct = (pll_ctrl & 0x4000) >> 14;
107 int feedback = (pll_ctrl & 0x2000) >> 13;
108 int p = (1 << ((pll_ctrl & 0x1800) >> 11) * 2);
109 int n = ((pll_ctrl & 0x0600) >> 9) + 1;
110 int m = ((pll_ctrl & 0x01fe) >> 1) + 1;
111 int lock = (pll_ctrl & 0x1);
114 LOG_WARNING("PLL is not locked");
116 if (!bypass && direct) /* direct mode */
117 return (m * fclkin) / n;
119 if (bypass && !direct) /* bypass mode */
120 return fclkin / (2 * p);
122 if (bypass & direct) /* direct bypass mode */
125 if (feedback) /* integer mode */
126 return m * (fclkin / n);
127 else /* non-integer mode */
128 return (m / (2 * p)) * (fclkin / n);
131 static float lpc32xx_cycle_time(struct nand_device *nand)
133 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
134 struct target *target = nand->target;
135 uint32_t sysclk_ctrl, pwr_ctrl, hclkdiv_ctrl, hclkpll_ctrl;
142 /* calculate timings */
144 /* determine current SYSCLK (13'MHz or main oscillator) */
145 retval = target_read_u32(target, 0x40004050, &sysclk_ctrl);
146 if (ERROR_OK != retval) {
147 LOG_ERROR("could not read SYSCLK_CTRL");
148 return ERROR_NAND_OPERATION_FAILED;
151 if ((sysclk_ctrl & 1) == 0)
152 sysclk = lpc32xx_info->osc_freq;
156 /* determine selected HCLK source */
157 retval = target_read_u32(target, 0x40004044, &pwr_ctrl);
158 if (ERROR_OK != retval) {
159 LOG_ERROR("could not read HCLK_CTRL");
160 return ERROR_NAND_OPERATION_FAILED;
163 if ((pwr_ctrl & (1 << 2)) == 0) { /* DIRECT RUN mode */
166 retval = target_read_u32(target, 0x40004058, &hclkpll_ctrl);
167 if (ERROR_OK != retval) {
168 LOG_ERROR("could not read HCLKPLL_CTRL");
169 return ERROR_NAND_OPERATION_FAILED;
171 hclk_pll = lpc32xx_pll(sysclk, hclkpll_ctrl);
173 retval = target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
174 if (ERROR_OK != retval) {
175 LOG_ERROR("could not read CLKDIV_CTRL");
176 return ERROR_NAND_OPERATION_FAILED;
179 if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
180 hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
181 else /* HCLK uses HCLK_PLL */
182 hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
185 LOG_DEBUG("LPC32xx HCLK currently clocked at %i kHz", hclk);
187 cycle = (1.0 / hclk) * 1000000.0;
192 static int lpc32xx_init(struct nand_device *nand)
194 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
195 struct target *target = nand->target;
196 int bus_width = nand->bus_width ? : 8;
197 int address_cycles = nand->address_cycles ? : 3;
198 int page_size = nand->page_size ? : 512;
201 if (target->state != TARGET_HALTED) {
202 LOG_ERROR("target must be halted to use LPC32xx "
203 "NAND flash controller");
204 return ERROR_NAND_OPERATION_FAILED;
207 /* sanitize arguments */
208 if (bus_width != 8) {
209 LOG_ERROR("LPC32xx doesn't support %i", bus_width);
210 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
213 /* inform calling code about selected bus width */
214 nand->bus_width = bus_width;
216 if ((address_cycles < 3) || (address_cycles > 5)) {
217 LOG_ERROR("LPC32xx driver doesn't support %i address cycles", address_cycles);
218 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
221 if ((page_size != 512) && (page_size != 2048)) {
222 LOG_ERROR("LPC32xx doesn't support page size %i", page_size);
223 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
226 /* select MLC controller if none is currently selected */
227 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
228 LOG_DEBUG("no LPC32xx NAND flash controller selected, "
229 "using default 'slc'");
230 lpc32xx_info->selected_controller = LPC32xx_SLC_CONTROLLER;
233 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
234 uint32_t mlc_icr_value = 0x0;
236 int twp, twh, trp, treh, trhz, trbwb, tcea;
238 /* FLASHCLK_CTRL = 0x22 (enable clk for MLC) */
239 retval = target_write_u32(target, 0x400040c8, 0x22);
240 if (ERROR_OK != retval) {
241 LOG_ERROR("could not set FLASHCLK_CTRL");
242 return ERROR_NAND_OPERATION_FAILED;
245 /* MLC_CEH = 0x0 (Force nCE assert) */
246 retval = target_write_u32(target, 0x200b804c, 0x0);
247 if (ERROR_OK != retval) {
248 LOG_ERROR("could not set MLC_CEH");
249 return ERROR_NAND_OPERATION_FAILED;
252 /* MLC_LOCK = 0xa25e (unlock protected registers) */
253 retval = target_write_u32(target, 0x200b8044, 0xa25e);
254 if (ERROR_OK != retval) {
255 LOG_ERROR("could not set MLC_LOCK");
256 return ERROR_NAND_OPERATION_FAILED;
259 /* MLC_ICR = configuration */
260 if (lpc32xx_info->sw_write_protection)
261 mlc_icr_value |= 0x8;
262 if (page_size == 2048)
263 mlc_icr_value |= 0x4;
264 if (address_cycles == 4)
265 mlc_icr_value |= 0x2;
267 mlc_icr_value |= 0x1;
268 retval = target_write_u32(target, 0x200b8030, mlc_icr_value);
269 if (ERROR_OK != retval) {
270 LOG_ERROR("could not set MLC_ICR");
271 return ERROR_NAND_OPERATION_FAILED;
274 /* calculate NAND controller timings */
275 cycle = lpc32xx_cycle_time(nand);
277 twp = ((40 / cycle) + 1);
278 twh = ((20 / cycle) + 1);
279 trp = ((30 / cycle) + 1);
280 treh = ((15 / cycle) + 1);
281 trhz = ((30 / cycle) + 1);
282 trbwb = ((100 / cycle) + 1);
283 tcea = ((45 / cycle) + 1);
285 /* MLC_LOCK = 0xa25e (unlock protected registers) */
286 retval = target_write_u32(target, 0x200b8044, 0xa25e);
287 if (ERROR_OK != retval) {
288 LOG_ERROR("could not set MLC_LOCK");
289 return ERROR_NAND_OPERATION_FAILED;
293 retval = target_write_u32(target, 0x200b8034,
297 | ((treh & 0xf) << 12)
298 | ((trhz & 0x7) << 16)
299 | ((trbwb & 0x1f) << 19)
300 | ((tcea & 0x3) << 24));
301 if (ERROR_OK != retval) {
302 LOG_ERROR("could not set MLC_TIME_REG");
303 return ERROR_NAND_OPERATION_FAILED;
306 retval = lpc32xx_reset(nand);
307 if (ERROR_OK != retval)
308 return ERROR_NAND_OPERATION_FAILED;
309 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
311 int r_setup, r_hold, r_width, r_rdy;
312 int w_setup, w_hold, w_width, w_rdy;
314 /* FLASHCLK_CTRL = 0x05 (enable clk for SLC) */
315 retval = target_write_u32(target, 0x400040c8, 0x05);
316 if (ERROR_OK != retval) {
317 LOG_ERROR("could not set FLASHCLK_CTRL");
318 return ERROR_NAND_OPERATION_FAILED;
321 /* after reset set other registers of SLC,
322 * so reset calling is here at the begining
324 retval = lpc32xx_reset(nand);
325 if (ERROR_OK != retval)
326 return ERROR_NAND_OPERATION_FAILED;
336 retval = target_write_u32(target, 0x20020014,
337 0x3e | (bus_width == 16) ? 1 : 0);
338 if (ERROR_OK != retval) {
339 LOG_ERROR("could not set SLC_CFG");
340 return ERROR_NAND_OPERATION_FAILED;
343 /* SLC_IEN = 3 (INT_RDY_EN = 1) ,(INT_TC_STAT = 1) */
344 retval = target_write_u32(target, 0x20020020, 0x03);
345 if (ERROR_OK != retval) {
346 LOG_ERROR("could not set SLC_IEN");
347 return ERROR_NAND_OPERATION_FAILED;
350 /* DMA configuration */
352 /* DMACLK_CTRL = 0x01 (enable clock for DMA controller) */
353 retval = target_write_u32(target, 0x400040e8, 0x01);
354 if (ERROR_OK != retval) {
355 LOG_ERROR("could not set DMACLK_CTRL");
356 return ERROR_NAND_OPERATION_FAILED;
359 /* DMACConfig = DMA enabled*/
360 retval = target_write_u32(target, 0x31000030, 0x01);
361 if (ERROR_OK != retval) {
362 LOG_ERROR("could not set DMACConfig");
363 return ERROR_NAND_OPERATION_FAILED;
366 /* calculate NAND controller timings */
367 cycle = lpc32xx_cycle_time(nand);
369 r_setup = w_setup = 0;
370 r_hold = w_hold = 10 / cycle;
371 r_width = 30 / cycle;
372 w_width = 40 / cycle;
373 r_rdy = w_rdy = 100 / cycle;
375 /* SLC_TAC: SLC timing arcs register */
376 retval = target_write_u32(target, 0x2002002c,
378 | ((r_hold & 0xf) << 4)
379 | ((r_width & 0xf) << 8)
380 | ((r_rdy & 0xf) << 12)
381 | ((w_setup & 0xf) << 16)
382 | ((w_hold & 0xf) << 20)
383 | ((w_width & 0xf) << 24)
384 | ((w_rdy & 0xf) << 28));
385 if (ERROR_OK != retval) {
386 LOG_ERROR("could not set SLC_TAC");
387 return ERROR_NAND_OPERATION_FAILED;
394 static int lpc32xx_reset(struct nand_device *nand)
396 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
397 struct target *target = nand->target;
400 if (target->state != TARGET_HALTED) {
401 LOG_ERROR("target must be halted to use "
402 "LPC32xx NAND flash controller");
403 return ERROR_NAND_OPERATION_FAILED;
406 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
407 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
408 return ERROR_NAND_OPERATION_FAILED;
409 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
410 /* MLC_CMD = 0xff (reset controller and NAND device) */
411 retval = target_write_u32(target, 0x200b8000, 0xff);
412 if (ERROR_OK != retval) {
413 LOG_ERROR("could not set MLC_CMD");
414 return ERROR_NAND_OPERATION_FAILED;
417 if (!lpc32xx_controller_ready(nand, 100)) {
418 LOG_ERROR("LPC32xx MLC NAND controller timed out "
420 return ERROR_NAND_OPERATION_TIMEOUT;
422 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
423 /* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
424 retval = target_write_u32(target, 0x20020010, 0x6);
425 if (ERROR_OK != retval) {
426 LOG_ERROR("could not set SLC_CTRL");
427 return ERROR_NAND_OPERATION_FAILED;
430 if (!lpc32xx_controller_ready(nand, 100))
432 LOG_ERROR("LPC32xx SLC NAND controller timed out "
434 return ERROR_NAND_OPERATION_TIMEOUT;
441 static int lpc32xx_command(struct nand_device *nand, uint8_t command)
443 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
444 struct target *target = nand->target;
447 if (target->state != TARGET_HALTED) {
448 LOG_ERROR("target must be halted to use "
449 "LPC32xx NAND flash controller");
450 return ERROR_NAND_OPERATION_FAILED;
453 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
454 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
455 return ERROR_NAND_OPERATION_FAILED;
456 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
457 /* MLC_CMD = command */
458 retval = target_write_u32(target, 0x200b8000, command);
459 if (ERROR_OK != retval) {
460 LOG_ERROR("could not set MLC_CMD");
461 return ERROR_NAND_OPERATION_FAILED;
463 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
464 /* SLC_CMD = command */
465 retval = target_write_u32(target, 0x20020008, command);
466 if (ERROR_OK != retval) {
467 LOG_ERROR("could not set SLC_CMD");
468 return ERROR_NAND_OPERATION_FAILED;
475 static int lpc32xx_address(struct nand_device *nand, uint8_t address)
477 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
478 struct target *target = nand->target;
481 if (target->state != TARGET_HALTED) {
482 LOG_ERROR("target must be halted to use "
483 "LPC32xx NAND flash controller");
484 return ERROR_NAND_OPERATION_FAILED;
487 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
488 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
489 return ERROR_NAND_OPERATION_FAILED;
490 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
491 /* MLC_ADDR = address */
492 retval = target_write_u32(target, 0x200b8004, address);
493 if (ERROR_OK != retval) {
494 LOG_ERROR("could not set MLC_ADDR");
495 return ERROR_NAND_OPERATION_FAILED;
497 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
498 /* SLC_ADDR = address */
499 retval = target_write_u32(target, 0x20020004, address);
500 if (ERROR_OK != retval) {
501 LOG_ERROR("could not set SLC_ADDR");
502 return ERROR_NAND_OPERATION_FAILED;
509 static int lpc32xx_write_data(struct nand_device *nand, uint16_t data)
511 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
512 struct target *target = nand->target;
515 if (target->state != TARGET_HALTED) {
516 LOG_ERROR("target must be halted to use "
517 "LPC32xx NAND flash controller");
518 return ERROR_NAND_OPERATION_FAILED;
521 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
522 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
523 return ERROR_NAND_OPERATION_FAILED;
524 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
525 /* MLC_DATA = data */
526 retval = target_write_u32(target, 0x200b0000, data);
527 if (ERROR_OK != retval) {
528 LOG_ERROR("could not set MLC_DATA");
529 return ERROR_NAND_OPERATION_FAILED;
531 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
532 /* SLC_DATA = data */
533 retval = target_write_u32(target, 0x20020000, data);
534 if (ERROR_OK != retval) {
535 LOG_ERROR("could not set SLC_DATA");
536 return ERROR_NAND_OPERATION_FAILED;
543 static int lpc32xx_read_data(struct nand_device *nand, void *data)
545 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
546 struct target *target = nand->target;
549 if (target->state != TARGET_HALTED) {
550 LOG_ERROR("target must be halted to use LPC32xx "
551 "NAND flash controller");
552 return ERROR_NAND_OPERATION_FAILED;
555 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
556 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
557 return ERROR_NAND_OPERATION_FAILED;
558 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
559 /* data = MLC_DATA, use sized access */
560 if (nand->bus_width == 8) {
561 uint8_t *data8 = data;
562 retval = target_read_u8(target, 0x200b0000, data8);
564 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
565 return ERROR_NAND_OPERATION_FAILED;
567 if (ERROR_OK != retval) {
568 LOG_ERROR("could not read MLC_DATA");
569 return ERROR_NAND_OPERATION_FAILED;
571 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
574 /* data = SLC_DATA, must use 32-bit access */
575 retval = target_read_u32(target, 0x20020000, &data32);
576 if (ERROR_OK != retval) {
577 LOG_ERROR("could not read SLC_DATA");
578 return ERROR_NAND_OPERATION_FAILED;
581 if (nand->bus_width == 8) {
582 uint8_t *data8 = data;
583 *data8 = data32 & 0xff;
585 LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
586 return ERROR_NAND_OPERATION_FAILED;
593 static int lpc32xx_write_page_mlc(struct nand_device *nand, uint32_t page,
594 uint8_t *data, uint32_t data_size,
595 uint8_t *oob, uint32_t oob_size)
597 struct target *target = nand->target;
600 static uint8_t page_buffer[512];
601 static uint8_t oob_buffer[6];
602 int quarter, num_quarters;
604 /* MLC_CMD = sequential input */
605 retval = target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
606 if (ERROR_OK != retval) {
607 LOG_ERROR("could not set MLC_CMD");
608 return ERROR_NAND_OPERATION_FAILED;
611 if (nand->page_size == 512) {
612 /* MLC_ADDR = 0x0 (one column cycle) */
613 retval = target_write_u32(target, 0x200b8004, 0x0);
614 if (ERROR_OK != retval) {
615 LOG_ERROR("could not set MLC_ADDR");
616 return ERROR_NAND_OPERATION_FAILED;
620 retval = target_write_u32(target, 0x200b8004, page & 0xff);
621 if (ERROR_OK != retval) {
622 LOG_ERROR("could not set MLC_ADDR");
623 return ERROR_NAND_OPERATION_FAILED;
625 retval = target_write_u32(target, 0x200b8004,
627 if (ERROR_OK != retval) {
628 LOG_ERROR("could not set MLC_ADDR");
629 return ERROR_NAND_OPERATION_FAILED;
632 if (nand->address_cycles == 4) {
633 retval = target_write_u32(target, 0x200b8004,
634 (page >> 16) & 0xff);
635 if (ERROR_OK != retval) {
636 LOG_ERROR("could not set MLC_ADDR");
637 return ERROR_NAND_OPERATION_FAILED;
641 /* MLC_ADDR = 0x0 (two column cycles) */
642 retval = target_write_u32(target, 0x200b8004, 0x0);
643 if (ERROR_OK != retval) {
644 LOG_ERROR("could not set MLC_ADDR");
645 return ERROR_NAND_OPERATION_FAILED;
647 retval = target_write_u32(target, 0x200b8004, 0x0);
648 if (ERROR_OK != retval) {
649 LOG_ERROR("could not set MLC_ADDR");
650 return ERROR_NAND_OPERATION_FAILED;
654 retval = target_write_u32(target, 0x200b8004, page & 0xff);
655 if (ERROR_OK != retval) {
656 LOG_ERROR("could not set MLC_ADDR");
657 return ERROR_NAND_OPERATION_FAILED;
659 retval = target_write_u32(target, 0x200b8004,
661 if (ERROR_OK != retval) {
662 LOG_ERROR("could not set MLC_ADDR");
663 return ERROR_NAND_OPERATION_FAILED;
667 /* when using the MLC controller, we have to treat a large page device
668 * as being made out of four quarters, each the size of a small page
671 num_quarters = (nand->page_size == 2048) ? 4 : 1;
673 for (quarter = 0; quarter < num_quarters; quarter++) {
674 int thisrun_data_size = (data_size > 512) ? 512 : data_size;
675 int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
677 memset(page_buffer, 0xff, 512);
679 memcpy(page_buffer, data, thisrun_data_size);
680 data_size -= thisrun_data_size;
681 data += thisrun_data_size;
684 memset(oob_buffer, 0xff, 6);
686 memcpy(oob_buffer, oob, thisrun_oob_size);
687 oob_size -= thisrun_oob_size;
688 oob += thisrun_oob_size;
691 /* write MLC_ECC_ENC_REG to start encode cycle */
692 retval = target_write_u32(target, 0x200b8008, 0x0);
693 if (ERROR_OK != retval) {
694 LOG_ERROR("could not set MLC_ECC_ENC_REG");
695 return ERROR_NAND_OPERATION_FAILED;
698 retval = target_write_memory(target, 0x200a8000,
699 4, 128, page_buffer);
700 if (ERROR_OK != retval) {
701 LOG_ERROR("could not set MLC_BUF (data)");
702 return ERROR_NAND_OPERATION_FAILED;
704 retval = target_write_memory(target, 0x200a8000,
706 if (ERROR_OK != retval) {
707 LOG_ERROR("could not set MLC_BUF (oob)");
708 return ERROR_NAND_OPERATION_FAILED;
711 /* write MLC_ECC_AUTO_ENC_REG to start auto encode */
712 retval = target_write_u32(target, 0x200b8010, 0x0);
713 if (ERROR_OK != retval) {
714 LOG_ERROR("could not set MLC_ECC_AUTO_ENC_REG");
715 return ERROR_NAND_OPERATION_FAILED;
718 if (!lpc32xx_controller_ready(nand, 1000)) {
719 LOG_ERROR("timeout while waiting for "
720 "completion of auto encode cycle");
721 return ERROR_NAND_OPERATION_FAILED;
725 /* MLC_CMD = auto program command */
726 retval = target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
727 if (ERROR_OK != retval) {
728 LOG_ERROR("could not set MLC_CMD");
729 return ERROR_NAND_OPERATION_FAILED;
732 if ((retval = nand_read_status(nand, &status)) != ERROR_OK) {
733 LOG_ERROR("couldn't read status");
734 return ERROR_NAND_OPERATION_FAILED;
737 if (status & NAND_STATUS_FAIL) {
738 LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
740 return ERROR_NAND_OPERATION_FAILED;
746 /* SLC controller in !raw mode will use target cpu to read/write nand from/to
747 * target internal memory. The transfer to/from flash is done by DMA. This
748 * function sets up the dma linked list in host memory for later transfer to
751 static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
754 uint32_t i, dmasrc, ctrl, ecc_ctrl, oob_ctrl, dmadst;
758 Source burst size =16,
759 Destination burst size = 16,
760 Source transfer width = 32 bit,
761 Destination transfer width = 32 bit,
762 Source AHB master select = M0,
763 Destination AHB master select = M0,
764 Source increment = 0, // set later
765 Destination increment = 0, // set later
766 Terminal count interrupt enable bit = 0 // set on last
768 * Write Operation Sequence for Small Block NAND
769 * ----------------------------------------------------------
770 * 1. X'fer 256 bytes of data from Memory to Flash.
771 * 2. Copy generated ECC data from Register to Spare Area
772 * 3. X'fer next 256 bytes of data from Memory to Flash.
773 * 4. Copy generated ECC data from Register to Spare Area.
774 * 5. X'fer 16 byets of Spare area from Memory to Flash.
775 * Read Operation Sequence for Small Block NAND
776 * ----------------------------------------------------------
777 * 1. X'fer 256 bytes of data from Flash to Memory.
778 * 2. Copy generated ECC data from Register to ECC calc Buffer.
779 * 3. X'fer next 256 bytes of data from Flash to Memory.
780 * 4. Copy generated ECC data from Register to ECC calc Buffer.
781 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
782 * Write Operation Sequence for Large Block NAND
783 * ----------------------------------------------------------
784 * 1. Steps(1-4) of Write Operations repeate for four times
785 * which generates 16 DMA descriptors to X'fer 2048 bytes of
786 * data & 32 bytes of ECC data.
787 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
788 * Read Operation Sequence for Large Block NAND
789 * ----------------------------------------------------------
790 * 1. Steps(1-4) of Read Operations repeate for four times
791 * which generates 16 DMA descriptors to X'fer 2048 bytes of
792 * data & 32 bytes of ECC data.
793 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
796 ctrl = (0x40 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
797 | 0 << 25 | 0 << 26 | 0 << 27 | 0 << 31);
801 Source burst size =4,
802 Destination burst size = 4,
803 Source transfer width = 32 bit,
804 Destination transfer width = 32 bit,
805 Source AHB master select = M0,
806 Destination AHB master select = M0,
807 Source increment = 0,
808 Destination increment = 1,
809 Terminal count interrupt enable bit = 0
811 ecc_ctrl = 0x01 | 1 << 12 | 1 << 15 | 2 << 18 | 2 << 21 | 0 << 24
812 | 0 << 25 | 0 << 26 | 1 << 27 | 0 << 31;
815 TransferSize =16 for lp or 4 for sp,
816 Source burst size =16,
817 Destination burst size = 16,
818 Source transfer width = 32 bit,
819 Destination transfer width = 32 bit,
820 Source AHB master select = M0,
821 Destination AHB master select = M0,
822 Source increment = 0, // set later
823 Destination increment = 0, // set later
824 Terminal count interrupt enable bit = 1 // set on last
826 oob_ctrl = (page_size == 2048 ? 0x10 : 0x04)
827 | 3 << 12 | 3 << 15 | 2 << 18 | 2 << 21 | 0 << 24
828 | 0 << 25 | 0 << 26 | 0 << 27 | 1 << 31;
830 ctrl |= 1 << 27; /* Destination increment = 1 */
831 oob_ctrl |= 1 << 27; /* Destination increment = 1 */
832 dmasrc = 0x20020038; /* SLC_DMA_DATA */
833 dmadst = target_mem_base + DATA_OFFS;
835 ctrl |= 1 << 26; /* Source increment = 1 */
836 oob_ctrl |= 1 << 26; /* Source increment = 1 */
837 dmasrc = target_mem_base + DATA_OFFS;
838 dmadst = 0x20020038; /* SLC_DMA_DATA */
841 * Write Operation Sequence for Small Block NAND
842 * ----------------------------------------------------------
843 * 1. X'fer 256 bytes of data from Memory to Flash.
844 * 2. Copy generated ECC data from Register to Spare Area
845 * 3. X'fer next 256 bytes of data from Memory to Flash.
846 * 4. Copy generated ECC data from Register to Spare Area.
847 * 5. X'fer 16 byets of Spare area from Memory to Flash.
848 * Read Operation Sequence for Small Block NAND
849 * ----------------------------------------------------------
850 * 1. X'fer 256 bytes of data from Flash to Memory.
851 * 2. Copy generated ECC data from Register to ECC calc Buffer.
852 * 3. X'fer next 256 bytes of data from Flash to Memory.
853 * 4. Copy generated ECC data from Register to ECC calc Buffer.
854 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
855 * Write Operation Sequence for Large Block NAND
856 * ----------------------------------------------------------
857 * 1. Steps(1-4) of Write Operations repeate for four times
858 * which generates 16 DMA descriptors to X'fer 2048 bytes of
859 * data & 32 bytes of ECC data.
860 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
861 * Read Operation Sequence for Large Block NAND
862 * ----------------------------------------------------------
863 * 1. Steps(1-4) of Read Operations repeate for four times
864 * which generates 16 DMA descriptors to X'fer 2048 bytes of
865 * data & 32 bytes of ECC data.
866 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
868 for (i = 0; i < page_size/0x100; i++)
870 dmalist[i*2].dma_src = (do_read ? dmasrc : (dmasrc + i * 256));
871 dmalist[i*2].dma_dest = (do_read ? (dmadst + i * 256) : dmadst);
872 dmalist[i*2].next_lli =
873 target_mem_base + (i*2 + 1) * sizeof(dmac_ll_t);
874 dmalist[i*2].next_ctrl = ctrl;
876 dmalist[(i*2) + 1].dma_src = 0x20020034; /* SLC_ECC */
877 dmalist[(i*2) + 1].dma_dest =
878 target_mem_base + ECC_OFFS + i * 4;
879 dmalist[(i*2) + 1].next_lli =
880 target_mem_base + (i*2 + 2) * sizeof(dmac_ll_t);
881 dmalist[(i*2) + 1].next_ctrl = ecc_ctrl;
886 dmadst = target_mem_base + SPARE_OFFS;
888 dmasrc = target_mem_base + SPARE_OFFS;
889 dmalist[(i*2) - 1].next_lli = 0; /* last link = null on write */
890 dmalist[(i*2) - 1].next_ctrl |= (1 << 31); /* Set TC enable */
892 dmalist[i*2].dma_src = dmasrc;
893 dmalist[i*2].dma_dest = dmadst;
894 dmalist[i*2].next_lli = 0;
895 dmalist[i*2].next_ctrl = oob_ctrl;
897 return (i*2 + 1); /* Number of descriptors */
900 static int lpc32xx_start_slc_dma(struct nand_device *nand, uint32_t count,
903 struct target *target = nand->target;
906 /* DMACIntTCClear = ch0 */
907 retval = target_write_u32(target, 0x31000008, 1);
908 if (ERROR_OK != retval) {
909 LOG_ERROR("Could not set DMACIntTCClear");
913 /* DMACIntErrClear = ch0 */
914 retval = target_write_u32(target, 0x31000010, 1);
915 if (ERROR_OK != retval) {
916 LOG_ERROR("Could not set DMACIntErrClear");
922 SrcPeripheral = 1 (SLC),
923 DestPeripheral = 1 (SLC),
924 FlowCntrl = 2 (Pher -> Mem, DMA),
930 retval = target_write_u32(target, 0x31000110,
931 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
932 | 0<<15 | 0<<16 | 0<<18);
933 if (ERROR_OK != retval) {
934 LOG_ERROR("Could not set DMACC0Config");
938 /* SLC_CTRL = 3 (START DMA), ECC_CLEAR */
939 retval = target_write_u32(target, 0x20020010, 0x3);
940 if (ERROR_OK != retval) {
941 LOG_ERROR("Could not set SLC_CTRL");
945 /* SLC_ICR = 2, INT_TC_CLR, clear pending TC*/
946 retval = target_write_u32(target, 0x20020028, 2);
947 if (ERROR_OK != retval) {
948 LOG_ERROR("Could not set SLC_ICR");
953 retval = target_write_u32(target, 0x20020030, count);
954 if (ERROR_OK != retval) {
955 LOG_ERROR("lpc32xx_start_slc_dma: Could not set SLC_TC");
960 if (do_wait && !lpc32xx_tc_ready(nand, 100)) {
961 LOG_ERROR("timeout while waiting for completion of DMA");
962 return ERROR_NAND_OPERATION_FAILED;
968 static int lpc32xx_dma_ready(struct nand_device *nand, int timeout)
970 struct target *target = nand->target;
972 LOG_DEBUG("lpc32xx_dma_ready count start=%d", timeout);
979 /* Read DMACRawIntTCStat */
980 retval = target_read_u32(target, 0x31000014, &tc_stat);
981 if (ERROR_OK != retval) {
982 LOG_ERROR("Could not read DMACRawIntTCStat");
985 /* Read DMACRawIntErrStat */
986 retval = target_read_u32(target, 0x31000018, &err_stat);
987 if (ERROR_OK != retval) {
988 LOG_ERROR("Could not read DMACRawIntErrStat");
991 if ((tc_stat | err_stat) & 1) {
992 LOG_DEBUG("lpc32xx_dma_ready count=%d",
995 LOG_ERROR("lpc32xx_dma_ready "
996 "DMA error, aborted");
1004 } while (timeout-- > 0);
1009 static uint32_t slc_ecc_copy_to_buffer(uint8_t * spare,
1010 const uint32_t * ecc, int count)
1013 for (i = 0; i < (count * 3); i += 3) {
1014 uint32_t ce = ecc[i/3];
1015 ce = ~(ce << 2) & 0xFFFFFF;
1016 spare[i+2] = (uint8_t)(ce & 0xFF); ce >>= 8;
1017 spare[i+1] = (uint8_t)(ce & 0xFF); ce >>= 8;
1018 spare[i] = (uint8_t)(ce & 0xFF);
1023 static void lpc32xx_dump_oob(uint8_t *oob, uint32_t oob_size)
1026 while (oob_size > 0) {
1027 LOG_DEBUG("%02x: %02x %02x %02x %02x %02x %02x %02x %02x", addr,
1028 oob[0], oob[1], oob[2], oob[3],
1029 oob[4], oob[5], oob[6], oob[7]);
1036 static int lpc32xx_write_page_slc(struct nand_device *nand,
1037 struct working_area *pworking_area,
1038 uint32_t page, uint8_t *data,
1039 uint32_t data_size, uint8_t *oob,
1042 struct target *target = nand->target;
1044 uint32_t target_mem_base;
1046 LOG_DEBUG("SLC write page %x data=%d, oob=%d, "
1047 "data_size=%d, oob_size=%d",
1048 page, data != 0, oob != 0, data_size, oob_size);
1050 target_mem_base = pworking_area->address;
1052 * Skip writting page which has all 0xFF data as this will
1053 * generate 0x0 value.
1056 uint32_t i, all_ff = 1;
1057 for (i = 0; i < data_size; i++)
1058 if (data[i] != 0xFF) {
1065 /* Make the dma descriptors in local memory */
1066 int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 0);
1067 /* Write them to target.
1068 XXX: Assumes host and target have same byte sex.
1070 retval = target_write_memory(target, target_mem_base, 4,
1071 nll * sizeof(dmac_ll_t) / 4,
1072 (uint8_t *)dmalist);
1073 if (ERROR_OK != retval) {
1074 LOG_ERROR("Could not write DMA descriptors to IRAM");
1078 retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
1079 if (ERROR_OK != retval) {
1080 LOG_ERROR("NAND_CMD_SEQIN failed");
1092 retval = target_write_u32(target, 0x20020014, 0x3c);
1093 if (ERROR_OK != retval) {
1094 LOG_ERROR("Could not set SLC_CFG");
1098 /* Write data to target */
1099 static uint8_t fdata[2048];
1100 memset(fdata, 0xFF, nand->page_size);
1101 memcpy(fdata, data, data_size);
1102 retval = target_write_memory(target,
1103 target_mem_base + DATA_OFFS,
1104 4, nand->page_size/4, fdata);
1105 if (ERROR_OK != retval) {
1106 LOG_ERROR("Could not write data to IRAM");
1110 /* Write first decriptor to DMA controller */
1111 retval = target_write_memory(target, 0x31000100, 4,
1112 sizeof(dmac_ll_t) / 4,
1113 (uint8_t *)dmalist);
1114 if (ERROR_OK != retval) {
1115 LOG_ERROR("Could not write DMA descriptor to DMAC");
1119 /* Start xfer of data from iram to flash using DMA */
1120 int tot_size = nand->page_size;
1121 tot_size += tot_size == 2048 ? 64 : 16;
1122 retval = lpc32xx_start_slc_dma(nand, tot_size, 0);
1123 if (ERROR_OK != retval) {
1124 LOG_ERROR("DMA failed");
1128 /* Wait for DMA to finish. SLC is not finished at this stage */
1129 if (!lpc32xx_dma_ready(nand, 100)) {
1130 LOG_ERROR("Data DMA failed during write");
1131 return ERROR_FLASH_OPERATION_FAILED;
1135 /* Copy OOB to iram */
1136 static uint8_t foob[64];
1137 int foob_size = nand->page_size == 2048 ? 64 : 16;
1138 memset(foob, 0xFF, foob_size);
1139 if (oob) { /* Raw mode */
1140 memcpy(foob, oob, oob_size);
1142 /* Get HW generated ECC, made while writing data */
1143 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1144 static uint32_t hw_ecc[8];
1145 retval = target_read_memory(target, target_mem_base + ECC_OFFS,
1146 4, ecc_count, (uint8_t *)hw_ecc);
1147 if (ERROR_OK != retval) {
1148 LOG_ERROR("Reading hw generated ECC from IRAM failed");
1151 /* Copy to oob, at correct offsets */
1152 static uint8_t ecc[24];
1153 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1154 int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1156 for (i = 0; i < ecc_count * 3; i++)
1157 foob[layout[i]] = ecc[i];
1158 lpc32xx_dump_oob(foob, foob_size);
1160 retval = target_write_memory(target, target_mem_base + SPARE_OFFS, 4,
1161 foob_size / 4, foob);
1162 if (ERROR_OK != retval) {
1163 LOG_ERROR("Writing OOB to IRAM failed");
1167 /* Write OOB decriptor to DMA controller */
1168 retval = target_write_memory(target, 0x31000100, 4,
1169 sizeof(dmac_ll_t) / 4,
1170 (uint8_t *)(&dmalist[nll-1]));
1171 if (ERROR_OK != retval) {
1172 LOG_ERROR("Could not write OOB DMA descriptor to DMAC");
1176 /* Only restart DMA with last descriptor,
1177 * don't setup SLC again */
1179 /* DMACIntTCClear = ch0 */
1180 retval = target_write_u32(target, 0x31000008, 1);
1181 if (ERROR_OK != retval) {
1182 LOG_ERROR("Could not set DMACIntTCClear");
1187 SrcPeripheral = 1 (SLC),
1188 DestPeripheral = 1 (SLC),
1189 FlowCntrl = 2 (Pher -> Mem, DMA),
1195 retval = target_write_u32(target, 0x31000110,
1196 1 | 1<<1 | 1<<6 | 2<<11 | 0<<14
1197 | 0<<15 | 0<<16 | 0<<18);
1198 if (ERROR_OK != retval) {
1199 LOG_ERROR("Could not set DMACC0Config");
1203 if (!lpc32xx_tc_ready(nand, 100)) {
1204 LOG_ERROR("timeout while waiting for "
1205 "completion of DMA");
1206 return ERROR_NAND_OPERATION_FAILED;
1209 /* Start xfer of data from iram to flash using DMA */
1210 retval = lpc32xx_start_slc_dma(nand, foob_size, 1);
1211 if (ERROR_OK != retval) {
1212 LOG_ERROR("DMA OOB failed");
1217 /* Let NAND start actual writing */
1218 retval = nand_write_finish(nand);
1219 if (ERROR_OK != retval) {
1220 LOG_ERROR("nand_write_finish failed");
1227 static int lpc32xx_write_page(struct nand_device *nand, uint32_t page,
1228 uint8_t *data, uint32_t data_size,
1229 uint8_t *oob, uint32_t oob_size)
1231 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1232 struct target *target = nand->target;
1233 int retval = ERROR_OK;
1235 if (target->state != TARGET_HALTED) {
1236 LOG_ERROR("target must be halted to use LPC32xx "
1237 "NAND flash controller");
1238 return ERROR_NAND_OPERATION_FAILED;
1241 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1242 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1243 return ERROR_NAND_OPERATION_FAILED;
1244 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1246 LOG_ERROR("LPC32xx MLC controller can't write "
1248 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1251 if (oob && (oob_size > 24)) {
1252 LOG_ERROR("LPC32xx MLC controller can't write more "
1253 "than 6 bytes for each quarter's OOB data");
1254 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1257 if (data_size > (uint32_t)nand->page_size) {
1258 LOG_ERROR("data size exceeds page size");
1259 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1262 retval = lpc32xx_write_page_mlc(nand, page, data, data_size,
1264 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1265 struct working_area *pworking_area;
1268 * if oob only mode is active original method is used
1269 * as SLC controller hangs during DMA interworking. (?)
1270 * Anyway the code supports the oob only mode below.
1272 return nand_write_page_raw(nand, page, data,
1273 data_size, oob, oob_size);
1275 retval = target_alloc_working_area(target,
1276 nand->page_size + DATA_OFFS,
1278 if (retval != ERROR_OK) {
1279 LOG_ERROR("Can't allocate working area in "
1280 "LPC internal RAM");
1281 return ERROR_FLASH_OPERATION_FAILED;
1283 retval = lpc32xx_write_page_slc(nand, pworking_area, page,
1284 data, data_size, oob, oob_size);
1285 target_free_working_area(target, pworking_area);
1291 static int lpc32xx_read_page_mlc(struct nand_device *nand, uint32_t page,
1292 uint8_t *data, uint32_t data_size,
1293 uint8_t *oob, uint32_t oob_size)
1295 struct target *target = nand->target;
1296 static uint8_t page_buffer[2048];
1297 static uint8_t oob_buffer[64];
1298 uint32_t page_bytes_done = 0;
1299 uint32_t oob_bytes_done = 0;
1304 /* MLC_CMD = Read OOB
1305 * we can use the READOOB command on both small and large page
1306 * devices, as the controller translates the 0x50 command to
1307 * a 0x0 with appropriate positioning of the serial buffer
1310 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READOOB);
1312 /* MLC_CMD = Read0 */
1313 retval = target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
1315 if (ERROR_OK != retval) {
1316 LOG_ERROR("could not set MLC_CMD");
1317 return ERROR_NAND_OPERATION_FAILED;
1319 if (nand->page_size == 512) {
1320 /* small page device */
1321 /* MLC_ADDR = 0x0 (one column cycle) */
1322 retval = target_write_u32(target, 0x200b8004, 0x0);
1323 if (ERROR_OK != retval) {
1324 LOG_ERROR("could not set MLC_ADDR");
1325 return ERROR_NAND_OPERATION_FAILED;
1328 /* MLC_ADDR = row */
1329 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1330 if (ERROR_OK != retval) {
1331 LOG_ERROR("could not set MLC_ADDR");
1332 return ERROR_NAND_OPERATION_FAILED;
1334 retval = target_write_u32(target, 0x200b8004,
1335 (page >> 8) & 0xff);
1336 if (ERROR_OK != retval) {
1337 LOG_ERROR("could not set MLC_ADDR");
1338 return ERROR_NAND_OPERATION_FAILED;
1341 if (nand->address_cycles == 4) {
1342 retval = target_write_u32(target, 0x200b8004,
1343 (page >> 16) & 0xff);
1344 if (ERROR_OK != retval) {
1345 LOG_ERROR("could not set MLC_ADDR");
1346 return ERROR_NAND_OPERATION_FAILED;
1350 /* large page device */
1351 /* MLC_ADDR = 0x0 (two column cycles) */
1352 retval = target_write_u32(target, 0x200b8004, 0x0);
1353 if (ERROR_OK != retval) {
1354 LOG_ERROR("could not set MLC_ADDR");
1355 return ERROR_NAND_OPERATION_FAILED;
1357 retval = target_write_u32(target, 0x200b8004, 0x0);
1358 if (ERROR_OK != retval) {
1359 LOG_ERROR("could not set MLC_ADDR");
1360 return ERROR_NAND_OPERATION_FAILED;
1363 /* MLC_ADDR = row */
1364 retval = target_write_u32(target, 0x200b8004, page & 0xff);
1365 if (ERROR_OK != retval) {
1366 LOG_ERROR("could not set MLC_ADDR");
1367 return ERROR_NAND_OPERATION_FAILED;
1369 retval = target_write_u32(target, 0x200b8004,
1370 (page >> 8) & 0xff);
1371 if (ERROR_OK != retval) {
1372 LOG_ERROR("could not set MLC_ADDR");
1373 return ERROR_NAND_OPERATION_FAILED;
1376 /* MLC_CMD = Read Start */
1377 retval = target_write_u32(target, 0x200b8000,
1378 NAND_CMD_READSTART);
1379 if (ERROR_OK != retval) {
1380 LOG_ERROR("could not set MLC_CMD");
1381 return ERROR_NAND_OPERATION_FAILED;
1385 while (page_bytes_done < (uint32_t)nand->page_size) {
1386 /* MLC_ECC_AUTO_DEC_REG = dummy */
1387 retval = target_write_u32(target, 0x200b8014, 0xaa55aa55);
1388 if (ERROR_OK != retval) {
1389 LOG_ERROR("could not set MLC_ECC_AUTO_DEC_REG");
1390 return ERROR_NAND_OPERATION_FAILED;
1393 if (!lpc32xx_controller_ready(nand, 1000)) {
1394 LOG_ERROR("timeout while waiting for "
1395 "completion of auto decode cycle");
1396 return ERROR_NAND_OPERATION_FAILED;
1399 retval = target_read_u32(target, 0x200b8048, &mlc_isr);
1400 if (ERROR_OK != retval) {
1401 LOG_ERROR("could not read MLC_ISR");
1402 return ERROR_NAND_OPERATION_FAILED;
1405 if (mlc_isr & 0x8) {
1406 if (mlc_isr & 0x40) {
1407 LOG_ERROR("uncorrectable error detected: "
1408 "0x%2.2x", (unsigned)mlc_isr);
1409 return ERROR_NAND_OPERATION_FAILED;
1412 LOG_WARNING("%i symbol error detected and corrected",
1413 ((int)(((mlc_isr & 0x30) >> 4) + 1)));
1417 retval = target_read_memory(target, 0x200a8000, 4, 128,
1418 page_buffer + page_bytes_done);
1419 if (ERROR_OK != retval) {
1420 LOG_ERROR("could not read MLC_BUF (data)");
1421 return ERROR_NAND_OPERATION_FAILED;
1426 retval = target_read_memory(target, 0x200a8000, 4, 4,
1427 oob_buffer + oob_bytes_done);
1428 if (ERROR_OK != retval) {
1429 LOG_ERROR("could not read MLC_BUF (oob)");
1430 return ERROR_NAND_OPERATION_FAILED;
1434 page_bytes_done += 512;
1435 oob_bytes_done += 16;
1439 memcpy(data, page_buffer, data_size);
1442 memcpy(oob, oob_buffer, oob_size);
1447 static int lpc32xx_read_page_slc(struct nand_device *nand,
1448 struct working_area *pworking_area,
1449 uint32_t page, uint8_t *data,
1450 uint32_t data_size, uint8_t *oob,
1453 struct target *target = nand->target;
1455 uint32_t target_mem_base;
1457 LOG_DEBUG("SLC read page %x data=%d, oob=%d",
1458 page, data_size, oob_size);
1460 target_mem_base = pworking_area->address;
1462 /* Make the dma descriptors in local memory */
1463 int nll = lpc32xx_make_dma_list(target_mem_base, nand->page_size, 1);
1464 /* Write them to target.
1465 XXX: Assumes host and target have same byte sex.
1467 retval = target_write_memory(target, target_mem_base, 4,
1468 nll * sizeof(dmac_ll_t) / 4,
1469 (uint8_t *)dmalist);
1470 if (ERROR_OK != retval) {
1471 LOG_ERROR("Could not write DMA descriptors to IRAM");
1475 retval = nand_page_command(nand, page, NAND_CMD_READ0, 0);
1476 if (ERROR_OK != retval) {
1477 LOG_ERROR("lpc32xx_read_page_slc: NAND_CMD_READ0 failed");
1489 retval = target_write_u32(target, 0x20020014, 0x3e);
1490 if (ERROR_OK != retval) {
1491 LOG_ERROR("lpc32xx_read_page_slc: Could not set SLC_CFG");
1495 /* Write first decriptor to DMA controller */
1496 retval = target_write_memory(target, 0x31000100, 4,
1497 sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
1498 if (ERROR_OK != retval) {
1499 LOG_ERROR("Could not write DMA descriptor to DMAC");
1503 /* Start xfer of data from flash to iram using DMA */
1504 int tot_size = nand->page_size;
1505 tot_size += nand->page_size == 2048 ? 64 : 16;
1506 retval = lpc32xx_start_slc_dma(nand, tot_size, 1);
1507 if (ERROR_OK != retval) {
1508 LOG_ERROR("lpc32xx_read_page_slc: DMA read failed");
1512 /* Copy data from iram */
1514 retval = target_read_memory(target, target_mem_base + DATA_OFFS,
1515 4, data_size/4, data);
1516 if (ERROR_OK != retval) {
1517 LOG_ERROR("Could not read data from IRAM");
1522 /* No error correction, just return data as read from flash */
1523 retval = target_read_memory(target,
1524 target_mem_base + SPARE_OFFS, 4,
1526 if (ERROR_OK != retval) {
1527 LOG_ERROR("Could not read OOB from IRAM");
1533 /* Copy OOB from flash, stored in IRAM */
1534 static uint8_t foob[64];
1535 retval = target_read_memory(target, target_mem_base + SPARE_OFFS,
1536 4, nand->page_size == 2048 ? 16 : 4, foob);
1537 lpc32xx_dump_oob(foob, nand->page_size == 2048 ? 64 : 16);
1538 if (ERROR_OK != retval) {
1539 LOG_ERROR("Could not read OOB from IRAM");
1542 /* Copy ECC from HW, generated while reading */
1543 int ecc_count = nand->page_size == 2048 ? 8 : 2;
1544 static uint32_t hw_ecc[8]; /* max size */
1545 retval = target_read_memory(target, target_mem_base + ECC_OFFS, 4,
1546 ecc_count, (uint8_t *)hw_ecc);
1547 if (ERROR_OK != retval) {
1548 LOG_ERROR("Could not read hw generated ECC from IRAM");
1551 static uint8_t ecc[24];
1552 slc_ecc_copy_to_buffer(ecc, hw_ecc, ecc_count);
1553 /* Copy ECC from flash using correct layout */
1554 static uint8_t fecc[24]; /* max size */
1555 int *layout = nand->page_size == 2048 ? lp_ooblayout : sp_ooblayout;
1557 for (i = 0; i < ecc_count * 3; i++)
1558 fecc[i] = foob[layout[i]];
1559 /* Compare ECC and possibly correct data */
1560 for (i = 0; i < ecc_count; i++) {
1561 retval = nand_correct_data(nand, data + 256*i, &fecc[i * 3],
1564 LOG_WARNING("error detected and corrected: %d/%d",
1572 LOG_ERROR("uncorrectable error detected: %d/%d", page, i);
1573 retval = ERROR_NAND_OPERATION_FAILED;
1578 static int lpc32xx_read_page(struct nand_device *nand, uint32_t page,
1579 uint8_t *data, uint32_t data_size,
1580 uint8_t *oob, uint32_t oob_size)
1582 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1583 struct target *target = nand->target;
1584 int retval = ERROR_OK;
1586 if (target->state != TARGET_HALTED) {
1587 LOG_ERROR("target must be halted to use LPC32xx "
1588 "NAND flash controller");
1589 return ERROR_NAND_OPERATION_FAILED;
1592 if (lpc32xx_info->selected_controller == LPC32xx_NO_CONTROLLER) {
1593 LOG_ERROR("BUG: no LPC32xx NAND flash controller selected");
1594 return ERROR_NAND_OPERATION_FAILED;
1595 } else if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1596 if (data_size > (uint32_t)nand->page_size) {
1597 LOG_ERROR("data size exceeds page size");
1598 return ERROR_NAND_OPERATION_NOT_SUPPORTED;
1600 retval = lpc32xx_read_page_mlc(nand, page, data, data_size,
1602 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1603 struct working_area *pworking_area;
1605 retval = target_alloc_working_area(target,
1606 nand->page_size + 0x200,
1608 if (retval != ERROR_OK) {
1609 LOG_ERROR("Can't allocate working area in "
1610 "LPC internal RAM");
1611 return ERROR_FLASH_OPERATION_FAILED;
1613 retval = lpc32xx_read_page_slc(nand, pworking_area, page,
1614 data, data_size, oob, oob_size);
1615 target_free_working_area(target, pworking_area);
1621 static int lpc32xx_controller_ready(struct nand_device *nand, int timeout)
1623 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1624 struct target *target = nand->target;
1627 if (target->state != TARGET_HALTED) {
1628 LOG_ERROR("target must be halted to use LPC32xx "
1629 "NAND flash controller");
1630 return ERROR_NAND_OPERATION_FAILED;
1633 LOG_DEBUG("lpc32xx_controller_ready count start=%d", timeout);
1636 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1639 /* Read MLC_ISR, wait for controller to become ready */
1640 retval = target_read_u8(target, 0x200b8048, &status);
1641 if (ERROR_OK != retval) {
1642 LOG_ERROR("could not set MLC_STAT");
1643 return ERROR_NAND_OPERATION_FAILED;
1647 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1651 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1654 /* Read SLC_STAT and check READY bit */
1655 retval = target_read_u32(target, 0x20020018, &status);
1656 if (ERROR_OK != retval) {
1657 LOG_ERROR("could not set SLC_STAT");
1658 return ERROR_NAND_OPERATION_FAILED;
1662 LOG_DEBUG("lpc32xx_controller_ready count=%d",
1669 } while (timeout-- > 0);
1674 static int lpc32xx_nand_ready(struct nand_device *nand, int timeout)
1676 struct lpc32xx_nand_controller *lpc32xx_info = nand->controller_priv;
1677 struct target *target = nand->target;
1680 if (target->state != TARGET_HALTED) {
1681 LOG_ERROR("target must be halted to use LPC32xx "
1682 "NAND flash controller");
1683 return ERROR_NAND_OPERATION_FAILED;
1686 LOG_DEBUG("lpc32xx_nand_ready count start=%d", timeout);
1689 if (lpc32xx_info->selected_controller == LPC32xx_MLC_CONTROLLER) {
1690 uint8_t status = 0x0;
1692 /* Read MLC_ISR, wait for NAND flash device to
1694 retval = target_read_u8(target, 0x200b8048, &status);
1695 if (ERROR_OK != retval) {
1696 LOG_ERROR("could not read MLC_ISR");
1697 return ERROR_NAND_OPERATION_FAILED;
1701 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1705 } else if (lpc32xx_info->selected_controller == LPC32xx_SLC_CONTROLLER) {
1706 uint32_t status = 0x0;
1708 /* Read SLC_STAT and check READY bit */
1709 retval = target_read_u32(target, 0x20020018, &status);
1710 if (ERROR_OK != retval) {
1711 LOG_ERROR("could not read SLC_STAT");
1712 return ERROR_NAND_OPERATION_FAILED;
1716 LOG_DEBUG("lpc32xx_nand_ready count end=%d",
1723 } while (timeout-- > 0);
1728 static int lpc32xx_tc_ready(struct nand_device *nand, int timeout)
1730 struct target *target = nand->target;
1732 LOG_DEBUG("lpc32xx_tc_ready count start=%d", timeout);
1735 uint32_t status = 0x0;
1737 /* Read SLC_INT_STAT and check INT_TC_STAT bit */
1738 retval = target_read_u32(target, 0x2002001c, &status);
1739 if (ERROR_OK != retval) {
1740 LOG_ERROR("Could not read SLC_INT_STAT");
1744 LOG_DEBUG("lpc32xx_tc_ready count=%d", timeout);
1749 } while (timeout-- > 0);
1754 COMMAND_HANDLER(handle_lpc32xx_select_command)
1756 struct lpc32xx_nand_controller *lpc32xx_info = NULL;
1757 char *selected[] = {
1761 if ((CMD_ARGC < 1) || (CMD_ARGC > 3)) {
1762 return ERROR_COMMAND_SYNTAX_ERROR;
1766 COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
1767 struct nand_device *nand = get_nand_device_by_num(num);
1769 command_print(CMD_CTX, "nand device '#%s' is out of bounds",
1774 lpc32xx_info = nand->controller_priv;
1776 if (CMD_ARGC >= 2) {
1777 if (strcmp(CMD_ARGV[1], "mlc") == 0) {
1778 lpc32xx_info->selected_controller =
1779 LPC32xx_MLC_CONTROLLER;
1780 } else if (strcmp(CMD_ARGV[1], "slc") == 0) {
1781 lpc32xx_info->selected_controller =
1782 LPC32xx_SLC_CONTROLLER;
1784 return ERROR_COMMAND_SYNTAX_ERROR;
1788 command_print(CMD_CTX, "%s controller selected",
1789 selected[lpc32xx_info->selected_controller]);
1794 static const struct command_registration lpc32xx_exec_command_handlers[] = {
1797 .handler = handle_lpc32xx_select_command,
1798 .mode = COMMAND_EXEC,
1799 .help = "select MLC or SLC controller (default is MLC)",
1800 .usage = "bank_id ['mlc'|'slc' ]",
1802 COMMAND_REGISTRATION_DONE
1804 static const struct command_registration lpc32xx_command_handler[] = {
1807 .mode = COMMAND_ANY,
1808 .help = "LPC32xx NAND flash controller commands",
1810 .chain = lpc32xx_exec_command_handlers,
1812 COMMAND_REGISTRATION_DONE
1815 struct nand_flash_controller lpc32xx_nand_controller = {
1817 .commands = lpc32xx_command_handler,
1818 .nand_device_command = lpc32xx_nand_device_command,
1819 .init = lpc32xx_init,
1820 .reset = lpc32xx_reset,
1821 .command = lpc32xx_command,
1822 .address = lpc32xx_address,
1823 .write_data = lpc32xx_write_data,
1824 .read_data = lpc32xx_read_data,
1825 .write_page = lpc32xx_write_page,
1826 .read_page = lpc32xx_read_page,
1827 .nand_ready = lpc32xx_nand_ready,