git.sur5r.net Git - openocd/blob - src/flash/nand/mx2.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Alexei Babich                                   *
   3  *   Rezonans plc., Chelyabinsk, Russia                                    *
   4  *   impatt@mail.ru                                                        *
   5  *                                                                         *
   6  *   Copyright (C) 2010 by Gaetan CARLIER                                  *
   7  *   Trump s.a., Belgium                                                   *
   8  *                                                                         *
   9  *   This program is free software; you can redistribute it and/or modify  *
  10  *   it under the terms of the GNU General Public License as published by  *
  11  *   the Free Software Foundation; either version 2 of the License, or     *
  12  *   (at your option) any later version.                                   *
  13  *                                                                         *
  14  *   This program is distributed in the hope that it will be useful,       *
  15  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  16  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  17  *   GNU General Public License for more details.                          *
  18  *                                                                         *
  19  *   You should have received a copy of the GNU General Public License     *
  20  *   along with this program; if not, write to the                         *
  21  *   Free Software Foundation, Inc.,                                       *
  22  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  23  ***************************************************************************/
  24
  25 /*
  26  * Freescale iMX OpenOCD NAND Flash controller support.
  27  * based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
  28  */
  29
  30 /*
  31  * driver tested with Samsung K9F2G08UXA and Numonyx/ST NAND02G-B2D @mxc
  32  * tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #",
  33  * "nand write # file 0", "nand verify"
  34  *
  35  * get_next_halfword_from_sram_buffer() not tested
  36  * !! all function only tested with 2k page nand device; mxc_write_page
  37  *    writes the 4 MAIN_BUFFER's and is not compatible with < 2k page
  38  * !! oob must be be used due to NFS bug
  39 */
  40 #ifdef HAVE_CONFIG_H
  41 #include "config.h"
  42 #endif
  43
  44 #include "imp.h"
  45 #include "mx2.h"
  46 #include <target/target.h>
  47
  48 /* This permits to print (in LOG_INFO) how much bytes
  49  * has been written after a page read or write.
  50  * This is useful when OpenOCD is used with a graphical
  51  * front-end to estimate progression of the global read/write
  52  */
  53 #undef _MXC_PRINT_STAT
  54 /* #define _MXC_PRINT_STAT */
  55
  56 static const char target_not_halted_err_msg[] =
  57         "target must be halted to use mxc NAND flash controller";
  58 static const char data_block_size_err_msg[] =
  59         "minimal granularity is one half-word, %" PRId32 " is incorrect";
  60 static const char sram_buffer_bounds_err_msg[] =
  61         "trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
  62 static const char get_status_register_err_msg[] = "can't get NAND status";
  63 static uint32_t in_sram_address;
  64 static unsigned char sign_of_sequental_byte_read;
  65
  66 static int initialize_nf_controller(struct nand_device *nand);
  67 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value);
  68 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value);
  69 static int poll_for_complete_op(struct nand_device *nand, const char *text);
  70 static int validate_target_state(struct nand_device *nand);
  71 static int do_data_output(struct nand_device *nand);
  72
  73 static int mxc_command(struct nand_device *nand, uint8_t command);
  74 static int mxc_address(struct nand_device *nand, uint8_t address);
  75
  76 NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
  77 {
  78         struct mxc_nf_controller *mxc_nf_info;
  79         int hwecc_needed;
  80         int x;
  81
  82         mxc_nf_info = malloc(sizeof(struct mxc_nf_controller));
  83         if (mxc_nf_info == NULL) {
  84                 LOG_ERROR("no memory for nand controller");
  85                 return ERROR_FAIL;
  86         }
  87         nand->controller_priv = mxc_nf_info;
  88
  89         if (CMD_ARGC < 4) {
  90                 LOG_ERROR("use \"nand device mxc target mx27|mx31|mx35 noecc|hwecc [biswap]\"");
  91                 return ERROR_FAIL;
  92         }
  93
  94         /*
  95          * check board type
  96          */
  97         if (strcmp(CMD_ARGV[2], "mx27") == 0)
  98                 mxc_nf_info->mxc_base_addr = 0xD8000000;
  99         else if (strcmp(CMD_ARGV[2], "mx31") == 0)
 100                 mxc_nf_info->mxc_base_addr = 0xB8000000;
 101         else if (strcmp(CMD_ARGV[2], "mx35") == 0)
 102                 mxc_nf_info->mxc_base_addr = 0xBB000000;
 103
 104         /*
 105          * check hwecc requirements
 106          */
 107         hwecc_needed = strcmp(CMD_ARGV[3], "hwecc");
 108         if (hwecc_needed == 0)
 109                 mxc_nf_info->flags.hw_ecc_enabled = 1;
 110         else
 111                 mxc_nf_info->flags.hw_ecc_enabled = 0;
 112
 113         mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 114         mxc_nf_info->fin = MXC_NF_FIN_NONE;
 115         mxc_nf_info->flags.target_little_endian =
 116         (nand->target->endianness == TARGET_LITTLE_ENDIAN);
 117
 118         /*
 119          * should factory bad block indicator be swaped
 120          * as a workaround for how the nfc handles pages.
 121          */
 122         if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
 123                 LOG_DEBUG("BI-swap enabled");
 124                 mxc_nf_info->flags.biswap_enabled = 1;
 125         }
 126
 127         /*
 128          * testing host endianness
 129          */
 130         x = 1;
 131         if (*(char *) &x == 1)
 132                 mxc_nf_info->flags.host_little_endian = 1;
 133         else
 134                 mxc_nf_info->flags.host_little_endian = 0;
 135         return ERROR_OK;
 136 }
 137
 138 COMMAND_HANDLER(handle_mxc_biswap_command)
 139 {
 140         struct nand_device *nand = NULL;
 141         struct mxc_nf_controller *mxc_nf_info = NULL;
 142
 143         if (CMD_ARGC < 1 || CMD_ARGC > 2)
 144                 return ERROR_COMMAND_SYNTAX_ERROR;
 145
 146         int retval = CALL_COMMAND_HANDLER(nand_command_get_device, 0, &nand);
 147         if (retval != ERROR_OK) {
 148                 command_print(CMD_CTX, "invalid nand device number or name: %s", CMD_ARGV[0]);
 149                 return ERROR_COMMAND_ARGUMENT_INVALID;
 150         }
 151
 152         mxc_nf_info = nand->controller_priv;
 153         if (CMD_ARGC == 2) {
 154                 if (strcmp(CMD_ARGV[1], "enable") == 0)
 155                         mxc_nf_info->flags.biswap_enabled = true;
 156                 else
 157                         mxc_nf_info->flags.biswap_enabled = false;
 158         }
 159         if (mxc_nf_info->flags.biswap_enabled)
 160                 command_print(CMD_CTX, "BI-swapping enabled on %s", nand->name);
 161         else
 162                 command_print(CMD_CTX, "BI-swapping disabled on %s", nand->name);
 163
 164         return ERROR_OK;
 165 }
 166
 167 static const struct command_registration mxc_sub_command_handlers[] = {
 168         {
 169                 .name = "biswap",
 170                 .handler = handle_mxc_biswap_command ,
 171                 .help = "Turns on/off bad block information swaping from main area, "
 172                                 "without parameter query status.",
 173                 .usage = "bank_id ['enable'|'disable']",
 174         },
 175         COMMAND_REGISTRATION_DONE
 176 };
 177
 178 static const struct command_registration mxc_nand_command_handler[] = {
 179         {
 180                 .name = "mxc",
 181                 .mode = COMMAND_ANY,
 182                 .help = "MXC NAND flash controller commands",
 183                 .chain = mxc_sub_command_handlers
 184         },
 185         COMMAND_REGISTRATION_DONE
 186 };
 187
 188 static int mxc_init(struct nand_device *nand)
 189 {
 190         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 191         struct target *target = nand->target;
 192
 193         int validate_target_result;
 194         uint16_t buffsize_register_content;
 195         uint32_t pcsr_register_content;
 196         int retval;
 197         uint16_t nand_status_content;
 198         /*
 199          * validate target state
 200          */
 201         validate_target_result = validate_target_state(nand);
 202         if (validate_target_result != ERROR_OK)
 203                 return validate_target_result;
 204
 205         target_read_u16(target, MXC_NF_BUFSIZ, &buffsize_register_content);
 206         mxc_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
 207
 208         target_read_u32(target, MXC_FMCR, &pcsr_register_content);
 209         if (!nand->bus_width) {
 210                 /* bus_width not yet defined. Read it from MXC_FMCR */
 211                 nand->bus_width =
 212                         (pcsr_register_content & MXC_FMCR_NF_16BIT_SEL) ? 16 : 8;
 213         } else {
 214                 /* bus_width forced in soft. Sync it to MXC_FMCR */
 215                 pcsr_register_content |=
 216                         ((nand->bus_width == 16) ? MXC_FMCR_NF_16BIT_SEL : 0x00000000);
 217                 target_write_u32(target, MXC_FMCR, pcsr_register_content);
 218         }
 219         if (nand->bus_width == 16)
 220                 LOG_DEBUG("MXC_NF : bus is 16-bit width");
 221         else
 222                 LOG_DEBUG("MXC_NF : bus is 8-bit width");
 223
 224         if (!nand->page_size) {
 225                 nand->page_size = (pcsr_register_content & MXC_FMCR_NF_FMS) ? 2048 : 512;
 226         } else {
 227                 pcsr_register_content |=
 228                         ((nand->page_size == 2048) ? MXC_FMCR_NF_FMS : 0x00000000);
 229                 target_write_u32(target, MXC_FMCR, pcsr_register_content);
 230         }
 231         if (mxc_nf_info->flags.one_kb_sram && (nand->page_size == 2048)) {
 232                 LOG_ERROR("NAND controller have only 1 kb SRAM, so "
 233                           "pagesize 2048 is incompatible with it");
 234         } else {
 235                 LOG_DEBUG("MXC_NF : NAND controller can handle pagesize of 2048");
 236         }
 237
 238         initialize_nf_controller(nand);
 239
 240         retval = ERROR_OK;
 241         retval |= mxc_command(nand, NAND_CMD_STATUS);
 242         retval |= mxc_address(nand, 0x00);
 243         retval |= do_data_output(nand);
 244         if (retval != ERROR_OK) {
 245                 LOG_ERROR(get_status_register_err_msg);
 246                 return ERROR_FAIL;
 247         }
 248         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 249         if (!(nand_status_content & 0x0080)) {
 250                 LOG_INFO("NAND read-only");
 251                 mxc_nf_info->flags.nand_readonly = 1;
 252         } else {
 253                 mxc_nf_info->flags.nand_readonly = 0;
 254         }
 255         return ERROR_OK;
 256 }
 257
 258 static int mxc_read_data(struct nand_device *nand, void *data)
 259 {
 260         int validate_target_result;
 261         int try_data_output_from_nand_chip;
 262         /*
 263          * validate target state
 264          */
 265         validate_target_result = validate_target_state(nand);
 266         if (validate_target_result != ERROR_OK)
 267                 return validate_target_result;
 268
 269         /*
 270          * get data from nand chip
 271          */
 272         try_data_output_from_nand_chip = do_data_output(nand);
 273         if (try_data_output_from_nand_chip != ERROR_OK) {
 274                 LOG_ERROR("mxc_read_data : read data failed : '%x'",
 275                                   try_data_output_from_nand_chip);
 276                 return try_data_output_from_nand_chip;
 277         }
 278
 279         if (nand->bus_width == 16)
 280                 get_next_halfword_from_sram_buffer(nand, data);
 281         else
 282                 get_next_byte_from_sram_buffer(nand, data);
 283
 284         return ERROR_OK;
 285 }
 286
 287 static int mxc_write_data(struct nand_device *nand, uint16_t data)
 288 {
 289         LOG_ERROR("write_data() not implemented");
 290         return ERROR_NAND_OPERATION_FAILED;
 291 }
 292
 293 static int mxc_reset(struct nand_device *nand)
 294 {
 295         /*
 296          * validate target state
 297          */
 298         int validate_target_result;
 299         validate_target_result = validate_target_state(nand);
 300         if (validate_target_result != ERROR_OK)
 301                 return validate_target_result;
 302         initialize_nf_controller(nand);
 303         return ERROR_OK;
 304 }
 305
 306 static int mxc_command(struct nand_device *nand, uint8_t command)
 307 {
 308         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 309         struct target *target = nand->target;
 310         int validate_target_result;
 311         int poll_result;
 312         /*
 313          * validate target state
 314          */
 315         validate_target_result = validate_target_state(nand);
 316         if (validate_target_result != ERROR_OK)
 317                 return validate_target_result;
 318
 319         switch (command) {
 320         case NAND_CMD_READOOB:
 321                 command = NAND_CMD_READ0;
 322                 /* set read point for data_read() and read_block_data() to
 323                  * spare area in SRAM buffer
 324                  */
 325                 in_sram_address = MXC_NF_SPARE_BUFFER0;
 326                 break;
 327         case NAND_CMD_READ1:
 328                 command = NAND_CMD_READ0;
 329                 /*
 330                  * offset == one half of page size
 331                  */
 332                 in_sram_address = MXC_NF_MAIN_BUFFER0 + (nand->page_size >> 1);
 333                 break;
 334         default:
 335                 in_sram_address = MXC_NF_MAIN_BUFFER0;
 336                 break;
 337         }
 338
 339         target_write_u16(target, MXC_NF_FCMD, command);
 340         /*
 341          * start command input operation (set MXC_NF_BIT_OP_DONE==0)
 342          */
 343         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FCI);
 344         poll_result = poll_for_complete_op(nand, "command");
 345         if (poll_result != ERROR_OK)
 346                 return poll_result;
 347         /*
 348          * reset cursor to begin of the buffer
 349          */
 350         sign_of_sequental_byte_read = 0;
 351         /* Handle special read command and adjust NF_CFG2(FDO) */
 352         switch (command) {
 353         case NAND_CMD_READID:
 354                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDID;
 355                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 356                 break;
 357         case NAND_CMD_STATUS:
 358                 mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 359                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 360                 target_write_u16 (target, MXC_NF_BUFADDR, 0);
 361                 in_sram_address = 0;
 362                 break;
 363         case NAND_CMD_READ0:
 364                 mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 365                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 366                 break;
 367         default:
 368                 /* Ohter command use the default 'One page data out' FDO */
 369                 mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 370                 break;
 371         }
 372         return ERROR_OK;
 373 }
 374
 375 static int mxc_address(struct nand_device *nand, uint8_t address)
 376 {
 377         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 378         struct target *target = nand->target;
 379         int validate_target_result;
 380         int poll_result;
 381         /*
 382          * validate target state
 383          */
 384         validate_target_result = validate_target_state(nand);
 385         if (validate_target_result != ERROR_OK)
 386                 return validate_target_result;
 387
 388         target_write_u16(target, MXC_NF_FADDR, address);
 389         /*
 390          * start address input operation (set MXC_NF_BIT_OP_DONE==0)
 391          */
 392         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FAI);
 393         poll_result = poll_for_complete_op(nand, "address");
 394         if (poll_result != ERROR_OK)
 395                 return poll_result;
 396
 397         return ERROR_OK;
 398 }
 399
 400 static int mxc_nand_ready(struct nand_device *nand, int tout)
 401 {
 402         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 403         struct target *target = nand->target;
 404         uint16_t poll_complete_status;
 405         int validate_target_result;
 406
 407         /*
 408          * validate target state
 409          */
 410         validate_target_result = validate_target_state(nand);
 411         if (validate_target_result != ERROR_OK)
 412                 return validate_target_result;
 413
 414         do {
 415                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 416                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 417                         return tout;
 418
 419                 alive_sleep(1);
 420         }
 421         while (tout-- > 0);
 422         return tout;
 423 }
 424
 425 static int mxc_write_page(struct nand_device *nand, uint32_t page,
 426                                                         uint8_t *data, uint32_t data_size,
 427                                                         uint8_t *oob, uint32_t oob_size)
 428 {
 429         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 430         struct target *target = nand->target;
 431         int retval;
 432         uint16_t nand_status_content;
 433         uint16_t swap1, swap2, new_swap1;
 434         int poll_result;
 435         if (data_size % 2) {
 436                 LOG_ERROR(data_block_size_err_msg, data_size);
 437                 return ERROR_NAND_OPERATION_FAILED;
 438         }
 439         if (oob_size % 2) {
 440                 LOG_ERROR(data_block_size_err_msg, oob_size);
 441                 return ERROR_NAND_OPERATION_FAILED;
 442         }
 443         if (!data) {
 444                 LOG_ERROR("nothing to program");
 445                 return ERROR_NAND_OPERATION_FAILED;
 446         }
 447         /*
 448          * validate target state
 449          */
 450         retval = validate_target_state(nand);
 451         if (retval != ERROR_OK)
 452                 return retval;
 453
 454         in_sram_address = MXC_NF_MAIN_BUFFER0;
 455         sign_of_sequental_byte_read = 0;
 456         retval = ERROR_OK;
 457         retval |= mxc_command(nand, NAND_CMD_SEQIN);
 458         retval |= mxc_address(nand, 0); /* col */
 459         retval |= mxc_address(nand, 0); /* col */
 460         retval |= mxc_address(nand, page & 0xff); /* page address */
 461         retval |= mxc_address(nand, (page >> 8) & 0xff); /* page address */
 462         retval |= mxc_address(nand, (page >> 16) & 0xff); /* page address */
 463
 464         target_write_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 465         if (oob) {
 466                 if (mxc_nf_info->flags.hw_ecc_enabled) {
 467                         /*
 468                          * part of spare block will be overrided by hardware
 469                          * ECC generator
 470                          */
 471                         LOG_DEBUG("part of spare block will be overrided "
 472                                   "by hardware ECC generator");
 473                 }
 474                 target_write_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size,     oob);
 475         }
 476
 477         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 478                 /* BI-swap - work-around of i.MX NFC for NAND device with page == 2kb*/
 479                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 480                 if (oob) {
 481                         LOG_ERROR("Due to NFC Bug, oob is not correctly implemented in mxc driver");
 482                         return ERROR_NAND_OPERATION_FAILED;
 483                 }
 484                 swap2 = 0xffff;  /* Spare buffer unused forced to 0xffff */
 485                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 486                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 487                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 488                 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
 489         }
 490
 491         /*
 492          * start data input operation (set MXC_NF_BIT_OP_DONE==0)
 493          */
 494         target_write_u16(target, MXC_NF_BUFADDR, 0);
 495         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 496         poll_result = poll_for_complete_op(nand, "data input");
 497         if (poll_result != ERROR_OK)
 498                 return poll_result;
 499
 500         target_write_u16(target, MXC_NF_BUFADDR, 1);
 501         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 502         poll_result = poll_for_complete_op(nand, "data input");
 503         if (poll_result != ERROR_OK)
 504                 return poll_result;
 505
 506         target_write_u16(target, MXC_NF_BUFADDR, 2);
 507         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 508         poll_result = poll_for_complete_op(nand, "data input");
 509         if (poll_result != ERROR_OK)
 510                 return poll_result;
 511
 512         target_write_u16(target, MXC_NF_BUFADDR, 3);
 513         target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_OP_FDI);
 514         poll_result = poll_for_complete_op(nand, "data input");
 515         if (poll_result != ERROR_OK)
 516                 return poll_result;
 517
 518         retval |= mxc_command(nand, NAND_CMD_PAGEPROG);
 519         if (retval != ERROR_OK)
 520                 return retval;
 521
 522         /*
 523          * check status register
 524          */
 525         retval = ERROR_OK;
 526         retval |= mxc_command(nand, NAND_CMD_STATUS);
 527         target_write_u16 (target, MXC_NF_BUFADDR, 0);
 528         mxc_nf_info->optype = MXC_NF_DATAOUT_NANDSTATUS;
 529         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 530         retval |= do_data_output(nand);
 531         if (retval != ERROR_OK) {
 532                 LOG_ERROR(get_status_register_err_msg);
 533                 return retval;
 534         }
 535         target_read_u16(target, MXC_NF_MAIN_BUFFER0, &nand_status_content);
 536         if (nand_status_content & 0x0001) {
 537                 /*
 538                  * page not correctly written
 539                  */
 540                 return ERROR_NAND_OPERATION_FAILED;
 541         }
 542 #ifdef _MXC_PRINT_STAT
 543         LOG_INFO("%d bytes newly written", data_size);
 544 #endif
 545         return ERROR_OK;
 546 }
 547
 548 static int mxc_read_page(struct nand_device *nand, uint32_t page,
 549                                                    uint8_t *data, uint32_t data_size,
 550                                                    uint8_t *oob, uint32_t oob_size)
 551 {
 552         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 553         struct target *target = nand->target;
 554         int retval;
 555         uint16_t swap1, swap2, new_swap1;
 556
 557         if (data_size % 2) {
 558                 LOG_ERROR(data_block_size_err_msg, data_size);
 559                 return ERROR_NAND_OPERATION_FAILED;
 560         }
 561         if (oob_size % 2) {
 562                 LOG_ERROR(data_block_size_err_msg, oob_size);
 563                 return ERROR_NAND_OPERATION_FAILED;
 564         }
 565
 566         /*
 567          * validate target state
 568          */
 569         retval = validate_target_state(nand);
 570         if (retval != ERROR_OK) {
 571                 return retval;
 572         }
 573         /* Reset address_cycles before mxc_command ?? */
 574         retval = mxc_command(nand, NAND_CMD_READ0);
 575         if (retval != ERROR_OK) return retval;
 576         retval = mxc_address(nand, 0); /* col */
 577         if (retval != ERROR_OK) return retval;
 578         retval = mxc_address(nand, 0); /* col */
 579         if (retval != ERROR_OK) return retval;
 580         retval = mxc_address(nand, page & 0xff); /* page address */
 581         if (retval != ERROR_OK) return retval;
 582         retval = mxc_address(nand, (page >> 8) & 0xff); /* page address */
 583         if (retval != ERROR_OK) return retval;
 584         retval = mxc_address(nand, (page >> 16) & 0xff); /* page address */
 585         if (retval != ERROR_OK) return retval;
 586         retval = mxc_command(nand, NAND_CMD_READSTART);
 587         if (retval != ERROR_OK) return retval;
 588
 589         target_write_u16(target, MXC_NF_BUFADDR, 0);
 590         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 591         retval = do_data_output(nand);
 592         if (retval != ERROR_OK) {
 593                 LOG_ERROR("MXC_NF : Error reading page 0");
 594                 return retval;
 595         }
 596         /* Test nand page size to know how much MAIN_BUFFER must be written */
 597         target_write_u16(target, MXC_NF_BUFADDR, 1);
 598         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 599         retval = do_data_output(nand);
 600         if (retval != ERROR_OK) {
 601                 LOG_ERROR("MXC_NF : Error reading page 1");
 602                 return retval;
 603         }
 604         target_write_u16(target, MXC_NF_BUFADDR, 2);
 605         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 606         retval = do_data_output(nand);
 607         if (retval != ERROR_OK) {
 608                 LOG_ERROR("MXC_NF : Error reading page 2");
 609                 return retval;
 610         }
 611         target_write_u16(target, MXC_NF_BUFADDR, 3);
 612         mxc_nf_info->fin = MXC_NF_FIN_DATAOUT;
 613         retval = do_data_output(nand);
 614         if (retval != ERROR_OK) {
 615                 LOG_ERROR("MXC_NF : Error reading page 3");
 616                 return retval;
 617         }
 618
 619         if (nand->page_size > 512 && mxc_nf_info->flags.biswap_enabled) {
 620                 /* BI-swap -  work-around of mxc NFC for NAND device with page == 2k */
 621                 target_read_u16(target, MXC_NF_MAIN_BUFFER3 + 464, &swap1);
 622                 target_read_u16(target, MXC_NF_SPARE_BUFFER3 + 4, &swap2);
 623                 new_swap1 = (swap1 & 0xFF00) | (swap2 >> 8);
 624                 swap2 = (swap1 << 8) | (swap2 & 0xFF);
 625                 target_write_u16(target, MXC_NF_MAIN_BUFFER3 + 464, new_swap1);
 626                 target_write_u16(target, MXC_NF_SPARE_BUFFER3 + 4, swap2);
 627         }
 628
 629         if (data)
 630                 target_read_buffer(target, MXC_NF_MAIN_BUFFER0, data_size, data);
 631         if (oob)
 632                 target_read_buffer(target, MXC_NF_SPARE_BUFFER0, oob_size, oob);
 633
 634 #ifdef _MXC_PRINT_STAT
 635         if (data_size > 0) {
 636                 /* When Operation Status is read (when page is erased),
 637                  * this function is used but data_size is null.
 638                  */
 639                 LOG_INFO("%d bytes newly read", data_size);
 640         }
 641 #endif
 642         return ERROR_OK;
 643 }
 644
 645 static int initialize_nf_controller(struct nand_device *nand)
 646 {
 647         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 648         struct target *target = nand->target;
 649         uint16_t work_mode;
 650         uint16_t temp;
 651         /*
 652          * resets NAND flash controller in zero time ? I dont know.
 653          */
 654         target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 655         work_mode = MXC_NF_BIT_INT_DIS; /* disable interrupt */
 656         if (target->endianness == TARGET_BIG_ENDIAN) {
 657                 LOG_DEBUG("MXC_NF : work in Big Endian mode");
 658                 work_mode |= MXC_NF_BIT_BE_EN;
 659         } else {
 660                 LOG_DEBUG("MXC_NF : work in Little Endian mode");
 661         }
 662         if (mxc_nf_info->flags.hw_ecc_enabled) {
 663                 LOG_DEBUG("MXC_NF : work with ECC mode");
 664                 work_mode |= MXC_NF_BIT_ECC_EN;
 665         } else {
 666                 LOG_DEBUG("MXC_NF : work without ECC mode");
 667         }
 668         target_write_u16(target, MXC_NF_CFG1, work_mode);
 669         /*
 670          * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
 671          */
 672         target_write_u16(target, MXC_NF_BUFCFG, 2);
 673         target_read_u16(target, MXC_NF_FWP, &temp);
 674         if ((temp & 0x0007) == 1) {
 675                 LOG_ERROR("NAND flash is tight-locked, reset needed");
 676                 return ERROR_FAIL;
 677         }
 678
 679         /*
 680          * unlock NAND flash for write
 681          */
 682         target_write_u16(target, MXC_NF_FWP, 4);
 683         target_write_u16(target, MXC_NF_LOCKSTART, 0x0000);
 684         target_write_u16(target, MXC_NF_LOCKEND, 0xFFFF);
 685         /*
 686          * 0x0000 means that first SRAM buffer @0xD800_0000 will be used
 687          */
 688         target_write_u16(target, MXC_NF_BUFADDR, 0x0000);
 689         /*
 690          * address of SRAM buffer
 691          */
 692         in_sram_address = MXC_NF_MAIN_BUFFER0;
 693         sign_of_sequental_byte_read = 0;
 694         return ERROR_OK;
 695 }
 696
 697 static int get_next_byte_from_sram_buffer(struct nand_device *nand, uint8_t *value)
 698 {
 699         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 700         struct target *target = nand->target;
 701         static uint8_t even_byte = 0;
 702         uint16_t temp;
 703         /*
 704          * host-big_endian ??
 705          */
 706         if (sign_of_sequental_byte_read == 0)
 707                 even_byte = 0;
 708
 709         if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
 710                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 711                 *value = 0;
 712                 sign_of_sequental_byte_read = 0;
 713                 even_byte = 0;
 714                 return ERROR_NAND_OPERATION_FAILED;
 715         } else {
 716                 target_read_u16(target, in_sram_address, &temp);
 717                 if (even_byte) {
 718                         *value = temp >> 8;
 719                         even_byte = 0;
 720                         in_sram_address += 2;
 721                 } else {
 722                         *value = temp & 0xff;
 723                         even_byte = 1;
 724                 }
 725         }
 726         sign_of_sequental_byte_read = 1;
 727         return ERROR_OK;
 728 }
 729
 730 static int get_next_halfword_from_sram_buffer(struct nand_device *nand, uint16_t *value)
 731 {
 732         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 733         struct target *target = nand->target;
 734
 735         if (in_sram_address > MXC_NF_LAST_BUFFER_ADDR) {
 736                 LOG_ERROR(sram_buffer_bounds_err_msg, in_sram_address);
 737                 *value = 0;
 738                 return ERROR_NAND_OPERATION_FAILED;
 739         } else {
 740                 target_read_u16(target, in_sram_address, value);
 741                 in_sram_address += 2;
 742         }
 743         return ERROR_OK;
 744 }
 745
 746 static int poll_for_complete_op(struct nand_device *nand, const char *text)
 747 {
 748         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 749         struct target *target = nand->target;
 750         uint16_t poll_complete_status;
 751
 752         for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++) {
 753                 target_read_u16(target, MXC_NF_CFG2, &poll_complete_status);
 754                 if (poll_complete_status & MXC_NF_BIT_OP_DONE)
 755                         break;
 756
 757                 usleep(10);
 758         }
 759         if (!(poll_complete_status & MXC_NF_BIT_OP_DONE)) {
 760                 LOG_ERROR("%s sending timeout", text);
 761                 return ERROR_NAND_OPERATION_FAILED;
 762         }
 763         return ERROR_OK;
 764 }
 765
 766 static int validate_target_state(struct nand_device *nand)
 767 {
 768         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 769         struct target *target = nand->target;
 770
 771         if (target->state != TARGET_HALTED) {
 772                 LOG_ERROR(target_not_halted_err_msg);
 773                 return ERROR_NAND_OPERATION_FAILED;
 774         }
 775
 776         if (mxc_nf_info->flags.target_little_endian !=
 777             (target->endianness == TARGET_LITTLE_ENDIAN)) {
 778                 /*
 779                  * endianness changed after NAND controller probed
 780                  */
 781                 return ERROR_NAND_OPERATION_FAILED;
 782         }
 783         return ERROR_OK;
 784 }
 785
 786 static int do_data_output(struct nand_device *nand)
 787 {
 788         struct mxc_nf_controller *mxc_nf_info = nand->controller_priv;
 789         struct target *target = nand->target;
 790         int poll_result;
 791         uint16_t ecc_status;
 792         switch (mxc_nf_info->fin) {
 793         case MXC_NF_FIN_DATAOUT:
 794                 /*
 795                  * start data output operation (set MXC_NF_BIT_OP_DONE==0)
 796                  */
 797                 target_write_u16(target, MXC_NF_CFG2, MXC_NF_BIT_DATAOUT_TYPE(mxc_nf_info->optype));
 798                 poll_result = poll_for_complete_op(nand, "data output");
 799                 if (poll_result != ERROR_OK)
 800                         return poll_result;
 801
 802                 mxc_nf_info->fin = MXC_NF_FIN_NONE;
 803                 /*
 804                  * ECC stuff
 805                  */
 806                 if ((mxc_nf_info->optype == MXC_NF_DATAOUT_PAGE) &&
 807                         mxc_nf_info->flags.hw_ecc_enabled) {
 808                         target_read_u16(target, MXC_NF_ECCSTATUS, &ecc_status);
 809                         switch (ecc_status & 0x000c) {
 810                         case 1 << 2:
 811                                 LOG_INFO("main area readed with 1 (correctable) error");
 812                                 break;
 813                         case 2 << 2:
 814                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 815                                 return ERROR_NAND_OPERATION_FAILED;
 816                                         break;
 817                         }
 818                         switch (ecc_status & 0x0003) {
 819                         case 1:
 820                                 LOG_INFO("spare area readed with 1 (correctable) error");
 821                                 break;
 822                         case 2:
 823                                 LOG_INFO("main area readed with more than 1 (incorrectable) error");
 824                                 return ERROR_NAND_OPERATION_FAILED;
 825                                 break;
 826                         }
 827                 }
 828                 break;
 829         case MXC_NF_FIN_NONE:
 830                 break;
 831         }
 832         return ERROR_OK;
 833 }
 834
 835 struct nand_flash_controller mxc_nand_flash_controller = {
 836         .name                                   = "mxc",
 837         .nand_device_command    = &mxc_nand_device_command,
 838         .commands                               = mxc_nand_command_handler,
 839         .init                                   = &mxc_init,
 840         .reset                                  = &mxc_reset,
 841         .command                                = &mxc_command,
 842         .address                                = &mxc_address,
 843         .write_data                             = &mxc_write_data,
 844         .read_data                              = &mxc_read_data,
 845         .write_page                             = &mxc_write_page,
 846         .read_page                              = &mxc_read_page,
 847         .nand_ready                             = &mxc_nand_ready,
 848 };