1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "time_support.h"
31 static int nand_read_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
32 //static int nand_read_plain(struct nand_device_s *nand, uint32_t address, uint8_t *data, uint32_t data_size);
34 static int nand_write_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
36 /* NAND flash controller
38 extern nand_flash_controller_t davinci_nand_controller;
39 extern nand_flash_controller_t lpc3180_nand_controller;
40 extern nand_flash_controller_t orion_nand_controller;
41 extern nand_flash_controller_t s3c2410_nand_controller;
42 extern nand_flash_controller_t s3c2412_nand_controller;
43 extern nand_flash_controller_t s3c2440_nand_controller;
44 extern nand_flash_controller_t s3c2443_nand_controller;
45 extern nand_flash_controller_t imx31_nand_flash_controller;
47 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
49 static nand_flash_controller_t *nand_flash_controllers[] =
51 &davinci_nand_controller,
52 &lpc3180_nand_controller,
53 &orion_nand_controller,
54 &s3c2410_nand_controller,
55 &s3c2412_nand_controller,
56 &s3c2440_nand_controller,
57 &s3c2443_nand_controller,
58 &imx31_nand_flash_controller,
59 /* &boundary_scan_nand_controller, */
63 /* configured NAND devices and NAND Flash command handler */
64 static nand_device_t *nand_devices = NULL;
65 static command_t *nand_cmd;
69 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
72 * Pagesize; 0, 256, 512
73 * 0 get this information from the extended chip ID
74 * 256 256 Byte page size
75 * 512 512 Byte page size
77 static nand_info_t nand_flash_ids[] =
79 /* start "museum" IDs */
80 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
81 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
82 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
83 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
84 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
85 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
86 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
87 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
88 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
89 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
91 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
92 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
93 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
94 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
95 /* end "museum" IDs */
97 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
98 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
99 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
100 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
102 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
103 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
104 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
105 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
107 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
108 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
109 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
112 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
113 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
114 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
115 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
116 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
117 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
118 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
122 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
123 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
124 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
125 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
127 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
128 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
129 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
130 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
132 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
133 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
134 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
135 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
137 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
138 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
139 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
140 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
142 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
143 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
144 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
145 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
147 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
148 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
149 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
150 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
152 {NULL, 0, 0, 0, 0, 0 }
155 /* Manufacturer ID list
157 static nand_manufacturer_t nand_manuf_ids[] =
160 {NAND_MFR_TOSHIBA, "Toshiba"},
161 {NAND_MFR_SAMSUNG, "Samsung"},
162 {NAND_MFR_FUJITSU, "Fujitsu"},
163 {NAND_MFR_NATIONAL, "National"},
164 {NAND_MFR_RENESAS, "Renesas"},
165 {NAND_MFR_STMICRO, "ST Micro"},
166 {NAND_MFR_HYNIX, "Hynix"},
167 {NAND_MFR_MICRON, "Micron"},
172 * Define default oob placement schemes for large and small page devices
176 static nand_ecclayout_t nand_oob_8 = {
187 static nand_ecclayout_t nand_oob_16 = {
189 .eccpos = {0, 1, 2, 3, 6, 7},
195 static nand_ecclayout_t nand_oob_64 = {
198 40, 41, 42, 43, 44, 45, 46, 47,
199 48, 49, 50, 51, 52, 53, 54, 55,
200 56, 57, 58, 59, 60, 61, 62, 63},
206 /* nand device <nand_controller> [controller options]
208 COMMAND_HANDLER(handle_nand_device_command)
215 LOG_WARNING("incomplete flash device nand configuration");
216 return ERROR_FLASH_BANK_INVALID;
219 for (i = 0; nand_flash_controllers[i]; i++)
221 nand_device_t *p, *c;
223 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
225 /* register flash specific commands */
226 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
228 LOG_ERROR("couldn't register '%s' commands", args[0]);
232 c = malloc(sizeof(nand_device_t));
234 c->controller = nand_flash_controllers[i];
235 c->controller_priv = NULL;
236 c->manufacturer = NULL;
239 c->address_cycles = 0;
244 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
246 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
251 /* put NAND device in linked list */
254 /* find last flash device */
255 for (p = nand_devices; p && p->next; p = p->next);
268 /* no valid NAND controller was found (i.e. the configuration option,
269 * didn't match one of the compiled-in controllers)
271 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
272 LOG_ERROR("compiled-in NAND flash controllers:");
273 for (i = 0; nand_flash_controllers[i]; i++)
275 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
281 int nand_register_commands(struct command_context_s *cmd_ctx)
283 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
285 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
290 nand_device_t *get_nand_device_by_num(int num)
295 for (p = nand_devices; p; p = p->next)
306 int nand_command_get_device_by_num(struct command_context_s *cmd_ctx,
307 const char *str, nand_device_t **nand)
310 COMMAND_PARSE_NUMBER(uint, str, num);
311 *nand = get_nand_device_by_num(num);
313 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", str);
314 return ERROR_INVALID_ARGUMENTS;
319 static int nand_build_bbt(struct nand_device_s *nand, int first, int last)
325 if ((first < 0) || (first >= nand->num_blocks))
328 if ((last >= nand->num_blocks) || (last == -1))
329 last = nand->num_blocks - 1;
331 for (i = first; i < last; i++)
333 nand_read_page(nand, page, NULL, 0, oob, 6);
335 if (((nand->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
336 || (((nand->page_size == 512) && (oob[5] != 0xff)) ||
337 ((nand->page_size == 2048) && (oob[0] != 0xff))))
339 LOG_WARNING("bad block: %i", i);
340 nand->blocks[i].is_bad = 1;
344 nand->blocks[i].is_bad = 0;
347 page += (nand->erase_size / nand->page_size);
353 int nand_read_status(struct nand_device_s *nand, uint8_t *status)
356 return ERROR_NAND_DEVICE_NOT_PROBED;
358 /* Send read status command */
359 nand->controller->command(nand, NAND_CMD_STATUS);
364 if (nand->device->options & NAND_BUSWIDTH_16)
367 nand->controller->read_data(nand, &data);
368 *status = data & 0xff;
372 nand->controller->read_data(nand, status);
378 static int nand_poll_ready(struct nand_device_s *nand, int timeout)
382 nand->controller->command(nand, NAND_CMD_STATUS);
384 if (nand->device->options & NAND_BUSWIDTH_16) {
386 nand->controller->read_data(nand, &data);
387 status = data & 0xff;
389 nand->controller->read_data(nand, &status);
391 if (status & NAND_STATUS_READY)
396 return (status & NAND_STATUS_READY) != 0;
399 int nand_probe(struct nand_device_s *nand)
401 uint8_t manufacturer_id, device_id;
406 /* clear device data */
408 nand->manufacturer = NULL;
410 /* clear device parameters */
412 nand->address_cycles = 0;
414 nand->erase_size = 0;
416 /* initialize controller (device parameters are zero, use controller default) */
417 if ((retval = nand->controller->init(nand) != ERROR_OK))
421 case ERROR_NAND_OPERATION_FAILED:
422 LOG_DEBUG("controller initialization failed");
423 return ERROR_NAND_OPERATION_FAILED;
424 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
425 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
426 return ERROR_NAND_OPERATION_FAILED;
428 LOG_ERROR("BUG: unknown controller initialization failure");
429 return ERROR_NAND_OPERATION_FAILED;
433 nand->controller->command(nand, NAND_CMD_RESET);
434 nand->controller->reset(nand);
436 nand->controller->command(nand, NAND_CMD_READID);
437 nand->controller->address(nand, 0x0);
439 if (nand->bus_width == 8)
441 nand->controller->read_data(nand, &manufacturer_id);
442 nand->controller->read_data(nand, &device_id);
447 nand->controller->read_data(nand, &data_buf);
448 manufacturer_id = data_buf & 0xff;
449 nand->controller->read_data(nand, &data_buf);
450 device_id = data_buf & 0xff;
453 for (i = 0; nand_flash_ids[i].name; i++)
455 if (nand_flash_ids[i].id == device_id)
457 nand->device = &nand_flash_ids[i];
462 for (i = 0; nand_manuf_ids[i].name; i++)
464 if (nand_manuf_ids[i].id == manufacturer_id)
466 nand->manufacturer = &nand_manuf_ids[i];
471 if (!nand->manufacturer)
473 nand->manufacturer = &nand_manuf_ids[0];
474 nand->manufacturer->id = manufacturer_id;
479 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
480 manufacturer_id, device_id);
481 return ERROR_NAND_OPERATION_FAILED;
484 LOG_DEBUG("found %s (%s)", nand->device->name, nand->manufacturer->name);
486 /* initialize device parameters */
489 if (nand->device->options & NAND_BUSWIDTH_16)
490 nand->bus_width = 16;
494 /* Do we need extended device probe information? */
495 if (nand->device->page_size == 0 ||
496 nand->device->erase_size == 0)
498 if (nand->bus_width == 8)
500 nand->controller->read_data(nand, id_buff + 3);
501 nand->controller->read_data(nand, id_buff + 4);
502 nand->controller->read_data(nand, id_buff + 5);
508 nand->controller->read_data(nand, &data_buf);
509 id_buff[3] = data_buf;
511 nand->controller->read_data(nand, &data_buf);
512 id_buff[4] = data_buf;
514 nand->controller->read_data(nand, &data_buf);
515 id_buff[5] = data_buf >> 8;
520 if (nand->device->page_size == 0)
522 nand->page_size = 1 << (10 + (id_buff[4] & 3));
524 else if (nand->device->page_size == 256)
526 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
527 return ERROR_NAND_OPERATION_FAILED;
531 nand->page_size = nand->device->page_size;
534 /* number of address cycles */
535 if (nand->page_size <= 512)
537 /* small page devices */
538 if (nand->device->chip_size <= 32)
539 nand->address_cycles = 3;
540 else if (nand->device->chip_size <= 8*1024)
541 nand->address_cycles = 4;
544 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
545 nand->address_cycles = 5;
550 /* large page devices */
551 if (nand->device->chip_size <= 128)
552 nand->address_cycles = 4;
553 else if (nand->device->chip_size <= 32*1024)
554 nand->address_cycles = 5;
557 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
558 nand->address_cycles = 6;
563 if (nand->device->erase_size == 0)
565 switch ((id_buff[4] >> 4) & 3) {
567 nand->erase_size = 64 << 10;
570 nand->erase_size = 128 << 10;
573 nand->erase_size = 256 << 10;
576 nand->erase_size =512 << 10;
582 nand->erase_size = nand->device->erase_size;
585 /* initialize controller, but leave parameters at the controllers default */
586 if ((retval = nand->controller->init(nand) != ERROR_OK))
590 case ERROR_NAND_OPERATION_FAILED:
591 LOG_DEBUG("controller initialization failed");
592 return ERROR_NAND_OPERATION_FAILED;
593 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
594 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
595 nand->bus_width, nand->address_cycles, nand->page_size);
596 return ERROR_NAND_OPERATION_FAILED;
598 LOG_ERROR("BUG: unknown controller initialization failure");
599 return ERROR_NAND_OPERATION_FAILED;
603 nand->num_blocks = (nand->device->chip_size * 1024) / (nand->erase_size / 1024);
604 nand->blocks = malloc(sizeof(nand_block_t) * nand->num_blocks);
606 for (i = 0; i < nand->num_blocks; i++)
608 nand->blocks[i].size = nand->erase_size;
609 nand->blocks[i].offset = i * nand->erase_size;
610 nand->blocks[i].is_erased = -1;
611 nand->blocks[i].is_bad = -1;
617 static int nand_erase(struct nand_device_s *nand, int first_block, int last_block)
625 return ERROR_NAND_DEVICE_NOT_PROBED;
627 if ((first_block < 0) || (last_block > nand->num_blocks))
628 return ERROR_INVALID_ARGUMENTS;
630 /* make sure we know if a block is bad before erasing it */
631 for (i = first_block; i <= last_block; i++)
633 if (nand->blocks[i].is_bad == -1)
635 nand_build_bbt(nand, i, last_block);
640 for (i = first_block; i <= last_block; i++)
642 /* Send erase setup command */
643 nand->controller->command(nand, NAND_CMD_ERASE1);
645 page = i * (nand->erase_size / nand->page_size);
647 /* Send page address */
648 if (nand->page_size <= 512)
651 nand->controller->address(nand, page & 0xff);
652 nand->controller->address(nand, (page >> 8) & 0xff);
654 /* 3rd cycle only on devices with more than 32 MiB */
655 if (nand->address_cycles >= 4)
656 nand->controller->address(nand, (page >> 16) & 0xff);
658 /* 4th cycle only on devices with more than 8 GiB */
659 if (nand->address_cycles >= 5)
660 nand->controller->address(nand, (page >> 24) & 0xff);
665 nand->controller->address(nand, page & 0xff);
666 nand->controller->address(nand, (page >> 8) & 0xff);
668 /* 3rd cycle only on devices with more than 128 MiB */
669 if (nand->address_cycles >= 5)
670 nand->controller->address(nand, (page >> 16) & 0xff);
673 /* Send erase confirm command */
674 nand->controller->command(nand, NAND_CMD_ERASE2);
676 retval = nand->controller->nand_ready ?
677 nand->controller->nand_ready(nand, 1000) :
678 nand_poll_ready(nand, 1000);
680 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
681 return ERROR_NAND_OPERATION_TIMEOUT;
684 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
686 LOG_ERROR("couldn't read status");
687 return ERROR_NAND_OPERATION_FAILED;
692 LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
693 (nand->blocks[i].is_bad == 1)
696 /* continue; other blocks might still be erasable */
699 nand->blocks[i].is_erased = 1;
706 static int nand_read_plain(struct nand_device_s *nand, uint32_t address, uint8_t *data, uint32_t data_size)
711 return ERROR_NAND_DEVICE_NOT_PROBED;
713 if (address % nand->page_size)
715 LOG_ERROR("reads need to be page aligned");
716 return ERROR_NAND_OPERATION_FAILED;
719 page = malloc(nand->page_size);
721 while (data_size > 0)
723 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
724 uint32_t page_address;
727 page_address = address / nand->page_size;
729 nand_read_page(nand, page_address, page, nand->page_size, NULL, 0);
731 memcpy(data, page, thisrun_size);
733 address += thisrun_size;
734 data += thisrun_size;
735 data_size -= thisrun_size;
743 static int nand_write_plain(struct nand_device_s *nand, uint32_t address, uint8_t *data, uint32_t data_size)
748 return ERROR_NAND_DEVICE_NOT_PROBED;
750 if (address % nand->page_size)
752 LOG_ERROR("writes need to be page aligned");
753 return ERROR_NAND_OPERATION_FAILED;
756 page = malloc(nand->page_size);
758 while (data_size > 0)
760 uint32_t thisrun_size = (data_size > nand->page_size) ? nand->page_size : data_size;
761 uint32_t page_address;
763 memset(page, 0xff, nand->page_size);
764 memcpy(page, data, thisrun_size);
766 page_address = address / nand->page_size;
768 nand_write_page(nand, page_address, page, nand->page_size, NULL, 0);
770 address += thisrun_size;
771 data += thisrun_size;
772 data_size -= thisrun_size;
781 int nand_write_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
786 return ERROR_NAND_DEVICE_NOT_PROBED;
788 block = page / (nand->erase_size / nand->page_size);
789 if (nand->blocks[block].is_erased == 1)
790 nand->blocks[block].is_erased = 0;
792 if (nand->use_raw || nand->controller->write_page == NULL)
793 return nand_write_page_raw(nand, page, data, data_size, oob, oob_size);
795 return nand->controller->write_page(nand, page, data, data_size, oob, oob_size);
798 static int nand_read_page(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
801 return ERROR_NAND_DEVICE_NOT_PROBED;
803 if (nand->use_raw || nand->controller->read_page == NULL)
804 return nand_read_page_raw(nand, page, data, data_size, oob, oob_size);
806 return nand->controller->read_page(nand, page, data, data_size, oob, oob_size);
809 int nand_read_page_raw(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
814 return ERROR_NAND_DEVICE_NOT_PROBED;
816 if (nand->page_size <= 512)
818 /* small page device */
820 nand->controller->command(nand, NAND_CMD_READ0);
822 nand->controller->command(nand, NAND_CMD_READOOB);
824 /* column (always 0, we start at the beginning of a page/OOB area) */
825 nand->controller->address(nand, 0x0);
828 nand->controller->address(nand, page & 0xff);
829 nand->controller->address(nand, (page >> 8) & 0xff);
831 /* 4th cycle only on devices with more than 32 MiB */
832 if (nand->address_cycles >= 4)
833 nand->controller->address(nand, (page >> 16) & 0xff);
835 /* 5th cycle only on devices with more than 8 GiB */
836 if (nand->address_cycles >= 5)
837 nand->controller->address(nand, (page >> 24) & 0xff);
841 /* large page device */
842 nand->controller->command(nand, NAND_CMD_READ0);
844 /* column (0 when we start at the beginning of a page,
845 * or 2048 for the beginning of OOB area)
847 nand->controller->address(nand, 0x0);
849 nand->controller->address(nand, 0x0);
851 nand->controller->address(nand, 0x8);
854 nand->controller->address(nand, page & 0xff);
855 nand->controller->address(nand, (page >> 8) & 0xff);
857 /* 5th cycle only on devices with more than 128 MiB */
858 if (nand->address_cycles >= 5)
859 nand->controller->address(nand, (page >> 16) & 0xff);
861 /* large page devices need a start command */
862 nand->controller->command(nand, NAND_CMD_READSTART);
865 if (nand->controller->nand_ready) {
866 if (!nand->controller->nand_ready(nand, 100))
867 return ERROR_NAND_OPERATION_TIMEOUT;
874 if (nand->controller->read_block_data != NULL)
875 (nand->controller->read_block_data)(nand, data, data_size);
878 for (i = 0; i < data_size;)
880 if (nand->device->options & NAND_BUSWIDTH_16)
882 nand->controller->read_data(nand, data);
888 nand->controller->read_data(nand, data);
898 if (nand->controller->read_block_data != NULL)
899 (nand->controller->read_block_data)(nand, oob, oob_size);
902 for (i = 0; i < oob_size;)
904 if (nand->device->options & NAND_BUSWIDTH_16)
906 nand->controller->read_data(nand, oob);
912 nand->controller->read_data(nand, oob);
923 int nand_write_page_raw(struct nand_device_s *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
930 return ERROR_NAND_DEVICE_NOT_PROBED;
932 nand->controller->command(nand, NAND_CMD_SEQIN);
934 if (nand->page_size <= 512)
936 /* column (always 0, we start at the beginning of a page/OOB area) */
937 nand->controller->address(nand, 0x0);
940 nand->controller->address(nand, page & 0xff);
941 nand->controller->address(nand, (page >> 8) & 0xff);
943 /* 4th cycle only on devices with more than 32 MiB */
944 if (nand->address_cycles >= 4)
945 nand->controller->address(nand, (page >> 16) & 0xff);
947 /* 5th cycle only on devices with more than 8 GiB */
948 if (nand->address_cycles >= 5)
949 nand->controller->address(nand, (page >> 24) & 0xff);
953 /* column (0 when we start at the beginning of a page,
954 * or 2048 for the beginning of OOB area)
956 nand->controller->address(nand, 0x0);
958 nand->controller->address(nand, 0x0);
960 nand->controller->address(nand, 0x8);
963 nand->controller->address(nand, page & 0xff);
964 nand->controller->address(nand, (page >> 8) & 0xff);
966 /* 5th cycle only on devices with more than 128 MiB */
967 if (nand->address_cycles >= 5)
968 nand->controller->address(nand, (page >> 16) & 0xff);
973 if (nand->controller->write_block_data != NULL)
974 (nand->controller->write_block_data)(nand, data, data_size);
977 for (i = 0; i < data_size;)
979 if (nand->device->options & NAND_BUSWIDTH_16)
981 uint16_t data_buf = le_to_h_u16(data);
982 nand->controller->write_data(nand, data_buf);
988 nand->controller->write_data(nand, *data);
998 if (nand->controller->write_block_data != NULL)
999 (nand->controller->write_block_data)(nand, oob, oob_size);
1002 for (i = 0; i < oob_size;)
1004 if (nand->device->options & NAND_BUSWIDTH_16)
1006 uint16_t oob_buf = le_to_h_u16(data);
1007 nand->controller->write_data(nand, oob_buf);
1013 nand->controller->write_data(nand, *oob);
1021 nand->controller->command(nand, NAND_CMD_PAGEPROG);
1023 retval = nand->controller->nand_ready ?
1024 nand->controller->nand_ready(nand, 100) :
1025 nand_poll_ready(nand, 100);
1027 return ERROR_NAND_OPERATION_TIMEOUT;
1029 if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
1031 LOG_ERROR("couldn't read status");
1032 return ERROR_NAND_OPERATION_FAILED;
1035 if (status & NAND_STATUS_FAIL)
1037 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1038 return ERROR_NAND_OPERATION_FAILED;
1044 COMMAND_HANDLER(handle_nand_list_command)
1051 command_print(cmd_ctx, "no NAND flash devices configured");
1055 for (p = nand_devices, i = 0; p; p = p->next, i++)
1058 command_print(cmd_ctx, "#%i: %s (%s) "
1059 "pagesize: %i, buswidth: %i,\n\t"
1060 "blocksize: %i, blocks: %i",
1061 i, p->device->name, p->manufacturer->name,
1062 p->page_size, p->bus_width,
1063 p->erase_size, p->num_blocks);
1065 command_print(cmd_ctx, "#%i: not probed", i);
1071 COMMAND_HANDLER(handle_nand_info_command)
1079 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1080 if (ERROR_OK != retval)
1085 return ERROR_COMMAND_SYNTAX_ERROR;
1091 COMMAND_PARSE_NUMBER(int, args[1], i);
1096 COMMAND_PARSE_NUMBER(int, args[1], first);
1097 COMMAND_PARSE_NUMBER(int, args[2], last);
1101 if (NULL == p->device)
1103 command_print(cmd_ctx, "#%s: not probed", args[0]);
1107 if (first >= p->num_blocks)
1108 first = p->num_blocks - 1;
1110 if (last >= p->num_blocks)
1111 last = p->num_blocks - 1;
1113 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1114 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1116 for (j = first; j <= last; j++)
1118 char *erase_state, *bad_state;
1120 if (p->blocks[j].is_erased == 0)
1121 erase_state = "not erased";
1122 else if (p->blocks[j].is_erased == 1)
1123 erase_state = "erased";
1125 erase_state = "erase state unknown";
1127 if (p->blocks[j].is_bad == 0)
1129 else if (p->blocks[j].is_bad == 1)
1130 bad_state = " (marked bad)";
1132 bad_state = " (block condition unknown)";
1134 command_print(cmd_ctx,
1135 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1137 p->blocks[j].offset,
1138 p->blocks[j].size / 1024,
1146 COMMAND_HANDLER(handle_nand_probe_command)
1150 return ERROR_COMMAND_SYNTAX_ERROR;
1154 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1155 if (ERROR_OK != retval)
1158 if ((retval = nand_probe(p)) == ERROR_OK)
1160 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1162 else if (retval == ERROR_NAND_OPERATION_FAILED)
1164 command_print(cmd_ctx, "probing failed for NAND flash device");
1168 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1174 COMMAND_HANDLER(handle_nand_erase_command)
1176 if (argc != 1 && argc != 3)
1178 return ERROR_COMMAND_SYNTAX_ERROR;
1183 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1184 if (ERROR_OK != retval)
1187 unsigned long offset;
1188 unsigned long length;
1190 /* erase specified part of the chip; or else everything */
1192 unsigned long size = p->erase_size * p->num_blocks;
1194 COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1195 if ((offset % p->erase_size) != 0 || offset >= size)
1196 return ERROR_INVALID_ARGUMENTS;
1198 COMMAND_PARSE_NUMBER(ulong, args[2], length);
1199 if ((length == 0) || (length % p->erase_size) != 0
1200 || (length + offset) > size)
1201 return ERROR_INVALID_ARGUMENTS;
1203 offset /= p->erase_size;
1204 length /= p->erase_size;
1207 length = p->num_blocks;
1210 retval = nand_erase(p, offset, offset + length - 1);
1211 if (retval == ERROR_OK)
1213 command_print(cmd_ctx, "erased blocks %lu to %lu "
1214 "on NAND flash device #%s '%s'",
1215 offset, offset + length,
1216 args[0], p->device->name);
1218 else if (retval == ERROR_NAND_OPERATION_FAILED)
1220 command_print(cmd_ctx, "erase failed");
1224 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1230 COMMAND_HANDLER(handle_nand_check_bad_blocks_command)
1235 if ((argc < 1) || (argc > 3) || (argc == 2))
1237 return ERROR_COMMAND_SYNTAX_ERROR;
1242 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1243 if (ERROR_OK != retval)
1248 unsigned long offset;
1249 unsigned long length;
1251 COMMAND_PARSE_NUMBER(ulong, args[1], offset);
1252 if (offset % p->erase_size)
1253 return ERROR_INVALID_ARGUMENTS;
1254 offset /= p->erase_size;
1256 COMMAND_PARSE_NUMBER(ulong, args[2], length);
1257 if (length % p->erase_size)
1258 return ERROR_INVALID_ARGUMENTS;
1261 length /= p->erase_size;
1264 last = offset + length;
1267 retval = nand_build_bbt(p, first, last);
1268 if (retval == ERROR_OK)
1270 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1271 "use \"nand info\" command to list blocks");
1273 else if (retval == ERROR_NAND_OPERATION_FAILED)
1275 command_print(cmd_ctx, "error when checking for bad blocks on "
1276 "NAND flash device");
1280 command_print(cmd_ctx, "unknown error when checking for bad "
1281 "blocks on NAND flash device");
1287 COMMAND_HANDLER(handle_nand_write_command)
1290 uint32_t binary_size;
1292 enum oob_formats oob_format = NAND_OOB_NONE;
1299 return ERROR_COMMAND_SYNTAX_ERROR;
1303 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1304 if (ERROR_OK != retval)
1307 uint8_t *page = NULL;
1308 uint32_t page_size = 0;
1309 uint8_t *oob = NULL;
1310 uint32_t oob_size = 0;
1311 const int *eccpos = NULL;
1313 COMMAND_PARSE_NUMBER(u32, args[2], offset);
1318 for (i = 3; i < argc; i++)
1320 if (!strcmp(args[i], "oob_raw"))
1321 oob_format |= NAND_OOB_RAW;
1322 else if (!strcmp(args[i], "oob_only"))
1323 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1324 else if (!strcmp(args[i], "oob_softecc"))
1325 oob_format |= NAND_OOB_SW_ECC;
1326 else if (!strcmp(args[i], "oob_softecc_kw"))
1327 oob_format |= NAND_OOB_SW_ECC_KW;
1330 command_print(cmd_ctx, "unknown option: %s", args[i]);
1331 return ERROR_COMMAND_SYNTAX_ERROR;
1336 struct duration bench;
1337 duration_start(&bench);
1339 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1344 buf_cnt = binary_size = fileio.size;
1346 if (!(oob_format & NAND_OOB_ONLY))
1348 page_size = p->page_size;
1349 page = malloc(p->page_size);
1352 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1354 if (p->page_size == 512) {
1356 eccpos = nand_oob_16.eccpos;
1357 } else if (p->page_size == 2048) {
1359 eccpos = nand_oob_64.eccpos;
1361 oob = malloc(oob_size);
1364 if (offset % p->page_size)
1366 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1367 fileio_close(&fileio);
1379 fileio_read(&fileio, page_size, page, &size_read);
1380 buf_cnt -= size_read;
1381 if (size_read < page_size)
1383 memset(page + size_read, 0xff, page_size - size_read);
1387 if (oob_format & NAND_OOB_SW_ECC)
1391 memset(oob, 0xff, oob_size);
1392 for (i = 0, j = 0; i < page_size; i += 256) {
1393 nand_calculate_ecc(p, page + i, ecc);
1394 oob[eccpos[j++]] = ecc[0];
1395 oob[eccpos[j++]] = ecc[1];
1396 oob[eccpos[j++]] = ecc[2];
1398 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1401 * In this case eccpos is not used as
1402 * the ECC data is always stored contigously
1403 * at the end of the OOB area. It consists
1404 * of 10 bytes per 512-byte data block.
1407 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1408 memset(oob, 0xff, oob_size);
1409 for (i = 0; i < page_size; i += 512) {
1410 nand_calculate_ecc_kw(p, page + i, ecc);
1414 else if (NULL != oob)
1416 fileio_read(&fileio, oob_size, oob, &size_read);
1417 buf_cnt -= size_read;
1418 if (size_read < oob_size)
1420 memset(oob + size_read, 0xff, oob_size - size_read);
1424 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1426 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8" PRIx32 "",
1427 args[1], args[0], offset);
1429 fileio_close(&fileio);
1435 offset += page_size;
1438 fileio_close(&fileio);
1443 if (duration_measure(&bench) == ERROR_OK)
1445 command_print(cmd_ctx, "wrote file %s to NAND flash %s "
1446 "up to offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
1447 args[1], args[0], offset, duration_elapsed(&bench),
1448 duration_kbps(&bench, fileio.size));
1454 COMMAND_HANDLER(handle_nand_dump_command)
1458 return ERROR_COMMAND_SYNTAX_ERROR;
1462 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1463 if (ERROR_OK != retval)
1466 if (NULL == p->device)
1468 command_print(cmd_ctx, "#%s: not probed", args[0]);
1474 uint8_t *page = NULL;
1475 uint32_t page_size = 0;
1476 uint8_t *oob = NULL;
1477 uint32_t oob_size = 0;
1479 COMMAND_PARSE_NUMBER(u32, args[2], address);
1481 COMMAND_PARSE_NUMBER(u32, args[3], size);
1482 uint32_t bytes_done = 0;
1483 enum oob_formats oob_format = NAND_OOB_NONE;
1488 for (i = 4; i < argc; i++)
1490 if (!strcmp(args[i], "oob_raw"))
1491 oob_format |= NAND_OOB_RAW;
1492 else if (!strcmp(args[i], "oob_only"))
1493 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1495 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1499 if ((address % p->page_size) || (size % p->page_size))
1501 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1505 if (!(oob_format & NAND_OOB_ONLY))
1507 page_size = p->page_size;
1508 page = malloc(p->page_size);
1511 if (oob_format & NAND_OOB_RAW)
1513 if (p->page_size == 512)
1515 else if (p->page_size == 2048)
1517 oob = malloc(oob_size);
1520 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1525 struct duration bench;
1526 duration_start(&bench);
1530 uint32_t size_written;
1531 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1533 command_print(cmd_ctx, "reading NAND flash page failed");
1536 fileio_close(&fileio);
1542 fileio_write(&fileio, page_size, page, &size_written);
1543 bytes_done += page_size;
1548 fileio_write(&fileio, oob_size, oob, &size_written);
1549 bytes_done += oob_size;
1552 size -= p->page_size;
1553 address += p->page_size;
1560 fileio_close(&fileio);
1562 if (duration_measure(&bench) == ERROR_OK)
1564 command_print(cmd_ctx, "dumped %lld byte in %fs (%0.3f kb/s)",
1565 fileio.size, duration_elapsed(&bench),
1566 duration_kbps(&bench, fileio.size));
1572 COMMAND_HANDLER(handle_nand_raw_access_command)
1574 if ((argc < 1) || (argc > 2))
1576 return ERROR_COMMAND_SYNTAX_ERROR;
1580 int retval = nand_command_get_device_by_num(cmd_ctx, args[0], &p);
1581 if (ERROR_OK != retval)
1584 if (NULL == p->device)
1586 command_print(cmd_ctx, "#%s: not probed", args[0]);
1592 if (strcmp("enable", args[1]) == 0)
1594 else if (strcmp("disable", args[1]) == 0)
1597 return ERROR_COMMAND_SYNTAX_ERROR;
1600 const char *msg = p->use_raw ? "enabled" : "disabled";
1601 command_print(cmd_ctx, "raw access is %s", msg);
1606 int nand_init(struct command_context_s *cmd_ctx)
1611 register_command(cmd_ctx, nand_cmd, "list",
1612 handle_nand_list_command, COMMAND_EXEC,
1613 "list configured NAND flash devices");
1614 register_command(cmd_ctx, nand_cmd, "info",
1615 handle_nand_info_command, COMMAND_EXEC,
1616 "print info about NAND flash device <num>");
1617 register_command(cmd_ctx, nand_cmd, "probe",
1618 handle_nand_probe_command, COMMAND_EXEC,
1619 "identify NAND flash device <num>");
1621 register_command(cmd_ctx, nand_cmd, "check_bad_blocks",
1622 handle_nand_check_bad_blocks_command, COMMAND_EXEC,
1623 "check NAND flash device <num> for bad blocks [<offset> <length>]");
1624 register_command(cmd_ctx, nand_cmd, "erase",
1625 handle_nand_erase_command, COMMAND_EXEC,
1626 "erase blocks on NAND flash device <num> [<offset> <length>]");
1627 register_command(cmd_ctx, nand_cmd, "dump",
1628 handle_nand_dump_command, COMMAND_EXEC,
1629 "dump from NAND flash device <num> <filename> "
1630 "<offset> <length> [oob_raw | oob_only]");
1631 register_command(cmd_ctx, nand_cmd, "write",
1632 handle_nand_write_command, COMMAND_EXEC,
1633 "write to NAND flash device <num> <filename> <offset> "
1634 "[oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
1636 register_command(cmd_ctx, nand_cmd, "raw_access",
1637 handle_nand_raw_access_command, COMMAND_EXEC,
1638 "raw access to NAND flash device <num> ['enable'|'disable']");