1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
28 #include "time_support.h"
31 static int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
32 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
33 static int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
34 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
35 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
36 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
37 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
39 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
41 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
42 //static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size);
44 static int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
46 /* NAND flash controller
48 extern nand_flash_controller_t davinci_nand_controller;
49 extern nand_flash_controller_t lpc3180_nand_controller;
50 extern nand_flash_controller_t orion_nand_controller;
51 extern nand_flash_controller_t s3c2410_nand_controller;
52 extern nand_flash_controller_t s3c2412_nand_controller;
53 extern nand_flash_controller_t s3c2440_nand_controller;
54 extern nand_flash_controller_t s3c2443_nand_controller;
55 extern nand_flash_controller_t imx31_nand_flash_controller;
57 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
59 static nand_flash_controller_t *nand_flash_controllers[] =
61 &davinci_nand_controller,
62 &lpc3180_nand_controller,
63 &orion_nand_controller,
64 &s3c2410_nand_controller,
65 &s3c2412_nand_controller,
66 &s3c2440_nand_controller,
67 &s3c2443_nand_controller,
68 &imx31_nand_flash_controller,
69 /* &boundary_scan_nand_controller, */
73 /* configured NAND devices and NAND Flash command handler */
74 static nand_device_t *nand_devices = NULL;
75 static command_t *nand_cmd;
79 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
82 * Pagesize; 0, 256, 512
83 * 0 get this information from the extended chip ID
84 * 256 256 Byte page size
85 * 512 512 Byte page size
87 static nand_info_t nand_flash_ids[] =
89 /* start "museum" IDs */
90 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
91 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
92 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
93 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
94 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
95 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
96 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
97 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
98 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
99 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
101 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
102 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
103 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
104 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
105 /* end "museum" IDs */
107 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
108 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
109 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
110 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
112 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
113 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
114 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
115 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
117 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
118 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
119 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
120 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
122 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
123 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
124 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
125 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
127 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
128 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
130 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
132 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
133 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
134 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
135 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
137 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
138 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
139 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
140 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
142 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
143 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
144 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
145 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
147 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
148 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
149 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
150 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
152 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
153 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
154 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
155 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
157 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
158 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
159 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
160 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
162 {NULL, 0, 0, 0, 0, 0 }
165 /* Manufacturer ID list
167 static nand_manufacturer_t nand_manuf_ids[] =
170 {NAND_MFR_TOSHIBA, "Toshiba"},
171 {NAND_MFR_SAMSUNG, "Samsung"},
172 {NAND_MFR_FUJITSU, "Fujitsu"},
173 {NAND_MFR_NATIONAL, "National"},
174 {NAND_MFR_RENESAS, "Renesas"},
175 {NAND_MFR_STMICRO, "ST Micro"},
176 {NAND_MFR_HYNIX, "Hynix"},
177 {NAND_MFR_MICRON, "Micron"},
182 * Define default oob placement schemes for large and small page devices
186 static nand_ecclayout_t nand_oob_8 = {
197 static nand_ecclayout_t nand_oob_16 = {
199 .eccpos = {0, 1, 2, 3, 6, 7},
205 static nand_ecclayout_t nand_oob_64 = {
208 40, 41, 42, 43, 44, 45, 46, 47,
209 48, 49, 50, 51, 52, 53, 54, 55,
210 56, 57, 58, 59, 60, 61, 62, 63},
216 /* nand device <nand_controller> [controller options]
218 static int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
225 LOG_WARNING("incomplete flash device nand configuration");
226 return ERROR_FLASH_BANK_INVALID;
229 for (i = 0; nand_flash_controllers[i]; i++)
231 nand_device_t *p, *c;
233 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
235 /* register flash specific commands */
236 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
238 LOG_ERROR("couldn't register '%s' commands", args[0]);
242 c = malloc(sizeof(nand_device_t));
244 c->controller = nand_flash_controllers[i];
245 c->controller_priv = NULL;
246 c->manufacturer = NULL;
249 c->address_cycles = 0;
254 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
256 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
261 /* put NAND device in linked list */
264 /* find last flash device */
265 for (p = nand_devices; p && p->next; p = p->next);
278 /* no valid NAND controller was found (i.e. the configuration option,
279 * didn't match one of the compiled-in controllers)
281 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
282 LOG_ERROR("compiled-in NAND flash controllers:");
283 for (i = 0; nand_flash_controllers[i]; i++)
285 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
291 int nand_register_commands(struct command_context_s *cmd_ctx)
293 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
295 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
300 int nand_init(struct command_context_s *cmd_ctx)
304 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
305 "list configured NAND flash devices");
306 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
307 "print info about NAND flash device <num>");
308 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
309 "identify NAND flash device <num>");
310 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
311 "check NAND flash device <num> for bad blocks [<offset> <length>]");
312 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
313 "erase blocks on NAND flash device <num> <offset> <length>");
314 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
315 "dump from NAND flash device <num> <filename> "
316 "<offset> <length> [oob_raw | oob_only]");
317 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
318 "write to NAND flash device <num> <filename> <offset> [oob_raw | oob_only | oob_softecc | oob_softecc_kw]");
319 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
320 "raw access to NAND flash device <num> ['enable'|'disable']");
326 nand_device_t *get_nand_device_by_num(int num)
331 for (p = nand_devices; p; p = p->next)
342 static int nand_build_bbt(struct nand_device_s *device, int first, int last)
348 if ((first < 0) || (first >= device->num_blocks))
351 if ((last >= device->num_blocks) || (last == -1))
352 last = device->num_blocks - 1;
354 for (i = first; i < last; i++)
356 nand_read_page(device, page, NULL, 0, oob, 6);
358 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
359 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
360 ((device->page_size == 2048) && (oob[0] != 0xff))))
362 LOG_WARNING("bad block: %i", i);
363 device->blocks[i].is_bad = 1;
367 device->blocks[i].is_bad = 0;
370 page += (device->erase_size / device->page_size);
376 int nand_read_status(struct nand_device_s *device, uint8_t *status)
379 return ERROR_NAND_DEVICE_NOT_PROBED;
381 /* Send read status command */
382 device->controller->command(device, NAND_CMD_STATUS);
387 if (device->device->options & NAND_BUSWIDTH_16)
390 device->controller->read_data(device, &data);
391 *status = data & 0xff;
395 device->controller->read_data(device, status);
401 static int nand_poll_ready(struct nand_device_s *device, int timeout)
405 device->controller->command(device, NAND_CMD_STATUS);
407 if (device->device->options & NAND_BUSWIDTH_16) {
409 device->controller->read_data(device, &data);
410 status = data & 0xff;
412 device->controller->read_data(device, &status);
414 if (status & NAND_STATUS_READY)
419 return (status & NAND_STATUS_READY) != 0;
422 int nand_probe(struct nand_device_s *device)
424 uint8_t manufacturer_id, device_id;
429 /* clear device data */
430 device->device = NULL;
431 device->manufacturer = NULL;
433 /* clear device parameters */
434 device->bus_width = 0;
435 device->address_cycles = 0;
436 device->page_size = 0;
437 device->erase_size = 0;
439 /* initialize controller (device parameters are zero, use controller default) */
440 if ((retval = device->controller->init(device) != ERROR_OK))
444 case ERROR_NAND_OPERATION_FAILED:
445 LOG_DEBUG("controller initialization failed");
446 return ERROR_NAND_OPERATION_FAILED;
447 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
448 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
449 return ERROR_NAND_OPERATION_FAILED;
451 LOG_ERROR("BUG: unknown controller initialization failure");
452 return ERROR_NAND_OPERATION_FAILED;
456 device->controller->command(device, NAND_CMD_RESET);
457 device->controller->reset(device);
459 device->controller->command(device, NAND_CMD_READID);
460 device->controller->address(device, 0x0);
462 if (device->bus_width == 8)
464 device->controller->read_data(device, &manufacturer_id);
465 device->controller->read_data(device, &device_id);
470 device->controller->read_data(device, &data_buf);
471 manufacturer_id = data_buf & 0xff;
472 device->controller->read_data(device, &data_buf);
473 device_id = data_buf & 0xff;
476 for (i = 0; nand_flash_ids[i].name; i++)
478 if (nand_flash_ids[i].id == device_id)
480 device->device = &nand_flash_ids[i];
485 for (i = 0; nand_manuf_ids[i].name; i++)
487 if (nand_manuf_ids[i].id == manufacturer_id)
489 device->manufacturer = &nand_manuf_ids[i];
494 if (!device->manufacturer)
496 device->manufacturer = &nand_manuf_ids[0];
497 device->manufacturer->id = manufacturer_id;
502 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
503 manufacturer_id, device_id);
504 return ERROR_NAND_OPERATION_FAILED;
507 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
509 /* initialize device parameters */
512 if (device->device->options & NAND_BUSWIDTH_16)
513 device->bus_width = 16;
515 device->bus_width = 8;
517 /* Do we need extended device probe information? */
518 if (device->device->page_size == 0 ||
519 device->device->erase_size == 0)
521 if (device->bus_width == 8)
523 device->controller->read_data(device, id_buff + 3);
524 device->controller->read_data(device, id_buff + 4);
525 device->controller->read_data(device, id_buff + 5);
531 device->controller->read_data(device, &data_buf);
532 id_buff[3] = data_buf;
534 device->controller->read_data(device, &data_buf);
535 id_buff[4] = data_buf;
537 device->controller->read_data(device, &data_buf);
538 id_buff[5] = data_buf >> 8;
543 if (device->device->page_size == 0)
545 device->page_size = 1 << (10 + (id_buff[4] & 3));
547 else if (device->device->page_size == 256)
549 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
550 return ERROR_NAND_OPERATION_FAILED;
554 device->page_size = device->device->page_size;
557 /* number of address cycles */
558 if (device->page_size <= 512)
560 /* small page devices */
561 if (device->device->chip_size <= 32)
562 device->address_cycles = 3;
563 else if (device->device->chip_size <= 8*1024)
564 device->address_cycles = 4;
567 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
568 device->address_cycles = 5;
573 /* large page devices */
574 if (device->device->chip_size <= 128)
575 device->address_cycles = 4;
576 else if (device->device->chip_size <= 32*1024)
577 device->address_cycles = 5;
580 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
581 device->address_cycles = 6;
586 if (device->device->erase_size == 0)
588 switch ((id_buff[4] >> 4) & 3) {
590 device->erase_size = 64 << 10;
593 device->erase_size = 128 << 10;
596 device->erase_size = 256 << 10;
599 device->erase_size =512 << 10;
605 device->erase_size = device->device->erase_size;
608 /* initialize controller, but leave parameters at the controllers default */
609 if ((retval = device->controller->init(device) != ERROR_OK))
613 case ERROR_NAND_OPERATION_FAILED:
614 LOG_DEBUG("controller initialization failed");
615 return ERROR_NAND_OPERATION_FAILED;
616 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
617 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
618 device->bus_width, device->address_cycles, device->page_size);
619 return ERROR_NAND_OPERATION_FAILED;
621 LOG_ERROR("BUG: unknown controller initialization failure");
622 return ERROR_NAND_OPERATION_FAILED;
626 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
627 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
629 for (i = 0; i < device->num_blocks; i++)
631 device->blocks[i].size = device->erase_size;
632 device->blocks[i].offset = i * device->erase_size;
633 device->blocks[i].is_erased = -1;
634 device->blocks[i].is_bad = -1;
640 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
648 return ERROR_NAND_DEVICE_NOT_PROBED;
650 if ((first_block < 0) || (last_block > device->num_blocks))
651 return ERROR_INVALID_ARGUMENTS;
653 /* make sure we know if a block is bad before erasing it */
654 for (i = first_block; i <= last_block; i++)
656 if (device->blocks[i].is_bad == -1)
658 nand_build_bbt(device, i, last_block);
663 for (i = first_block; i <= last_block; i++)
665 /* Send erase setup command */
666 device->controller->command(device, NAND_CMD_ERASE1);
668 page = i * (device->erase_size / device->page_size);
670 /* Send page address */
671 if (device->page_size <= 512)
674 device->controller->address(device, page & 0xff);
675 device->controller->address(device, (page >> 8) & 0xff);
677 /* 3rd cycle only on devices with more than 32 MiB */
678 if (device->address_cycles >= 4)
679 device->controller->address(device, (page >> 16) & 0xff);
681 /* 4th cycle only on devices with more than 8 GiB */
682 if (device->address_cycles >= 5)
683 device->controller->address(device, (page >> 24) & 0xff);
688 device->controller->address(device, page & 0xff);
689 device->controller->address(device, (page >> 8) & 0xff);
691 /* 3rd cycle only on devices with more than 128 MiB */
692 if (device->address_cycles >= 5)
693 device->controller->address(device, (page >> 16) & 0xff);
696 /* Send erase confirm command */
697 device->controller->command(device, NAND_CMD_ERASE2);
699 retval = device->controller->nand_ready ?
700 device->controller->nand_ready(device, 1000) :
701 nand_poll_ready(device, 1000);
703 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
704 return ERROR_NAND_OPERATION_TIMEOUT;
707 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
709 LOG_ERROR("couldn't read status");
710 return ERROR_NAND_OPERATION_FAILED;
715 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
716 return ERROR_NAND_OPERATION_FAILED;
719 device->blocks[i].is_erased = 1;
726 static int nand_read_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
731 return ERROR_NAND_DEVICE_NOT_PROBED;
733 if (address % device->page_size)
735 LOG_ERROR("reads need to be page aligned");
736 return ERROR_NAND_OPERATION_FAILED;
739 page = malloc(device->page_size);
741 while (data_size > 0)
743 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
744 uint32_t page_address;
747 page_address = address / device->page_size;
749 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
751 memcpy(data, page, thisrun_size);
753 address += thisrun_size;
754 data += thisrun_size;
755 data_size -= thisrun_size;
763 static int nand_write_plain(struct nand_device_s *device, uint32_t address, uint8_t *data, uint32_t data_size)
768 return ERROR_NAND_DEVICE_NOT_PROBED;
770 if (address % device->page_size)
772 LOG_ERROR("writes need to be page aligned");
773 return ERROR_NAND_OPERATION_FAILED;
776 page = malloc(device->page_size);
778 while (data_size > 0)
780 uint32_t thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
781 uint32_t page_address;
783 memset(page, 0xff, device->page_size);
784 memcpy(page, data, thisrun_size);
786 page_address = address / device->page_size;
788 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
790 address += thisrun_size;
791 data += thisrun_size;
792 data_size -= thisrun_size;
801 int nand_write_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
806 return ERROR_NAND_DEVICE_NOT_PROBED;
808 block = page / (device->erase_size / device->page_size);
809 if (device->blocks[block].is_erased == 1)
810 device->blocks[block].is_erased = 0;
812 if (device->use_raw || device->controller->write_page == NULL)
813 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
815 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
818 static int nand_read_page(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
821 return ERROR_NAND_DEVICE_NOT_PROBED;
823 if (device->use_raw || device->controller->read_page == NULL)
824 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
826 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
829 int nand_read_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
834 return ERROR_NAND_DEVICE_NOT_PROBED;
836 if (device->page_size <= 512)
838 /* small page device */
840 device->controller->command(device, NAND_CMD_READ0);
842 device->controller->command(device, NAND_CMD_READOOB);
844 /* column (always 0, we start at the beginning of a page/OOB area) */
845 device->controller->address(device, 0x0);
848 device->controller->address(device, page & 0xff);
849 device->controller->address(device, (page >> 8) & 0xff);
851 /* 4th cycle only on devices with more than 32 MiB */
852 if (device->address_cycles >= 4)
853 device->controller->address(device, (page >> 16) & 0xff);
855 /* 5th cycle only on devices with more than 8 GiB */
856 if (device->address_cycles >= 5)
857 device->controller->address(device, (page >> 24) & 0xff);
861 /* large page device */
862 device->controller->command(device, NAND_CMD_READ0);
864 /* column (0 when we start at the beginning of a page,
865 * or 2048 for the beginning of OOB area)
867 device->controller->address(device, 0x0);
869 device->controller->address(device, 0x0);
871 device->controller->address(device, 0x8);
874 device->controller->address(device, page & 0xff);
875 device->controller->address(device, (page >> 8) & 0xff);
877 /* 5th cycle only on devices with more than 128 MiB */
878 if (device->address_cycles >= 5)
879 device->controller->address(device, (page >> 16) & 0xff);
881 /* large page devices need a start command */
882 device->controller->command(device, NAND_CMD_READSTART);
885 if (device->controller->nand_ready) {
886 if (!device->controller->nand_ready(device, 100))
887 return ERROR_NAND_OPERATION_TIMEOUT;
894 if (device->controller->read_block_data != NULL)
895 (device->controller->read_block_data)(device, data, data_size);
898 for (i = 0; i < data_size;)
900 if (device->device->options & NAND_BUSWIDTH_16)
902 device->controller->read_data(device, data);
908 device->controller->read_data(device, data);
918 if (device->controller->read_block_data != NULL)
919 (device->controller->read_block_data)(device, oob, oob_size);
922 for (i = 0; i < oob_size;)
924 if (device->device->options & NAND_BUSWIDTH_16)
926 device->controller->read_data(device, oob);
932 device->controller->read_data(device, oob);
943 int nand_write_page_raw(struct nand_device_s *device, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
950 return ERROR_NAND_DEVICE_NOT_PROBED;
952 device->controller->command(device, NAND_CMD_SEQIN);
954 if (device->page_size <= 512)
956 /* column (always 0, we start at the beginning of a page/OOB area) */
957 device->controller->address(device, 0x0);
960 device->controller->address(device, page & 0xff);
961 device->controller->address(device, (page >> 8) & 0xff);
963 /* 4th cycle only on devices with more than 32 MiB */
964 if (device->address_cycles >= 4)
965 device->controller->address(device, (page >> 16) & 0xff);
967 /* 5th cycle only on devices with more than 8 GiB */
968 if (device->address_cycles >= 5)
969 device->controller->address(device, (page >> 24) & 0xff);
973 /* column (0 when we start at the beginning of a page,
974 * or 2048 for the beginning of OOB area)
976 device->controller->address(device, 0x0);
978 device->controller->address(device, 0x0);
980 device->controller->address(device, 0x8);
983 device->controller->address(device, page & 0xff);
984 device->controller->address(device, (page >> 8) & 0xff);
986 /* 5th cycle only on devices with more than 128 MiB */
987 if (device->address_cycles >= 5)
988 device->controller->address(device, (page >> 16) & 0xff);
993 if (device->controller->write_block_data != NULL)
994 (device->controller->write_block_data)(device, data, data_size);
997 for (i = 0; i < data_size;)
999 if (device->device->options & NAND_BUSWIDTH_16)
1001 uint16_t data_buf = le_to_h_u16(data);
1002 device->controller->write_data(device, data_buf);
1008 device->controller->write_data(device, *data);
1018 if (device->controller->write_block_data != NULL)
1019 (device->controller->write_block_data)(device, oob, oob_size);
1022 for (i = 0; i < oob_size;)
1024 if (device->device->options & NAND_BUSWIDTH_16)
1026 uint16_t oob_buf = le_to_h_u16(data);
1027 device->controller->write_data(device, oob_buf);
1033 device->controller->write_data(device, *oob);
1041 device->controller->command(device, NAND_CMD_PAGEPROG);
1043 retval = device->controller->nand_ready ?
1044 device->controller->nand_ready(device, 100) :
1045 nand_poll_ready(device, 100);
1047 return ERROR_NAND_OPERATION_TIMEOUT;
1049 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1051 LOG_ERROR("couldn't read status");
1052 return ERROR_NAND_OPERATION_FAILED;
1055 if (status & NAND_STATUS_FAIL)
1057 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1058 return ERROR_NAND_OPERATION_FAILED;
1064 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1071 command_print(cmd_ctx, "no NAND flash devices configured");
1075 for (p = nand_devices, i = 0; p; p = p->next, i++)
1078 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1079 i, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1081 command_print(cmd_ctx, "#%i: not probed", i);
1087 static int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1097 return ERROR_COMMAND_SYNTAX_ERROR;
1103 first = last = strtoul(args[1], NULL, 0);
1106 first = strtoul(args[1], NULL, 0);
1107 last = strtoul(args[2], NULL, 0);
1111 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1116 if (first >= p->num_blocks)
1117 first = p->num_blocks - 1;
1119 if (last >= p->num_blocks)
1120 last = p->num_blocks - 1;
1122 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1123 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1125 for (j = first; j <= last; j++)
1127 char *erase_state, *bad_state;
1129 if (p->blocks[j].is_erased == 0)
1130 erase_state = "not erased";
1131 else if (p->blocks[j].is_erased == 1)
1132 erase_state = "erased";
1134 erase_state = "erase state unknown";
1136 if (p->blocks[j].is_bad == 0)
1138 else if (p->blocks[j].is_bad == 1)
1139 bad_state = " (marked bad)";
1141 bad_state = " (block condition unknown)";
1143 command_print(cmd_ctx,
1144 "\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
1146 p->blocks[j].offset,
1147 p->blocks[j].size / 1024,
1154 command_print(cmd_ctx, "#%s: not probed", args[0]);
1161 static int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1168 return ERROR_COMMAND_SYNTAX_ERROR;
1171 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1174 if ((retval = nand_probe(p)) == ERROR_OK)
1176 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1178 else if (retval == ERROR_NAND_OPERATION_FAILED)
1180 command_print(cmd_ctx, "probing failed for NAND flash device");
1184 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1189 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1195 static int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1202 return ERROR_COMMAND_SYNTAX_ERROR;
1206 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1210 unsigned long offset;
1211 unsigned long length;
1213 offset = strtoul(args[1], &cp, 0);
1214 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1216 return ERROR_INVALID_ARGUMENTS;
1218 offset /= p->erase_size;
1220 length = strtoul(args[2], &cp, 0);
1221 if (*cp || length == ULONG_MAX || length % p->erase_size)
1223 return ERROR_INVALID_ARGUMENTS;
1226 length /= p->erase_size;
1228 retval = nand_erase(p, offset, offset + length);
1229 if (retval == ERROR_OK)
1231 command_print(cmd_ctx, "successfully erased blocks "
1232 "%lu to %lu on NAND flash device '%s'",
1233 offset, offset + length, p->device->name);
1235 else if (retval == ERROR_NAND_OPERATION_FAILED)
1237 command_print(cmd_ctx, "erase failed");
1241 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1246 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1252 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1259 if ((argc < 1) || (argc > 3) || (argc == 2))
1261 return ERROR_COMMAND_SYNTAX_ERROR;
1265 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1267 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds",
1269 return ERROR_INVALID_ARGUMENTS;
1275 unsigned long offset;
1276 unsigned long length;
1278 offset = strtoul(args[1], &cp, 0);
1279 if (*cp || offset == ULONG_MAX || offset % p->erase_size)
1281 return ERROR_INVALID_ARGUMENTS;
1283 offset /= p->erase_size;
1285 length = strtoul(args[2], &cp, 0);
1286 if (*cp || length == ULONG_MAX || length % p->erase_size)
1288 return ERROR_INVALID_ARGUMENTS;
1291 length /= p->erase_size;
1294 last = offset + length;
1297 retval = nand_build_bbt(p, first, last);
1298 if (retval == ERROR_OK)
1300 command_print(cmd_ctx, "checked NAND flash device for bad blocks, "
1301 "use \"nand info\" command to list blocks");
1303 else if (retval == ERROR_NAND_OPERATION_FAILED)
1305 command_print(cmd_ctx, "error when checking for bad blocks on "
1306 "NAND flash device");
1310 command_print(cmd_ctx, "unknown error when checking for bad "
1311 "blocks on NAND flash device");
1317 static int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1320 uint32_t binary_size;
1322 enum oob_formats oob_format = NAND_OOB_NONE;
1326 duration_t duration;
1327 char *duration_text;
1333 return ERROR_COMMAND_SYNTAX_ERROR;
1337 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1340 uint8_t *page = NULL;
1341 uint32_t page_size = 0;
1342 uint8_t *oob = NULL;
1343 uint32_t oob_size = 0;
1344 const int *eccpos = NULL;
1346 offset = strtoul(args[2], NULL, 0);
1351 for (i = 3; i < argc; i++)
1353 if (!strcmp(args[i], "oob_raw"))
1354 oob_format |= NAND_OOB_RAW;
1355 else if (!strcmp(args[i], "oob_only"))
1356 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1357 else if (!strcmp(args[i], "oob_softecc"))
1358 oob_format |= NAND_OOB_SW_ECC;
1359 else if (!strcmp(args[i], "oob_softecc_kw"))
1360 oob_format |= NAND_OOB_SW_ECC_KW;
1363 command_print(cmd_ctx, "unknown option: %s", args[i]);
1364 return ERROR_COMMAND_SYNTAX_ERROR;
1369 duration_start_measure(&duration);
1371 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1376 buf_cnt = binary_size = fileio.size;
1378 if (!(oob_format & NAND_OOB_ONLY))
1380 page_size = p->page_size;
1381 page = malloc(p->page_size);
1384 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC | NAND_OOB_SW_ECC_KW))
1386 if (p->page_size == 512) {
1388 eccpos = nand_oob_16.eccpos;
1389 } else if (p->page_size == 2048) {
1391 eccpos = nand_oob_64.eccpos;
1393 oob = malloc(oob_size);
1396 if (offset % p->page_size)
1398 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1399 fileio_close(&fileio);
1411 fileio_read(&fileio, page_size, page, &size_read);
1412 buf_cnt -= size_read;
1413 if (size_read < page_size)
1415 memset(page + size_read, 0xff, page_size - size_read);
1419 if (oob_format & NAND_OOB_SW_ECC)
1423 memset(oob, 0xff, oob_size);
1424 for (i = 0, j = 0; i < page_size; i += 256) {
1425 nand_calculate_ecc(p, page + i, ecc);
1426 oob[eccpos[j++]] = ecc[0];
1427 oob[eccpos[j++]] = ecc[1];
1428 oob[eccpos[j++]] = ecc[2];
1430 } else if (oob_format & NAND_OOB_SW_ECC_KW)
1433 * In this case eccpos is not used as
1434 * the ECC data is always stored contigously
1435 * at the end of the OOB area. It consists
1436 * of 10 bytes per 512-byte data block.
1439 uint8_t *ecc = oob + oob_size - page_size/512 * 10;
1440 memset(oob, 0xff, oob_size);
1441 for (i = 0; i < page_size; i += 512) {
1442 nand_calculate_ecc_kw(p, page + i, ecc);
1446 else if (NULL != oob)
1448 fileio_read(&fileio, oob_size, oob, &size_read);
1449 buf_cnt -= size_read;
1450 if (size_read < oob_size)
1452 memset(oob + size_read, 0xff, oob_size - size_read);
1456 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1458 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8" PRIx32 "",
1459 args[1], args[0], offset);
1461 fileio_close(&fileio);
1467 offset += page_size;
1470 fileio_close(&fileio);
1475 duration_stop_measure(&duration, &duration_text);
1476 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8" PRIx32 " in %s",
1477 args[1], args[0], offset, duration_text);
1478 free(duration_text);
1479 duration_text = NULL;
1483 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1489 static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1495 return ERROR_COMMAND_SYNTAX_ERROR;
1498 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1504 duration_t duration;
1505 char *duration_text;
1508 uint8_t *page = NULL;
1509 uint32_t page_size = 0;
1510 uint8_t *oob = NULL;
1511 uint32_t oob_size = 0;
1512 uint32_t address = strtoul(args[2], NULL, 0);
1513 uint32_t size = strtoul(args[3], NULL, 0);
1514 uint32_t bytes_done = 0;
1515 enum oob_formats oob_format = NAND_OOB_NONE;
1520 for (i = 4; i < argc; i++)
1522 if (!strcmp(args[i], "oob_raw"))
1523 oob_format |= NAND_OOB_RAW;
1524 else if (!strcmp(args[i], "oob_only"))
1525 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1527 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1531 if ((address % p->page_size) || (size % p->page_size))
1533 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1537 if (!(oob_format & NAND_OOB_ONLY))
1539 page_size = p->page_size;
1540 page = malloc(p->page_size);
1543 if (oob_format & NAND_OOB_RAW)
1545 if (p->page_size == 512)
1547 else if (p->page_size == 2048)
1549 oob = malloc(oob_size);
1552 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1557 duration_start_measure(&duration);
1561 uint32_t size_written;
1562 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1564 command_print(cmd_ctx, "reading NAND flash page failed");
1567 fileio_close(&fileio);
1573 fileio_write(&fileio, page_size, page, &size_written);
1574 bytes_done += page_size;
1579 fileio_write(&fileio, oob_size, oob, &size_written);
1580 bytes_done += oob_size;
1583 size -= p->page_size;
1584 address += p->page_size;
1591 fileio_close(&fileio);
1593 duration_stop_measure(&duration, &duration_text);
1594 command_print(cmd_ctx, "dumped %lld byte in %s", fileio.size, duration_text);
1595 free(duration_text);
1596 duration_text = NULL;
1600 command_print(cmd_ctx, "#%s: not probed", args[0]);
1605 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1611 static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1615 if ((argc < 1) || (argc > 2))
1617 return ERROR_COMMAND_SYNTAX_ERROR;
1620 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1627 if (strcmp("enable", args[1]) == 0)
1631 else if (strcmp("disable", args[1]) == 0)
1637 return ERROR_COMMAND_SYNTAX_ERROR;
1641 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1645 command_print(cmd_ctx, "#%s: not probed", args[0]);
1650 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);