1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Partially based on drivers/mtd/nand_ids.c from Linux. *
6 * Copyright (C) 2002 Thomas Gleixner <tglx@linutronix.de> *
8 * This program is free software; you can redistribute it and/or modify *
9 * it under the terms of the GNU General Public License as published by *
10 * the Free Software Foundation; either version 2 of the License, or *
11 * (at your option) any later version. *
13 * This program is distributed in the hope that it will be useful, *
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
16 * GNU General Public License for more details. *
18 * You should have received a copy of the GNU General Public License *
19 * along with this program; if not, write to the *
20 * Free Software Foundation, Inc., *
21 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
22 ***************************************************************************/
27 #include "replacements.h"
38 #include "time_support.h"
42 int nand_register_commands(struct command_context_s *cmd_ctx);
43 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
44 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
45 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
46 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
47 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
48 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
49 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
50 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
52 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
54 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
55 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
56 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size);
58 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
59 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
61 /* NAND flash controller
63 extern nand_flash_controller_t lpc3180_nand_controller;
64 extern nand_flash_controller_t orion_nand_controller;
65 extern nand_flash_controller_t s3c2410_nand_controller;
66 extern nand_flash_controller_t s3c2412_nand_controller;
67 extern nand_flash_controller_t s3c2440_nand_controller;
68 extern nand_flash_controller_t s3c2443_nand_controller;
70 /* extern nand_flash_controller_t boundary_scan_nand_controller; */
72 nand_flash_controller_t *nand_flash_controllers[] =
74 &lpc3180_nand_controller,
75 &orion_nand_controller,
76 &s3c2410_nand_controller,
77 &s3c2412_nand_controller,
78 &s3c2440_nand_controller,
79 &s3c2443_nand_controller,
80 /* &boundary_scan_nand_controller, */
84 /* configured NAND devices and NAND Flash command handler */
85 nand_device_t *nand_devices = NULL;
86 static command_t *nand_cmd;
90 * Name, ID code, pagesize, chipsize in MegaByte, eraseblock size,
93 * Pagesize; 0, 256, 512
94 * 0 get this information from the extended chip ID
95 * 256 256 Byte page size
96 * 512 512 Byte page size
98 nand_info_t nand_flash_ids[] =
100 {"NAND 1MiB 5V 8-bit", 0x6e, 256, 1, 0x1000, 0},
101 {"NAND 2MiB 5V 8-bit", 0x64, 256, 2, 0x1000, 0},
102 {"NAND 4MiB 5V 8-bit", 0x6b, 512, 4, 0x2000, 0},
103 {"NAND 1MiB 3,3V 8-bit", 0xe8, 256, 1, 0x1000, 0},
104 {"NAND 1MiB 3,3V 8-bit", 0xec, 256, 1, 0x1000, 0},
105 {"NAND 2MiB 3,3V 8-bit", 0xea, 256, 2, 0x1000, 0},
106 {"NAND 4MiB 3,3V 8-bit", 0xd5, 512, 4, 0x2000, 0},
107 {"NAND 4MiB 3,3V 8-bit", 0xe3, 512, 4, 0x2000, 0},
108 {"NAND 4MiB 3,3V 8-bit", 0xe5, 512, 4, 0x2000, 0},
109 {"NAND 8MiB 3,3V 8-bit", 0xd6, 512, 8, 0x2000, 0},
111 {"NAND 8MiB 1,8V 8-bit", 0x39, 512, 8, 0x2000, 0},
112 {"NAND 8MiB 3,3V 8-bit", 0xe6, 512, 8, 0x2000, 0},
113 {"NAND 8MiB 1,8V 16-bit", 0x49, 512, 8, 0x2000, NAND_BUSWIDTH_16},
114 {"NAND 8MiB 3,3V 16-bit", 0x59, 512, 8, 0x2000, NAND_BUSWIDTH_16},
116 {"NAND 16MiB 1,8V 8-bit", 0x33, 512, 16, 0x4000, 0},
117 {"NAND 16MiB 3,3V 8-bit", 0x73, 512, 16, 0x4000, 0},
118 {"NAND 16MiB 1,8V 16-bit", 0x43, 512, 16, 0x4000, NAND_BUSWIDTH_16},
119 {"NAND 16MiB 3,3V 16-bit", 0x53, 512, 16, 0x4000, NAND_BUSWIDTH_16},
121 {"NAND 32MiB 1,8V 8-bit", 0x35, 512, 32, 0x4000, 0},
122 {"NAND 32MiB 3,3V 8-bit", 0x75, 512, 32, 0x4000, 0},
123 {"NAND 32MiB 1,8V 16-bit", 0x45, 512, 32, 0x4000, NAND_BUSWIDTH_16},
124 {"NAND 32MiB 3,3V 16-bit", 0x55, 512, 32, 0x4000, NAND_BUSWIDTH_16},
126 {"NAND 64MiB 1,8V 8-bit", 0x36, 512, 64, 0x4000, 0},
127 {"NAND 64MiB 3,3V 8-bit", 0x76, 512, 64, 0x4000, 0},
128 {"NAND 64MiB 1,8V 16-bit", 0x46, 512, 64, 0x4000, NAND_BUSWIDTH_16},
129 {"NAND 64MiB 3,3V 16-bit", 0x56, 512, 64, 0x4000, NAND_BUSWIDTH_16},
131 {"NAND 128MiB 1,8V 8-bit", 0x78, 512, 128, 0x4000, 0},
132 {"NAND 128MiB 1,8V 8-bit", 0x39, 512, 128, 0x4000, 0},
133 {"NAND 128MiB 3,3V 8-bit", 0x79, 512, 128, 0x4000, 0},
134 {"NAND 128MiB 1,8V 16-bit", 0x72, 512, 128, 0x4000, NAND_BUSWIDTH_16},
135 {"NAND 128MiB 1,8V 16-bit", 0x49, 512, 128, 0x4000, NAND_BUSWIDTH_16},
136 {"NAND 128MiB 3,3V 16-bit", 0x74, 512, 128, 0x4000, NAND_BUSWIDTH_16},
137 {"NAND 128MiB 3,3V 16-bit", 0x59, 512, 128, 0x4000, NAND_BUSWIDTH_16},
139 {"NAND 256MiB 3,3V 8-bit", 0x71, 512, 256, 0x4000, 0},
141 {"NAND 64MiB 1,8V 8-bit", 0xA2, 0, 64, 0, LP_OPTIONS},
142 {"NAND 64MiB 3,3V 8-bit", 0xF2, 0, 64, 0, LP_OPTIONS},
143 {"NAND 64MiB 1,8V 16-bit", 0xB2, 0, 64, 0, LP_OPTIONS16},
144 {"NAND 64MiB 3,3V 16-bit", 0xC2, 0, 64, 0, LP_OPTIONS16},
146 {"NAND 128MiB 1,8V 8-bit", 0xA1, 0, 128, 0, LP_OPTIONS},
147 {"NAND 128MiB 3,3V 8-bit", 0xF1, 0, 128, 0, LP_OPTIONS},
148 {"NAND 128MiB 1,8V 16-bit", 0xB1, 0, 128, 0, LP_OPTIONS16},
149 {"NAND 128MiB 3,3V 16-bit", 0xC1, 0, 128, 0, LP_OPTIONS16},
151 {"NAND 256MiB 1,8V 8-bit", 0xAA, 0, 256, 0, LP_OPTIONS},
152 {"NAND 256MiB 3,3V 8-bit", 0xDA, 0, 256, 0, LP_OPTIONS},
153 {"NAND 256MiB 1,8V 16-bit", 0xBA, 0, 256, 0, LP_OPTIONS16},
154 {"NAND 256MiB 3,3V 16-bit", 0xCA, 0, 256, 0, LP_OPTIONS16},
156 {"NAND 512MiB 1,8V 8-bit", 0xAC, 0, 512, 0, LP_OPTIONS},
157 {"NAND 512MiB 3,3V 8-bit", 0xDC, 0, 512, 0, LP_OPTIONS},
158 {"NAND 512MiB 1,8V 16-bit", 0xBC, 0, 512, 0, LP_OPTIONS16},
159 {"NAND 512MiB 3,3V 16-bit", 0xCC, 0, 512, 0, LP_OPTIONS16},
161 {"NAND 1GiB 1,8V 8-bit", 0xA3, 0, 1024, 0, LP_OPTIONS},
162 {"NAND 1GiB 3,3V 8-bit", 0xD3, 0, 1024, 0, LP_OPTIONS},
163 {"NAND 1GiB 1,8V 16-bit", 0xB3, 0, 1024, 0, LP_OPTIONS16},
164 {"NAND 1GiB 3,3V 16-bit", 0xC3, 0, 1024, 0, LP_OPTIONS16},
166 {"NAND 2GiB 1,8V 8-bit", 0xA5, 0, 2048, 0, LP_OPTIONS},
167 {"NAND 2GiB 3,3V 8-bit", 0xD5, 0, 2048, 0, LP_OPTIONS},
168 {"NAND 2GiB 1,8V 16-bit", 0xB5, 0, 2048, 0, LP_OPTIONS16},
169 {"NAND 2GiB 3,3V 16-bit", 0xC5, 0, 2048, 0, LP_OPTIONS16},
174 /* Manufacturer ID list
176 nand_manufacturer_t nand_manuf_ids[] =
179 {NAND_MFR_TOSHIBA, "Toshiba"},
180 {NAND_MFR_SAMSUNG, "Samsung"},
181 {NAND_MFR_FUJITSU, "Fujitsu"},
182 {NAND_MFR_NATIONAL, "National"},
183 {NAND_MFR_RENESAS, "Renesas"},
184 {NAND_MFR_STMICRO, "ST Micro"},
185 {NAND_MFR_HYNIX, "Hynix"},
190 * Define default oob placement schemes for large and small page devices
193 nand_ecclayout_t nand_oob_8 = {
203 nand_ecclayout_t nand_oob_16 = {
205 .eccpos = {0, 1, 2, 3, 6, 7},
211 nand_ecclayout_t nand_oob_64 = {
214 40, 41, 42, 43, 44, 45, 46, 47,
215 48, 49, 50, 51, 52, 53, 54, 55,
216 56, 57, 58, 59, 60, 61, 62, 63},
222 /* nand device <nand_controller> [controller options]
224 int handle_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
231 LOG_WARNING("incomplete flash device nand configuration");
232 return ERROR_FLASH_BANK_INVALID;
235 for (i = 0; nand_flash_controllers[i]; i++)
237 nand_device_t *p, *c;
239 if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
241 /* register flash specific commands */
242 if ((retval = nand_flash_controllers[i]->register_commands(cmd_ctx)) != ERROR_OK)
244 LOG_ERROR("couldn't register '%s' commands", args[0]);
248 c = malloc(sizeof(nand_device_t));
250 c->controller = nand_flash_controllers[i];
251 c->controller_priv = NULL;
252 c->manufacturer = NULL;
255 c->address_cycles = 0;
260 if ((retval = nand_flash_controllers[i]->nand_device_command(cmd_ctx, cmd, args, argc, c)) != ERROR_OK)
262 LOG_ERROR("'%s' driver rejected nand flash", c->controller->name);
267 /* put NAND device in linked list */
270 /* find last flash device */
271 for (p = nand_devices; p && p->next; p = p->next);
284 /* no valid NAND controller was found (i.e. the configuration option,
285 * didn't match one of the compiled-in controllers)
287 LOG_ERROR("No valid NAND flash controller found (%s)", args[0]);
288 LOG_ERROR("compiled-in NAND flash controllers:");
289 for (i = 0; nand_flash_controllers[i]; i++)
291 LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
297 int nand_register_commands(struct command_context_s *cmd_ctx)
299 nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
301 register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
306 int nand_init(struct command_context_s *cmd_ctx)
310 register_command(cmd_ctx, nand_cmd, "list", handle_nand_list_command, COMMAND_EXEC,
311 "list configured NAND flash devices");
312 register_command(cmd_ctx, nand_cmd, "info", handle_nand_info_command, COMMAND_EXEC,
313 "print info about NAND flash device <num>");
314 register_command(cmd_ctx, nand_cmd, "probe", handle_nand_probe_command, COMMAND_EXEC,
315 "identify NAND flash device <num>");
316 register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
317 "check NAND flash device <num> for bad blocks [<first> <last>]");
318 register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
319 "erase blocks on NAND flash device <num> <first> <last>");
320 register_command(cmd_ctx, nand_cmd, "copy", handle_nand_copy_command, COMMAND_EXEC,
321 "copy from NAND flash device <num> <offset> <length> <ram-address>");
322 register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
323 "dump from NAND flash device <num> <filename> <offset> <size> [options]");
324 register_command(cmd_ctx, nand_cmd, "write", handle_nand_write_command, COMMAND_EXEC,
325 "write to NAND flash device <num> <filename> <offset> [oob_raw|oob_only|oob_softecc]");
326 register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
327 "raw access to NAND flash device <num> ['enable'|'disable']");
333 nand_device_t *get_nand_device_by_num(int num)
338 for (p = nand_devices; p; p = p->next)
349 int nand_build_bbt(struct nand_device_s *device, int first, int last)
355 if ((first < 0) || (first >= device->num_blocks))
358 if ((last >= device->num_blocks) || (last == -1))
359 last = device->num_blocks - 1;
361 for (i = first; i < last; i++)
363 nand_read_page(device, page, NULL, 0, oob, 6);
365 if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
366 || (((device->page_size == 512) && (oob[5] != 0xff)) ||
367 ((device->page_size == 2048) && (oob[0] != 0xff))))
369 LOG_WARNING("invalid block: %i", i);
370 device->blocks[i].is_bad = 1;
374 device->blocks[i].is_bad = 0;
377 page += (device->erase_size / device->page_size);
383 int nand_read_status(struct nand_device_s *device, u8 *status)
386 return ERROR_NAND_DEVICE_NOT_PROBED;
388 /* Send read status command */
389 device->controller->command(device, NAND_CMD_STATUS);
394 if (device->device->options & NAND_BUSWIDTH_16)
397 device->controller->read_data(device, &data);
398 *status = data & 0xff;
402 device->controller->read_data(device, status);
408 int nand_poll_ready(struct nand_device_s *device, int timeout)
412 device->controller->command(device, NAND_CMD_STATUS);
414 if (device->device->options & NAND_BUSWIDTH_16) {
416 device->controller->read_data(device, &data);
417 status = data & 0xff;
419 device->controller->read_data(device, &status);
421 if (status & NAND_STATUS_READY)
426 return (status & NAND_STATUS_READY) != 0;
429 int nand_probe(struct nand_device_s *device)
431 u8 manufacturer_id, device_id;
436 /* clear device data */
437 device->device = NULL;
438 device->manufacturer = NULL;
440 /* clear device parameters */
441 device->bus_width = 0;
442 device->address_cycles = 0;
443 device->page_size = 0;
444 device->erase_size = 0;
446 /* initialize controller (device parameters are zero, use controller default) */
447 if ((retval = device->controller->init(device) != ERROR_OK))
451 case ERROR_NAND_OPERATION_FAILED:
452 LOG_DEBUG("controller initialization failed");
453 return ERROR_NAND_OPERATION_FAILED;
454 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
455 LOG_ERROR("BUG: controller reported that it doesn't support default parameters");
456 return ERROR_NAND_OPERATION_FAILED;
458 LOG_ERROR("BUG: unknown controller initialization failure");
459 return ERROR_NAND_OPERATION_FAILED;
463 device->controller->command(device, NAND_CMD_RESET);
464 device->controller->reset(device);
466 device->controller->command(device, NAND_CMD_READID);
467 device->controller->address(device, 0x0);
469 if (device->bus_width == 8)
471 device->controller->read_data(device, &manufacturer_id);
472 device->controller->read_data(device, &device_id);
477 device->controller->read_data(device, &data_buf);
478 manufacturer_id = data_buf & 0xff;
479 device->controller->read_data(device, &data_buf);
480 device_id = data_buf & 0xff;
483 for (i = 0; nand_flash_ids[i].name; i++)
485 if (nand_flash_ids[i].id == device_id)
487 device->device = &nand_flash_ids[i];
492 for (i = 0; nand_manuf_ids[i].name; i++)
494 if (nand_manuf_ids[i].id == manufacturer_id)
496 device->manufacturer = &nand_manuf_ids[i];
501 if (!device->manufacturer)
503 device->manufacturer = &nand_manuf_ids[0];
504 device->manufacturer->id = manufacturer_id;
509 LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
510 manufacturer_id, device_id);
511 return ERROR_NAND_OPERATION_FAILED;
514 LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
516 /* initialize device parameters */
519 if (device->device->options & NAND_BUSWIDTH_16)
520 device->bus_width = 16;
522 device->bus_width = 8;
524 /* Do we need extended device probe information? */
525 if (device->device->page_size == 0 ||
526 device->device->erase_size == 0)
528 if (device->bus_width == 8)
530 device->controller->read_data(device, id_buff+3);
531 device->controller->read_data(device, id_buff+4);
532 device->controller->read_data(device, id_buff+5);
538 device->controller->read_data(device, &data_buf);
539 id_buff[3] = data_buf;
541 device->controller->read_data(device, &data_buf);
542 id_buff[4] = data_buf;
544 device->controller->read_data(device, &data_buf);
545 id_buff[5] = data_buf >> 8;
550 if (device->device->page_size == 0)
552 device->page_size = 1 << (10 + (id_buff[4] & 3));
554 else if (device->device->page_size == 256)
556 LOG_ERROR("NAND flashes with 256 byte pagesize are not supported");
557 return ERROR_NAND_OPERATION_FAILED;
561 device->page_size = device->device->page_size;
564 /* number of address cycles */
565 if (device->page_size <= 512)
567 /* small page devices */
568 if (device->device->chip_size <= 32)
569 device->address_cycles = 3;
570 else if (device->device->chip_size <= 8*1024)
571 device->address_cycles = 4;
574 LOG_ERROR("BUG: small page NAND device with more than 8 GiB encountered");
575 device->address_cycles = 5;
580 /* large page devices */
581 if (device->device->chip_size <= 128)
582 device->address_cycles = 4;
583 else if (device->device->chip_size <= 32*1024)
584 device->address_cycles = 5;
587 LOG_ERROR("BUG: large page NAND device with more than 32 GiB encountered");
588 device->address_cycles = 6;
593 if (device->device->erase_size == 0)
595 switch ((id_buff[4] >> 4) & 3) {
597 device->erase_size = 64 << 10;
600 device->erase_size = 128 << 10;
603 device->erase_size = 256 << 10;
606 device->erase_size =512 << 10;
612 device->erase_size = device->device->erase_size;
615 /* initialize controller, but leave parameters at the controllers default */
616 if ((retval = device->controller->init(device) != ERROR_OK))
620 case ERROR_NAND_OPERATION_FAILED:
621 LOG_DEBUG("controller initialization failed");
622 return ERROR_NAND_OPERATION_FAILED;
623 case ERROR_NAND_OPERATION_NOT_SUPPORTED:
624 LOG_ERROR("controller doesn't support requested parameters (buswidth: %i, address cycles: %i, page size: %i)",
625 device->bus_width, device->address_cycles, device->page_size);
626 return ERROR_NAND_OPERATION_FAILED;
628 LOG_ERROR("BUG: unknown controller initialization failure");
629 return ERROR_NAND_OPERATION_FAILED;
633 device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
634 device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
636 for (i = 0; i < device->num_blocks; i++)
638 device->blocks[i].size = device->erase_size;
639 device->blocks[i].offset = i * device->erase_size;
640 device->blocks[i].is_erased = -1;
641 device->blocks[i].is_bad = -1;
647 int nand_erase(struct nand_device_s *device, int first_block, int last_block)
655 return ERROR_NAND_DEVICE_NOT_PROBED;
657 if ((first_block < 0) || (last_block > device->num_blocks))
658 return ERROR_INVALID_ARGUMENTS;
660 /* make sure we know if a block is bad before erasing it */
661 for (i = first_block; i <= last_block; i++)
663 if (device->blocks[i].is_bad == -1)
665 nand_build_bbt(device, i, last_block);
670 for (i = first_block; i <= last_block; i++)
672 /* Send erase setup command */
673 device->controller->command(device, NAND_CMD_ERASE1);
675 page = i * (device->erase_size / device->page_size);
677 /* Send page address */
678 if (device->page_size <= 512)
681 device->controller->address(device, page & 0xff);
682 device->controller->address(device, (page >> 8) & 0xff);
684 /* 3rd cycle only on devices with more than 32 MiB */
685 if (device->address_cycles >= 4)
686 device->controller->address(device, (page >> 16) & 0xff);
688 /* 4th cycle only on devices with more than 8 GiB */
689 if (device->address_cycles >= 5)
690 device->controller->address(device, (page >> 24) & 0xff);
695 device->controller->address(device, page & 0xff);
696 device->controller->address(device, (page >> 8) & 0xff);
698 /* 3rd cycle only on devices with more than 128 MiB */
699 if (device->address_cycles >= 5)
700 device->controller->address(device, (page >> 16) & 0xff);
703 /* Send erase confirm command */
704 device->controller->command(device, NAND_CMD_ERASE2);
706 retval = device->controller->nand_ready ?
707 device->controller->nand_ready(device, 1000) :
708 nand_poll_ready(device, 1000);
710 LOG_ERROR("timeout waiting for NAND flash block erase to complete");
711 return ERROR_NAND_OPERATION_TIMEOUT;
714 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
716 LOG_ERROR("couldn't read status");
717 return ERROR_NAND_OPERATION_FAILED;
722 LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
723 return ERROR_NAND_OPERATION_FAILED;
726 device->blocks[i].is_erased = 1;
732 int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
737 return ERROR_NAND_DEVICE_NOT_PROBED;
739 if (address % device->page_size)
741 LOG_ERROR("reads need to be page aligned");
742 return ERROR_NAND_OPERATION_FAILED;
745 page = malloc(device->page_size);
747 while (data_size > 0 )
749 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
753 page_address = address / device->page_size;
755 nand_read_page(device, page_address, page, device->page_size, NULL, 0);
757 memcpy(data, page, thisrun_size);
759 address += thisrun_size;
760 data += thisrun_size;
761 data_size -= thisrun_size;
769 int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
774 return ERROR_NAND_DEVICE_NOT_PROBED;
776 if (address % device->page_size)
778 LOG_ERROR("writes need to be page aligned");
779 return ERROR_NAND_OPERATION_FAILED;
782 page = malloc(device->page_size);
784 while (data_size > 0 )
786 u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
789 memset(page, 0xff, device->page_size);
790 memcpy(page, data, thisrun_size);
792 page_address = address / device->page_size;
794 nand_write_page(device, page_address, page, device->page_size, NULL, 0);
796 address += thisrun_size;
797 data += thisrun_size;
798 data_size -= thisrun_size;
806 int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
811 return ERROR_NAND_DEVICE_NOT_PROBED;
813 block = page / (device->erase_size / device->page_size);
814 if (device->blocks[block].is_erased == 1)
815 device->blocks[block].is_erased = 0;
817 if (device->use_raw || device->controller->write_page == NULL)
818 return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
820 return device->controller->write_page(device, page, data, data_size, oob, oob_size);
823 int nand_read_page(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
826 return ERROR_NAND_DEVICE_NOT_PROBED;
828 if (device->use_raw || device->controller->read_page == NULL)
829 return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
831 return device->controller->read_page(device, page, data, data_size, oob, oob_size);
834 int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
839 return ERROR_NAND_DEVICE_NOT_PROBED;
841 if (device->page_size <= 512)
843 /* small page device */
845 device->controller->command(device, NAND_CMD_READ0);
847 device->controller->command(device, NAND_CMD_READOOB);
849 /* column (always 0, we start at the beginning of a page/OOB area) */
850 device->controller->address(device, 0x0);
853 device->controller->address(device, page & 0xff);
854 device->controller->address(device, (page >> 8) & 0xff);
856 /* 4th cycle only on devices with more than 32 MiB */
857 if (device->address_cycles >= 4)
858 device->controller->address(device, (page >> 16) & 0xff);
860 /* 5th cycle only on devices with more than 8 GiB */
861 if (device->address_cycles >= 5)
862 device->controller->address(device, (page >> 24) & 0xff);
866 /* large page device */
867 device->controller->command(device, NAND_CMD_READ0);
869 /* column (0 when we start at the beginning of a page,
870 * or 2048 for the beginning of OOB area)
872 device->controller->address(device, 0x0);
874 device->controller->address(device, 0x0);
876 device->controller->address(device, 0x8);
879 device->controller->address(device, page & 0xff);
880 device->controller->address(device, (page >> 8) & 0xff);
882 /* 5th cycle only on devices with more than 128 MiB */
883 if (device->address_cycles >= 5)
884 device->controller->address(device, (page >> 16) & 0xff);
886 /* large page devices need a start command */
887 device->controller->command(device, NAND_CMD_READSTART);
890 if (device->controller->nand_ready) {
891 if (!device->controller->nand_ready(device, 100))
892 return ERROR_NAND_OPERATION_TIMEOUT;
899 if (device->controller->read_block_data != NULL)
900 (device->controller->read_block_data)(device, data, data_size);
903 for (i = 0; i < data_size;)
905 if (device->device->options & NAND_BUSWIDTH_16)
907 device->controller->read_data(device, data);
913 device->controller->read_data(device, data);
923 if (device->controller->read_block_data != NULL)
924 (device->controller->read_block_data)(device, oob, oob_size);
927 for (i = 0; i < oob_size;)
929 if (device->device->options & NAND_BUSWIDTH_16)
931 device->controller->read_data(device, oob);
937 device->controller->read_data(device, oob);
948 int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
955 return ERROR_NAND_DEVICE_NOT_PROBED;
957 device->controller->command(device, NAND_CMD_SEQIN);
959 if (device->page_size <= 512)
961 /* column (always 0, we start at the beginning of a page/OOB area) */
962 device->controller->address(device, 0x0);
965 device->controller->address(device, page & 0xff);
966 device->controller->address(device, (page >> 8) & 0xff);
968 /* 4th cycle only on devices with more than 32 MiB */
969 if (device->address_cycles >= 4)
970 device->controller->address(device, (page >> 16) & 0xff);
972 /* 5th cycle only on devices with more than 8 GiB */
973 if (device->address_cycles >= 5)
974 device->controller->address(device, (page >> 24) & 0xff);
978 /* column (0 when we start at the beginning of a page,
979 * or 2048 for the beginning of OOB area)
981 device->controller->address(device, 0x0);
983 device->controller->address(device, 0x0);
985 device->controller->address(device, 0x8);
988 device->controller->address(device, page & 0xff);
989 device->controller->address(device, (page >> 8) & 0xff);
991 /* 5th cycle only on devices with more than 128 MiB */
992 if (device->address_cycles >= 5)
993 device->controller->address(device, (page >> 16) & 0xff);
998 if (device->controller->write_block_data != NULL)
999 (device->controller->write_block_data)(device, data, data_size);
1002 for (i = 0; i < data_size;)
1004 if (device->device->options & NAND_BUSWIDTH_16)
1006 u16 data_buf = le_to_h_u16(data);
1007 device->controller->write_data(device, data_buf);
1013 device->controller->write_data(device, *data);
1023 if (device->controller->write_block_data != NULL)
1024 (device->controller->write_block_data)(device, oob, oob_size);
1027 for (i = 0; i < oob_size;)
1029 if (device->device->options & NAND_BUSWIDTH_16)
1031 u16 oob_buf = le_to_h_u16(data);
1032 device->controller->write_data(device, oob_buf);
1038 device->controller->write_data(device, *oob);
1046 device->controller->command(device, NAND_CMD_PAGEPROG);
1048 retval = device->controller->nand_ready ?
1049 device->controller->nand_ready(device, 100) :
1050 nand_poll_ready(device, 100);
1052 return ERROR_NAND_OPERATION_TIMEOUT;
1054 if ((retval = nand_read_status(device, &status)) != ERROR_OK)
1056 LOG_ERROR("couldn't read status");
1057 return ERROR_NAND_OPERATION_FAILED;
1060 if (status & NAND_STATUS_FAIL)
1062 LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
1063 return ERROR_NAND_OPERATION_FAILED;
1069 int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1076 command_print(cmd_ctx, "no NAND flash devices configured");
1080 for (p = nand_devices; p; p = p->next)
1083 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1084 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1086 command_print(cmd_ctx, "#%i: not probed");
1092 int handle_nand_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1100 if ((argc < 1) || (argc > 3))
1102 return ERROR_COMMAND_SYNTAX_ERROR;
1108 first = last = strtoul(args[1], NULL, 0);
1112 first = strtoul(args[1], NULL, 0);
1113 last = strtoul(args[2], NULL, 0);
1116 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1121 if (first >= p->num_blocks)
1122 first = p->num_blocks - 1;
1124 if (last >= p->num_blocks)
1125 last = p->num_blocks - 1;
1127 command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
1128 i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
1130 for (j = first; j <= last; j++)
1132 char *erase_state, *bad_state;
1134 if (p->blocks[j].is_erased == 0)
1135 erase_state = "not erased";
1136 else if (p->blocks[j].is_erased == 1)
1137 erase_state = "erased";
1139 erase_state = "erase state unknown";
1141 if (p->blocks[j].is_bad == 0)
1143 else if (p->blocks[j].is_bad == 1)
1144 bad_state = " (marked bad)";
1146 bad_state = " (block condition unknown)";
1148 command_print(cmd_ctx, "\t#%i: 0x%8.8x (0x%xkB) %s%s",
1149 j, p->blocks[j].offset, p->blocks[j].size / 1024,
1150 erase_state, bad_state);
1155 command_print(cmd_ctx, "#%i: not probed");
1162 int handle_nand_probe_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1169 return ERROR_COMMAND_SYNTAX_ERROR;
1172 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1175 if ((retval = nand_probe(p)) == ERROR_OK)
1177 command_print(cmd_ctx, "NAND flash device '%s' found", p->device->name);
1179 else if (retval == ERROR_NAND_OPERATION_FAILED)
1181 command_print(cmd_ctx, "probing failed for NAND flash device");
1185 command_print(cmd_ctx, "unknown error when probing NAND flash device");
1190 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1196 int handle_nand_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1203 return ERROR_COMMAND_SYNTAX_ERROR;
1207 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1210 int first = strtoul(args[1], NULL, 0);
1211 int last = strtoul(args[2], NULL, 0);
1213 if ((retval = nand_erase(p, first, last)) == ERROR_OK)
1215 command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
1217 else if (retval == ERROR_NAND_OPERATION_FAILED)
1219 command_print(cmd_ctx, "erase failed");
1223 command_print(cmd_ctx, "unknown error when erasing NAND flash device");
1228 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1234 int handle_nand_check_bad_blocks_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1241 if ((argc < 1) || (argc > 3) || (argc == 2))
1243 return ERROR_COMMAND_SYNTAX_ERROR;
1249 first = strtoul(args[1], NULL, 0);
1250 last = strtoul(args[2], NULL, 0);
1253 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1256 if ((retval = nand_build_bbt(p, first, last)) == ERROR_OK)
1258 command_print(cmd_ctx, "checked NAND flash device for bad blocks, use \"nand info\" command to list blocks", p->device->name);
1260 else if (retval == ERROR_NAND_OPERATION_FAILED)
1262 command_print(cmd_ctx, "error when checking for bad blocks on NAND flash device");
1266 command_print(cmd_ctx, "unknown error when checking for bad blocks on NAND flash device");
1271 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1277 int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1283 return ERROR_COMMAND_SYNTAX_ERROR;
1287 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1294 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1300 int handle_nand_write_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1305 enum oob_formats oob_format = NAND_OOB_NONE;
1309 duration_t duration;
1310 char *duration_text;
1316 return ERROR_COMMAND_SYNTAX_ERROR;
1320 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1327 const int *eccpos = NULL;
1329 offset = strtoul(args[2], NULL, 0);
1334 for (i = 3; i < argc; i++)
1336 if (!strcmp(args[i], "oob_raw"))
1337 oob_format |= NAND_OOB_RAW;
1338 else if (!strcmp(args[i], "oob_only"))
1339 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1340 else if (!strcmp(args[i], "oob_softecc"))
1341 oob_format |= NAND_OOB_SW_ECC;
1344 command_print(cmd_ctx, "unknown option: %s", args[i]);
1345 return ERROR_COMMAND_SYNTAX_ERROR;
1350 duration_start_measure(&duration);
1352 if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
1357 buf_cnt = binary_size = fileio.size;
1359 if (!(oob_format & NAND_OOB_ONLY))
1361 page_size = p->page_size;
1362 page = malloc(p->page_size);
1365 if (oob_format & (NAND_OOB_RAW | NAND_OOB_SW_ECC))
1367 if (p->page_size == 512) {
1369 eccpos = nand_oob_16.eccpos;
1370 } else if (p->page_size == 2048) {
1372 eccpos = nand_oob_64.eccpos;
1374 oob = malloc(oob_size);
1377 if (offset % p->page_size)
1379 command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
1380 fileio_close(&fileio);
1392 fileio_read(&fileio, page_size, page, &size_read);
1393 buf_cnt -= size_read;
1394 if (size_read < page_size)
1396 memset(page + size_read, 0xff, page_size - size_read);
1400 if (oob_format & NAND_OOB_SW_ECC)
1404 memset(oob, 0xff, oob_size);
1405 for (i = 0, j = 0; i < page_size; i += 256) {
1406 nand_calculate_ecc(p, page+i, ecc);
1407 oob[eccpos[j++]] = ecc[0];
1408 oob[eccpos[j++]] = ecc[1];
1409 oob[eccpos[j++]] = ecc[2];
1412 else if (NULL != oob)
1414 fileio_read(&fileio, oob_size, oob, &size_read);
1415 buf_cnt -= size_read;
1416 if (size_read < oob_size)
1418 memset(oob + size_read, 0xff, oob_size - size_read);
1422 if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
1424 command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
1425 args[1], args[0], offset);
1427 fileio_close(&fileio);
1433 offset += page_size;
1436 fileio_close(&fileio);
1441 duration_stop_measure(&duration, &duration_text);
1442 command_print(cmd_ctx, "wrote file %s to NAND flash %s up to offset 0x%8.8x in %s",
1443 args[1], args[0], offset, duration_text);
1444 free(duration_text);
1445 duration_text = NULL;
1449 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1455 int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1461 return ERROR_COMMAND_SYNTAX_ERROR;
1464 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1470 duration_t duration;
1471 char *duration_text;
1478 u32 address = strtoul(args[2], NULL, 0);
1479 u32 size = strtoul(args[3], NULL, 0);
1481 enum oob_formats oob_format = NAND_OOB_NONE;
1486 for (i = 4; i < argc; i++)
1488 if (!strcmp(args[i], "oob_raw"))
1489 oob_format |= NAND_OOB_RAW;
1490 else if (!strcmp(args[i], "oob_only"))
1491 oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
1493 command_print(cmd_ctx, "unknown option: '%s'", args[i]);
1497 if ((address % p->page_size) || (size % p->page_size))
1499 command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
1503 if (!(oob_format & NAND_OOB_ONLY))
1505 page_size = p->page_size;
1506 page = malloc(p->page_size);
1509 if (oob_format & NAND_OOB_RAW)
1511 if (p->page_size == 512)
1513 else if (p->page_size == 2048)
1515 oob = malloc(oob_size);
1518 if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
1523 duration_start_measure(&duration);
1528 if ((retval = nand_read_page(p, address / p->page_size, page, page_size, oob, oob_size)) != ERROR_OK)
1530 command_print(cmd_ctx, "reading NAND flash page failed");
1533 fileio_close(&fileio);
1539 fileio_write(&fileio, page_size, page, &size_written);
1540 bytes_done += page_size;
1545 fileio_write(&fileio, oob_size, oob, &size_written);
1546 bytes_done += oob_size;
1549 size -= p->page_size;
1550 address += p->page_size;
1557 fileio_close(&fileio);
1559 duration_stop_measure(&duration, &duration_text);
1560 command_print(cmd_ctx, "dumped %"PRIi64" byte in %s", fileio.size, duration_text);
1561 free(duration_text);
1562 duration_text = NULL;
1566 command_print(cmd_ctx, "#%i: not probed");
1571 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
1577 int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
1581 if ((argc < 1) || (argc > 2))
1583 return ERROR_COMMAND_SYNTAX_ERROR;
1586 p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
1593 if (strcmp("enable", args[1]) == 0)
1597 else if (strcmp("disable", args[1]) == 0)
1603 return ERROR_COMMAND_SYNTAX_ERROR;
1607 command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
1611 command_print(cmd_ctx, "#%i: not probed");
1616 command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);