git.sur5r.net Git - openocd/blob - src/flash/nor/at91sam3.c

   1 /***************************************************************************
   2  *   Copyright (C) 2009 by Duane Ellis                                     *
   3  *   openocd@duaneellis.com                                                *
   4  *                                                                         *
   5  *   Copyright (C) 2010 by Olaf Lüke (at91sam3s* support)                  *
   6  *   olaf@uni-paderborn.de                                                 *
   7  *                                                                                                                                                 *
   8  *   Copyright (C) 2011 by Olivier Schonken (at91sam3x* support)           *                                          *
   9  *                     and Jim Norris                                      *
  10  *   This program is free software; you can redistribute it and/or modify  *
  11  *   it under the terms of the GNU General public License as published by  *
  12  *   the Free Software Foundation; either version 2 of the License, or     *
  13  *   (at your option) any later version.                                   *
  14  *                                                                         *
  15  *   This program is distributed in the hope that it will be useful,       *
  16  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  17  *   MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the         *
  18  *   GNU General public License for more details.                          *
  19  *                                                                         *
  20  *   You should have received a copy of the GNU General public License     *
  21  *   along with this program; if not, write to the                         *
  22  *   Free Software Foundation, Inc.,                                       *
  23  *   51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.           *
  24 ****************************************************************************/
  25
  26 /* Some of the the lower level code was based on code supplied by
  27  * ATMEL under this copyright. */
  28
  29 /* BEGIN ATMEL COPYRIGHT */
  30 /* ----------------------------------------------------------------------------
  31  *         ATMEL Microcontroller Software Support
  32  * ----------------------------------------------------------------------------
  33  * Copyright (c) 2009, Atmel Corporation
  34  *
  35  * All rights reserved.
  36  *
  37  * Redistribution and use in source and binary forms, with or without
  38  * modification, are permitted provided that the following conditions are met:
  39  *
  40  * - Redistributions of source code must retain the above copyright notice,
  41  * this list of conditions and the disclaimer below.
  42  *
  43  * Atmel's name may not be used to endorse or promote products derived from
  44  * this software without specific prior written permission.
  45  *
  46  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
  47  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  48  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
  49  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
  50  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  51  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
  52  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  53  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  54  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  55  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  56  * ----------------------------------------------------------------------------
  57  */
  58 /* END ATMEL COPYRIGHT */
  59
  60 #ifdef HAVE_CONFIG_H
  61 #include "config.h"
  62 #endif
  63
  64 #include "imp.h"
  65 #include <helper/time_support.h>
  66
  67 #define REG_NAME_WIDTH  (12)
  68
  69 /* at91sam3u series (has one or two flash banks) */
  70 #define FLASH_BANK0_BASE_U   0x00080000
  71 #define FLASH_BANK1_BASE_U   0x00100000
  72
  73 /* at91sam3s series (has always one flash bank) */
  74 #define FLASH_BANK_BASE_S   0x00400000
  75
  76 /* at91sam3sd series (has always two flash banks) */
  77 #define FLASH_BANK0_BASE_SD FLASH_BANK_BASE_S
  78 #define FLASH_BANK1_BASE_512K_SD (FLASH_BANK0_BASE_SD+(512*1024/2))
  79
  80
  81 /* at91sam3n series (has always one flash bank) */
  82 #define FLASH_BANK_BASE_N   0x00400000
  83
  84 /* at91sam3a/x series has two flash banks*/
  85 #define FLASH_BANK0_BASE_AX                     0x00080000
  86 /*Bank 1 of the at91sam3a/x series starts at 0x00080000 + half flash size*/
  87 #define FLASH_BANK1_BASE_256K_AX        0x000A0000
  88 #define FLASH_BANK1_BASE_512K_AX        0x000C0000
  89
  90 #define         AT91C_EFC_FCMD_GETD                 (0x0)       /* (EFC) Get Flash Descriptor */
  91 #define         AT91C_EFC_FCMD_WP                   (0x1)       /* (EFC) Write Page */
  92 #define         AT91C_EFC_FCMD_WPL                  (0x2)       /* (EFC) Write Page and Lock */
  93 #define         AT91C_EFC_FCMD_EWP                  (0x3)       /* (EFC) Erase Page and Write Page */
  94 #define         AT91C_EFC_FCMD_EWPL                 (0x4)       /* (EFC) Erase Page and Write Page then Lock */
  95 #define         AT91C_EFC_FCMD_EA                   (0x5)       /* (EFC) Erase All */
  96 /* cmd6 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
  97 /* #define      AT91C_EFC_FCMD_EPL                  (0x6) // (EFC) Erase plane? */
  98 /* cmd7 is not present in the at91sam3u4/2/1 data sheet table 17-2 */
  99 /* #define      AT91C_EFC_FCMD_EPA                  (0x7) // (EFC) Erase pages? */
 100 #define         AT91C_EFC_FCMD_SLB                  (0x8)       /* (EFC) Set Lock Bit */
 101 #define         AT91C_EFC_FCMD_CLB                  (0x9)       /* (EFC) Clear Lock Bit */
 102 #define         AT91C_EFC_FCMD_GLB                  (0xA)       /* (EFC) Get Lock Bit */
 103 #define         AT91C_EFC_FCMD_SFB                  (0xB)       /* (EFC) Set Fuse Bit */
 104 #define         AT91C_EFC_FCMD_CFB                  (0xC)       /* (EFC) Clear Fuse Bit */
 105 #define         AT91C_EFC_FCMD_GFB                  (0xD)       /* (EFC) Get Fuse Bit */
 106 #define         AT91C_EFC_FCMD_STUI                 (0xE)       /* (EFC) Start Read Unique ID */
 107 #define         AT91C_EFC_FCMD_SPUI                 (0xF)       /* (EFC) Stop Read Unique ID */
 108
 109 #define  offset_EFC_FMR   0
 110 #define  offset_EFC_FCR   4
 111 #define  offset_EFC_FSR   8
 112 #define  offset_EFC_FRR   12
 113
 114 extern struct flash_driver at91sam3_flash;
 115
 116 static float _tomhz(uint32_t freq_hz)
 117 {
 118         float f;
 119
 120         f = ((float)(freq_hz)) / 1000000.0;
 121         return f;
 122 }
 123
 124 /* How the chip is configured. */
 125 struct sam3_cfg {
 126         uint32_t unique_id[4];
 127
 128         uint32_t slow_freq;
 129         uint32_t rc_freq;
 130         uint32_t mainosc_freq;
 131         uint32_t plla_freq;
 132         uint32_t mclk_freq;
 133         uint32_t cpu_freq;
 134         uint32_t fclk_freq;
 135         uint32_t pclk0_freq;
 136         uint32_t pclk1_freq;
 137         uint32_t pclk2_freq;
 138
 139
 140 #define SAM3_CHIPID_CIDR          (0x400E0740)
 141         uint32_t CHIPID_CIDR;
 142 #define SAM3_CHIPID_CIDR2         (0x400E0940) /*SAM3X and SAM3A cidr at this address*/
 143         uint32_t CHIPID_CIDR2;
 144 #define SAM3_CHIPID_EXID          (0x400E0744)
 145         uint32_t CHIPID_EXID;
 146 #define SAM3_CHIPID_EXID2         (0x400E0944) /*SAM3X and SAM3A cidr at this address*/
 147         uint32_t CHIPID_EXID2;
 148
 149
 150 #define SAM3_PMC_BASE             (0x400E0400)
 151 #define SAM3_PMC_SCSR             (SAM3_PMC_BASE + 0x0008)
 152         uint32_t PMC_SCSR;
 153 #define SAM3_PMC_PCSR             (SAM3_PMC_BASE + 0x0018)
 154         uint32_t PMC_PCSR;
 155 #define SAM3_CKGR_UCKR            (SAM3_PMC_BASE + 0x001c)
 156         uint32_t CKGR_UCKR;
 157 #define SAM3_CKGR_MOR             (SAM3_PMC_BASE + 0x0020)
 158         uint32_t CKGR_MOR;
 159 #define SAM3_CKGR_MCFR            (SAM3_PMC_BASE + 0x0024)
 160         uint32_t CKGR_MCFR;
 161 #define SAM3_CKGR_PLLAR           (SAM3_PMC_BASE + 0x0028)
 162         uint32_t CKGR_PLLAR;
 163 #define SAM3_PMC_MCKR             (SAM3_PMC_BASE + 0x0030)
 164         uint32_t PMC_MCKR;
 165 #define SAM3_PMC_PCK0             (SAM3_PMC_BASE + 0x0040)
 166         uint32_t PMC_PCK0;
 167 #define SAM3_PMC_PCK1             (SAM3_PMC_BASE + 0x0044)
 168         uint32_t PMC_PCK1;
 169 #define SAM3_PMC_PCK2             (SAM3_PMC_BASE + 0x0048)
 170         uint32_t PMC_PCK2;
 171 #define SAM3_PMC_SR               (SAM3_PMC_BASE + 0x0068)
 172         uint32_t PMC_SR;
 173 #define SAM3_PMC_IMR              (SAM3_PMC_BASE + 0x006c)
 174         uint32_t PMC_IMR;
 175 #define SAM3_PMC_FSMR             (SAM3_PMC_BASE + 0x0070)
 176         uint32_t PMC_FSMR;
 177 #define SAM3_PMC_FSPR             (SAM3_PMC_BASE + 0x0074)
 178         uint32_t PMC_FSPR;
 179 };
 180
 181 /*
 182  * The AT91SAM3N data sheet 04-Oct-2010, AT91SAM3U data sheet 22-Aug-2011
 183  * and AT91SAM3S data sheet 09-Feb-2011 state that for flash writes
 184  * the flash wait state (FWS) should be set to 6. It seems like that the
 185  * cause of the problem is not the flash itself, but the flash write
 186  * buffer. Ie the wait states have to be set before writing into the
 187  * buffer.
 188  * Tested and confirmed with SAM3N and SAM3U
 189  */
 190
 191 struct sam3_bank_private {
 192         int probed;
 193         /* DANGER: THERE ARE DRAGONS HERE.. */
 194         /* NOTE: If you add more 'ghost' pointers */
 195         /* be aware that you must *manually* update */
 196         /* these pointers in the function sam3_GetDetails() */
 197         /* See the comment "Here there be dragons" */
 198
 199         /* so we can find the chip we belong to */
 200         struct sam3_chip *pChip;
 201         /* so we can find the original bank pointer */
 202         struct flash_bank *pBank;
 203         unsigned bank_number;
 204         uint32_t controller_address;
 205         uint32_t base_address;
 206         uint32_t flash_wait_states;
 207         bool present;
 208         unsigned size_bytes;
 209         unsigned nsectors;
 210         unsigned sector_size;
 211         unsigned page_size;
 212 };
 213
 214 struct sam3_chip_details {
 215         /* THERE ARE DRAGONS HERE.. */
 216         /* note: If you add pointers here */
 217         /* be careful about them as they */
 218         /* may need to be updated inside */
 219         /* the function: "sam3_GetDetails() */
 220         /* which copy/overwrites the */
 221         /* 'runtime' copy of this structure */
 222         uint32_t chipid_cidr;
 223         const char *name;
 224
 225         unsigned n_gpnvms;
 226 #define SAM3_N_NVM_BITS 3
 227         unsigned gpnvm[SAM3_N_NVM_BITS];
 228         unsigned total_flash_size;
 229         unsigned total_sram_size;
 230         unsigned n_banks;
 231 #define SAM3_MAX_FLASH_BANKS 2
 232         /* these are "initialized" from the global const data */
 233         struct sam3_bank_private bank[SAM3_MAX_FLASH_BANKS];
 234 };
 235
 236 struct sam3_chip {
 237         struct sam3_chip *next;
 238         int probed;
 239
 240         /* this is "initialized" from the global const structure */
 241         struct sam3_chip_details details;
 242         struct target *target;
 243         struct sam3_cfg cfg;
 244 };
 245
 246
 247 struct sam3_reg_list {
 248         uint32_t address;  size_t struct_offset; const char *name;
 249         void (*explain_func)(struct sam3_chip *pInfo);
 250 };
 251
 252 static struct sam3_chip *all_sam3_chips;
 253
 254 static struct sam3_chip *get_current_sam3(struct command_context *cmd_ctx)
 255 {
 256         struct target *t;
 257         static struct sam3_chip *p;
 258
 259         t = get_current_target(cmd_ctx);
 260         if (!t) {
 261                 command_print(cmd_ctx, "No current target?");
 262                 return NULL;
 263         }
 264
 265         p = all_sam3_chips;
 266         if (!p) {
 267                 /* this should not happen */
 268                 /* the command is not registered until the chip is created? */
 269                 command_print(cmd_ctx, "No SAM3 chips exist?");
 270                 return NULL;
 271         }
 272
 273         while (p) {
 274                 if (p->target == t)
 275                         return p;
 276                 p = p->next;
 277         }
 278         command_print(cmd_ctx, "Cannot find SAM3 chip?");
 279         return NULL;
 280 }
 281
 282 /* these are used to *initialize* the "pChip->details" structure. */
 283 static const struct sam3_chip_details all_sam3_details[] = {
 284         /* Start at91sam3u* series */
 285         {
 286                 .chipid_cidr    = 0x28100960,
 287                 .name           = "at91sam3u4e",
 288                 .total_flash_size     = 256 * 1024,
 289                 .total_sram_size      = 52 * 1024,
 290                 .n_gpnvms       = 3,
 291                 .n_banks        = 2,
 292
 293                 /* System boots at address 0x0 */
 294                 /* gpnvm[1] = selects boot code */
 295                 /*     if gpnvm[1] == 0 */
 296                 /*         boot is via "SAMBA" (rom) */
 297                 /*     else */
 298                 /*         boot is via FLASH */
 299                 /*         Selection is via gpnvm[2] */
 300                 /*     endif */
 301                 /*  */
 302                 /* NOTE: banks 0 & 1 switch places */
 303                 /*     if gpnvm[2] == 0 */
 304                 /*         Bank0 is the boot rom */
 305                 /*      else */
 306                 /*         Bank1 is the boot rom */
 307                 /*      endif */
 308 /*              .bank[0] = { */
 309                 {
 310                         {
 311                                 .probed = 0,
 312                                 .pChip  = NULL,
 313                                 .pBank  = NULL,
 314                                 .bank_number = 0,
 315                                 .base_address = FLASH_BANK0_BASE_U,
 316                                 .controller_address = 0x400e0800,
 317                                 .flash_wait_states = 6, /* workaround silicon bug */
 318                                 .present = 1,
 319                                 .size_bytes = 128 * 1024,
 320                                 .nsectors   = 16,
 321                                 .sector_size = 8192,
 322                                 .page_size   = 256,
 323                         },
 324
 325 /*              .bank[1] = { */
 326                         {
 327                                 .probed = 0,
 328                                 .pChip  = NULL,
 329                                 .pBank  = NULL,
 330                                 .bank_number = 1,
 331                                 .base_address = FLASH_BANK1_BASE_U,
 332                                 .controller_address = 0x400e0a00,
 333                                 .flash_wait_states = 6, /* workaround silicon bug */
 334                                 .present = 1,
 335                                 .size_bytes = 128 * 1024,
 336                                 .nsectors   = 16,
 337                                 .sector_size = 8192,
 338                                 .page_size   = 256,
 339                         },
 340                 },
 341         },
 342
 343         {
 344                 .chipid_cidr    = 0x281a0760,
 345                 .name           = "at91sam3u2e",
 346                 .total_flash_size     = 128 * 1024,
 347                 .total_sram_size      = 36 * 1024,
 348                 .n_gpnvms       = 2,
 349                 .n_banks        = 1,
 350
 351                 /* System boots at address 0x0 */
 352                 /* gpnvm[1] = selects boot code */
 353                 /*     if gpnvm[1] == 0 */
 354                 /*         boot is via "SAMBA" (rom) */
 355                 /*     else */
 356                 /*         boot is via FLASH */
 357                 /*         Selection is via gpnvm[2] */
 358                 /*     endif */
 359 /*              .bank[0] = { */
 360                 {
 361                         {
 362                                 .probed = 0,
 363                                 .pChip  = NULL,
 364                                 .pBank  = NULL,
 365                                 .bank_number = 0,
 366                                 .base_address = FLASH_BANK0_BASE_U,
 367                                 .controller_address = 0x400e0800,
 368                                 .flash_wait_states = 6, /* workaround silicon bug */
 369                                 .present = 1,
 370                                 .size_bytes = 128 * 1024,
 371                                 .nsectors   = 16,
 372                                 .sector_size = 8192,
 373                                 .page_size   = 256,
 374                         },
 375 /*                .bank[1] = { */
 376                         {
 377                                 .present = 0,
 378                                 .probed = 0,
 379                                 .bank_number = 1,
 380                         },
 381                 },
 382         },
 383         {
 384                 .chipid_cidr    = 0x28190560,
 385                 .name           = "at91sam3u1e",
 386                 .total_flash_size     = 64 * 1024,
 387                 .total_sram_size      = 20 * 1024,
 388                 .n_gpnvms       = 2,
 389                 .n_banks        = 1,
 390
 391                 /* System boots at address 0x0 */
 392                 /* gpnvm[1] = selects boot code */
 393                 /*     if gpnvm[1] == 0 */
 394                 /*         boot is via "SAMBA" (rom) */
 395                 /*     else */
 396                 /*         boot is via FLASH */
 397                 /*         Selection is via gpnvm[2] */
 398                 /*     endif */
 399                 /*  */
 400
 401 /*              .bank[0] = { */
 402                 {
 403                         {
 404                                 .probed = 0,
 405                                 .pChip  = NULL,
 406                                 .pBank  = NULL,
 407                                 .bank_number = 0,
 408                                 .base_address = FLASH_BANK0_BASE_U,
 409                                 .controller_address = 0x400e0800,
 410                                 .flash_wait_states = 6, /* workaround silicon bug */
 411                                 .present = 1,
 412                                 .size_bytes = 64 * 1024,
 413                                 .nsectors   = 8,
 414                                 .sector_size = 8192,
 415                                 .page_size   = 256,
 416                         },
 417
 418 /*              .bank[1] = { */
 419                         {
 420                                 .present = 0,
 421                                 .probed = 0,
 422                                 .bank_number = 1,
 423                         },
 424                 },
 425         },
 426
 427         {
 428                 .chipid_cidr    = 0x28000960,
 429                 .name           = "at91sam3u4c",
 430                 .total_flash_size     = 256 * 1024,
 431                 .total_sram_size      = 52 * 1024,
 432                 .n_gpnvms       = 3,
 433                 .n_banks        = 2,
 434
 435                 /* System boots at address 0x0 */
 436                 /* gpnvm[1] = selects boot code */
 437                 /*     if gpnvm[1] == 0 */
 438                 /*         boot is via "SAMBA" (rom) */
 439                 /*     else */
 440                 /*         boot is via FLASH */
 441                 /*         Selection is via gpnvm[2] */
 442                 /*     endif */
 443                 /*  */
 444                 /* NOTE: banks 0 & 1 switch places */
 445                 /*     if gpnvm[2] == 0 */
 446                 /*         Bank0 is the boot rom */
 447                 /*      else */
 448                 /*         Bank1 is the boot rom */
 449                 /*      endif */
 450                 {
 451                         {
 452 /*              .bank[0] = { */
 453                                 .probed = 0,
 454                                 .pChip  = NULL,
 455                                 .pBank  = NULL,
 456                                 .bank_number = 0,
 457                                 .base_address = FLASH_BANK0_BASE_U,
 458                                 .controller_address = 0x400e0800,
 459                                 .flash_wait_states = 6, /* workaround silicon bug */
 460                                 .present = 1,
 461                                 .size_bytes = 128 * 1024,
 462                                 .nsectors   = 16,
 463                                 .sector_size = 8192,
 464                                 .page_size   = 256,
 465                         },
 466 /*              .bank[1] = { */
 467                         {
 468                                 .probed = 0,
 469                                 .pChip  = NULL,
 470                                 .pBank  = NULL,
 471                                 .bank_number = 1,
 472                                 .base_address = FLASH_BANK1_BASE_U,
 473                                 .controller_address = 0x400e0a00,
 474                                 .flash_wait_states = 6, /* workaround silicon bug */
 475                                 .present = 1,
 476                                 .size_bytes = 128 * 1024,
 477                                 .nsectors   = 16,
 478                                 .sector_size = 8192,
 479                                 .page_size   = 256,
 480                         },
 481                 },
 482         },
 483
 484         {
 485                 .chipid_cidr    = 0x280a0760,
 486                 .name           = "at91sam3u2c",
 487                 .total_flash_size     = 128 * 1024,
 488                 .total_sram_size      = 36 * 1024,
 489                 .n_gpnvms       = 2,
 490                 .n_banks        = 1,
 491
 492                 /* System boots at address 0x0 */
 493                 /* gpnvm[1] = selects boot code */
 494                 /*     if gpnvm[1] == 0 */
 495                 /*         boot is via "SAMBA" (rom) */
 496                 /*     else */
 497                 /*         boot is via FLASH */
 498                 /*         Selection is via gpnvm[2] */
 499                 /*     endif */
 500                 {
 501 /*              .bank[0] = { */
 502                         {
 503                                 .probed = 0,
 504                                 .pChip  = NULL,
 505                                 .pBank  = NULL,
 506                                 .bank_number = 0,
 507                                 .base_address = FLASH_BANK0_BASE_U,
 508                                 .controller_address = 0x400e0800,
 509                                 .flash_wait_states = 6, /* workaround silicon bug */
 510                                 .present = 1,
 511                                 .size_bytes = 128 * 1024,
 512                                 .nsectors   = 16,
 513                                 .sector_size = 8192,
 514                                 .page_size   = 256,
 515                         },
 516 /*              .bank[1] = { */
 517                         {
 518                                 .present = 0,
 519                                 .probed = 0,
 520                                 .bank_number = 1,
 521                         },
 522                 },
 523         },
 524         {
 525                 .chipid_cidr    = 0x28090560,
 526                 .name           = "at91sam3u1c",
 527                 .total_flash_size     = 64 * 1024,
 528                 .total_sram_size      = 20 * 1024,
 529                 .n_gpnvms       = 2,
 530                 .n_banks        = 1,
 531
 532                 /* System boots at address 0x0 */
 533                 /* gpnvm[1] = selects boot code */
 534                 /*     if gpnvm[1] == 0 */
 535                 /*         boot is via "SAMBA" (rom) */
 536                 /*     else */
 537                 /*         boot is via FLASH */
 538                 /*         Selection is via gpnvm[2] */
 539                 /*     endif */
 540                 /*  */
 541
 542                 {
 543 /*              .bank[0] = { */
 544                         {
 545                                 .probed = 0,
 546                                 .pChip  = NULL,
 547                                 .pBank  = NULL,
 548                                 .bank_number = 0,
 549                                 .base_address = FLASH_BANK0_BASE_U,
 550                                 .controller_address = 0x400e0800,
 551                                 .flash_wait_states = 6, /* workaround silicon bug */
 552                                 .present = 1,
 553                                 .size_bytes = 64 * 1024,
 554                                 .nsectors   = 8,
 555                                 .sector_size = 8192,
 556                                 .page_size   = 256,
 557                         },
 558 /*              .bank[1] = { */
 559                         {
 560                                 .present = 0,
 561                                 .probed = 0,
 562                                 .bank_number = 1,
 563
 564                         },
 565                 },
 566         },
 567
 568         /* Start at91sam3s* series */
 569
 570         /* Note: The preliminary at91sam3s datasheet says on page 302 */
 571         /* that the flash controller is at address 0x400E0800. */
 572         /* This is _not_ the case, the controller resides at address 0x400e0a00. */
 573         {
 574                 .chipid_cidr    = 0x28A00960,
 575                 .name           = "at91sam3s4c",
 576                 .total_flash_size     = 256 * 1024,
 577                 .total_sram_size      = 48 * 1024,
 578                 .n_gpnvms       = 2,
 579                 .n_banks        = 1,
 580                 {
 581 /*              .bank[0] = { */
 582                         {
 583                                 .probed = 0,
 584                                 .pChip  = NULL,
 585                                 .pBank  = NULL,
 586                                 .bank_number = 0,
 587                                 .base_address = FLASH_BANK_BASE_S,
 588                                 .controller_address = 0x400e0a00,
 589                                 .flash_wait_states = 6, /* workaround silicon bug */
 590                                 .present = 1,
 591                                 .size_bytes = 256 * 1024,
 592                                 .nsectors   = 16,
 593                                 .sector_size = 16384,
 594                                 .page_size   = 256,
 595                         },
 596 /*              .bank[1] = { */
 597                         {
 598                                 .present = 0,
 599                                 .probed = 0,
 600                                 .bank_number = 1,
 601
 602                         },
 603                 },
 604         },
 605
 606         {
 607                 .chipid_cidr    = 0x28900960,
 608                 .name           = "at91sam3s4b",
 609                 .total_flash_size     = 256 * 1024,
 610                 .total_sram_size      = 48 * 1024,
 611                 .n_gpnvms       = 2,
 612                 .n_banks        = 1,
 613                 {
 614 /*              .bank[0] = { */
 615                         {
 616                                 .probed = 0,
 617                                 .pChip  = NULL,
 618                                 .pBank  = NULL,
 619                                 .bank_number = 0,
 620                                 .base_address = FLASH_BANK_BASE_S,
 621                                 .controller_address = 0x400e0a00,
 622                                 .flash_wait_states = 6, /* workaround silicon bug */
 623                                 .present = 1,
 624                                 .size_bytes = 256 * 1024,
 625                                 .nsectors   = 16,
 626                                 .sector_size = 16384,
 627                                 .page_size   = 256,
 628                         },
 629 /*              .bank[1] = { */
 630                         {
 631                                 .present = 0,
 632                                 .probed = 0,
 633                                 .bank_number = 1,
 634
 635                         },
 636                 },
 637         },
 638         {
 639                 .chipid_cidr    = 0x28800960,
 640                 .name           = "at91sam3s4a",
 641                 .total_flash_size     = 256 * 1024,
 642                 .total_sram_size      = 48 * 1024,
 643                 .n_gpnvms       = 2,
 644                 .n_banks        = 1,
 645                 {
 646 /*              .bank[0] = { */
 647                         {
 648                                 .probed = 0,
 649                                 .pChip  = NULL,
 650                                 .pBank  = NULL,
 651                                 .bank_number = 0,
 652                                 .base_address = FLASH_BANK_BASE_S,
 653                                 .controller_address = 0x400e0a00,
 654                                 .flash_wait_states = 6, /* workaround silicon bug */
 655                                 .present = 1,
 656                                 .size_bytes = 256 * 1024,
 657                                 .nsectors   = 16,
 658                                 .sector_size = 16384,
 659                                 .page_size   = 256,
 660                         },
 661 /*              .bank[1] = { */
 662                         {
 663                                 .present = 0,
 664                                 .probed = 0,
 665                                 .bank_number = 1,
 666
 667                         },
 668                 },
 669         },
 670         {
 671                 .chipid_cidr    = 0x28AA0760,
 672                 .name           = "at91sam3s2c",
 673                 .total_flash_size     = 128 * 1024,
 674                 .total_sram_size      = 32 * 1024,
 675                 .n_gpnvms       = 2,
 676                 .n_banks        = 1,
 677                 {
 678 /*              .bank[0] = { */
 679                         {
 680                                 .probed = 0,
 681                                 .pChip  = NULL,
 682                                 .pBank  = NULL,
 683                                 .bank_number = 0,
 684                                 .base_address = FLASH_BANK_BASE_S,
 685                                 .controller_address = 0x400e0a00,
 686                                 .flash_wait_states = 6, /* workaround silicon bug */
 687                                 .present = 1,
 688                                 .size_bytes = 128 * 1024,
 689                                 .nsectors   = 8,
 690                                 .sector_size = 16384,
 691                                 .page_size   = 256,
 692                         },
 693 /*              .bank[1] = { */
 694                         {
 695                                 .present = 0,
 696                                 .probed = 0,
 697                                 .bank_number = 1,
 698
 699                         },
 700                 },
 701         },
 702         {
 703                 .chipid_cidr    = 0x289A0760,
 704                 .name           = "at91sam3s2b",
 705                 .total_flash_size     = 128 * 1024,
 706                 .total_sram_size      = 32 * 1024,
 707                 .n_gpnvms       = 2,
 708                 .n_banks        = 1,
 709                 {
 710 /*              .bank[0] = { */
 711                         {
 712                                 .probed = 0,
 713                                 .pChip  = NULL,
 714                                 .pBank  = NULL,
 715                                 .bank_number = 0,
 716                                 .base_address = FLASH_BANK_BASE_S,
 717                                 .controller_address = 0x400e0a00,
 718                                 .flash_wait_states = 6, /* workaround silicon bug */
 719                                 .present = 1,
 720                                 .size_bytes = 128 * 1024,
 721                                 .nsectors   = 8,
 722                                 .sector_size = 16384,
 723                                 .page_size   = 256,
 724                         },
 725 /*              .bank[1] = { */
 726                         {
 727                                 .present = 0,
 728                                 .probed = 0,
 729                                 .bank_number = 1,
 730
 731                         },
 732                 },
 733         },
 734         {
 735                 .chipid_cidr    = 0x298B0A60,
 736                 .name           = "at91sam3sd8a",
 737                 .total_flash_size     = 512 * 1024,
 738                 .total_sram_size      = 64 * 1024,
 739                 .n_gpnvms       = 3,
 740                 .n_banks        = 2,
 741                 {
 742 /*                      .bank[0] = { */
 743                         {
 744                                 .probed = 0,
 745                                 .pChip  = NULL,
 746                                 .pBank  = NULL,
 747                                 .bank_number = 0,
 748                                 .base_address = FLASH_BANK0_BASE_SD,
 749                                 .controller_address = 0x400e0a00,
 750                                 .flash_wait_states = 6, /* workaround silicon bug */
 751                                 .present = 1,
 752                                 .size_bytes =  256 * 1024,
 753                                 .nsectors   =  16,
 754                                 .sector_size = 32768,
 755                                 .page_size   = 256,
 756                           },
 757 /*                      .bank[1] = { */
 758                           {
 759                                 .probed = 0,
 760                                 .pChip  = NULL,
 761                                 .pBank  = NULL,
 762                                 .bank_number = 1,
 763                                 .base_address = FLASH_BANK1_BASE_512K_SD,
 764                                 .controller_address = 0x400e0a00,
 765                                 .flash_wait_states = 6, /* workaround silicon bug */
 766                                 .present = 1,
 767                                 .size_bytes =  256 * 1024,
 768                                 .nsectors   =  16,
 769                                 .sector_size = 32768,
 770                                 .page_size   = 256,
 771                         },
 772                 },
 773         },
 774         {
 775                 .chipid_cidr    = 0x299B0A60,
 776                 .name           = "at91sam3sd8b",
 777                 .total_flash_size     = 512 * 1024,
 778                 .total_sram_size      = 64 * 1024,
 779                 .n_gpnvms       = 3,
 780                 .n_banks        = 2,
 781                 {
 782 /*                      .bank[0] = { */
 783                         {
 784                                 .probed = 0,
 785                                 .pChip  = NULL,
 786                                 .pBank  = NULL,
 787                                 .bank_number = 0,
 788                                 .base_address = FLASH_BANK0_BASE_SD,
 789                                 .controller_address = 0x400e0a00,
 790                                 .flash_wait_states = 6, /* workaround silicon bug */
 791                                 .present = 1,
 792                                 .size_bytes =  256 * 1024,
 793                                 .nsectors   =  16,
 794                                 .sector_size = 32768,
 795                                 .page_size   = 256,
 796                           },
 797 /*                      .bank[1] = { */
 798                           {
 799                                 .probed = 0,
 800                                 .pChip  = NULL,
 801                                 .pBank  = NULL,
 802                                 .bank_number = 1,
 803                                 .base_address = FLASH_BANK1_BASE_512K_SD,
 804                                 .controller_address = 0x400e0a00,
 805                                 .flash_wait_states = 6, /* workaround silicon bug */
 806                                 .present = 1,
 807                                 .size_bytes =  256 * 1024,
 808                                 .nsectors   =  16,
 809                                 .sector_size = 32768,
 810                                 .page_size   = 256,
 811                         },
 812                 },
 813         },
 814         {
 815                 .chipid_cidr    = 0x29ab0a60,
 816                 .name           = "at91sam3sd8c",
 817                 .total_flash_size     = 512 * 1024,
 818                 .total_sram_size      = 64 * 1024,
 819                 .n_gpnvms       = 3,
 820                 .n_banks        = 2,
 821                 {
 822 /*                      .bank[0] = { */
 823                         {
 824                                 .probed = 0,
 825                                 .pChip  = NULL,
 826                                 .pBank  = NULL,
 827                                 .bank_number = 0,
 828                                 .base_address = FLASH_BANK0_BASE_SD,
 829                                 .controller_address = 0x400e0a00,
 830                                 .flash_wait_states = 6, /* workaround silicon bug */
 831                                 .present = 1,
 832                                 .size_bytes =  256 * 1024,
 833                                 .nsectors   =  16,
 834                                 .sector_size = 32768,
 835                                 .page_size   = 256,
 836                           },
 837 /*                      .bank[1] = { */
 838                           {
 839                                 .probed = 0,
 840                                 .pChip  = NULL,
 841                                 .pBank  = NULL,
 842                                 .bank_number = 1,
 843                                 .base_address = FLASH_BANK1_BASE_512K_SD,
 844                                 .controller_address = 0x400e0a00,
 845                                 .flash_wait_states = 6, /* workaround silicon bug */
 846                                 .present = 1,
 847                                 .size_bytes =  256 * 1024,
 848                                 .nsectors   =  16,
 849                                 .sector_size = 32768,
 850                                 .page_size   = 256,
 851                         },
 852                 },
 853         },
 854         {
 855                 .chipid_cidr    = 0x288A0760,
 856                 .name           = "at91sam3s2a",
 857                 .total_flash_size     = 128 * 1024,
 858                 .total_sram_size      = 32 * 1024,
 859                 .n_gpnvms       = 2,
 860                 .n_banks        = 1,
 861                 {
 862 /*              .bank[0] = { */
 863                         {
 864                                 .probed = 0,
 865                                 .pChip  = NULL,
 866                                 .pBank  = NULL,
 867                                 .bank_number = 0,
 868                                 .base_address = FLASH_BANK_BASE_S,
 869                                 .controller_address = 0x400e0a00,
 870                                 .flash_wait_states = 6, /* workaround silicon bug */
 871                                 .present = 1,
 872                                 .size_bytes = 128 * 1024,
 873                                 .nsectors   = 8,
 874                                 .sector_size = 16384,
 875                                 .page_size   = 256,
 876                         },
 877 /*              .bank[1] = { */
 878                         {
 879                                 .present = 0,
 880                                 .probed = 0,
 881                                 .bank_number = 1,
 882
 883                         },
 884                 },
 885         },
 886         {
 887                 .chipid_cidr    = 0x28A90560,
 888                 .name           = "at91sam3s1c",
 889                 .total_flash_size     = 64 * 1024,
 890                 .total_sram_size      = 16 * 1024,
 891                 .n_gpnvms       = 2,
 892                 .n_banks        = 1,
 893                 {
 894 /*              .bank[0] = { */
 895                         {
 896                                 .probed = 0,
 897                                 .pChip  = NULL,
 898                                 .pBank  = NULL,
 899                                 .bank_number = 0,
 900                                 .base_address = FLASH_BANK_BASE_S,
 901                                 .controller_address = 0x400e0a00,
 902                                 .flash_wait_states = 6, /* workaround silicon bug */
 903                                 .present = 1,
 904                                 .size_bytes = 64 * 1024,
 905                                 .nsectors   = 4,
 906                                 .sector_size = 16384,
 907                                 .page_size   = 256,
 908                         },
 909 /*              .bank[1] = { */
 910                         {
 911                                 .present = 0,
 912                                 .probed = 0,
 913                                 .bank_number = 1,
 914
 915                         },
 916                 },
 917         },
 918         {
 919                 .chipid_cidr    = 0x28990560,
 920                 .name           = "at91sam3s1b",
 921                 .total_flash_size     = 64 * 1024,
 922                 .total_sram_size      = 16 * 1024,
 923                 .n_gpnvms       = 2,
 924                 .n_banks        = 1,
 925                 {
 926 /*              .bank[0] = { */
 927                         {
 928                                 .probed = 0,
 929                                 .pChip  = NULL,
 930                                 .pBank  = NULL,
 931                                 .bank_number = 0,
 932                                 .base_address = FLASH_BANK_BASE_S,
 933                                 .controller_address = 0x400e0a00,
 934                                 .flash_wait_states = 6, /* workaround silicon bug */
 935                                 .present = 1,
 936                                 .size_bytes = 64 * 1024,
 937                                 .nsectors   = 4,
 938                                 .sector_size = 16384,
 939                                 .page_size   = 256,
 940                         },
 941 /*              .bank[1] = { */
 942                         {
 943                                 .present = 0,
 944                                 .probed = 0,
 945                                 .bank_number = 1,
 946
 947                         },
 948                 },
 949         },
 950         {
 951                 .chipid_cidr    = 0x28890560,
 952                 .name           = "at91sam3s1a",
 953                 .total_flash_size     = 64 * 1024,
 954                 .total_sram_size      = 16 * 1024,
 955                 .n_gpnvms       = 2,
 956                 .n_banks        = 1,
 957                 {
 958 /*              .bank[0] = { */
 959                         {
 960                                 .probed = 0,
 961                                 .pChip  = NULL,
 962                                 .pBank  = NULL,
 963                                 .bank_number = 0,
 964                                 .base_address = FLASH_BANK_BASE_S,
 965                                 .controller_address = 0x400e0a00,
 966                                 .flash_wait_states = 6, /* workaround silicon bug */
 967                                 .present = 1,
 968                                 .size_bytes = 64 * 1024,
 969                                 .nsectors   = 4,
 970                                 .sector_size = 16384,
 971                                 .page_size   = 256,
 972                         },
 973 /*              .bank[1] = { */
 974                         {
 975                                 .present = 0,
 976                                 .probed = 0,
 977                                 .bank_number = 1,
 978
 979                         },
 980                 },
 981         },
 982
 983         /* Start at91sam3n* series */
 984         {
 985                 .chipid_cidr    = 0x29540960,
 986                 .name           = "at91sam3n4c",
 987                 .total_flash_size     = 256 * 1024,
 988                 .total_sram_size      = 24 * 1024,
 989                 .n_gpnvms       = 3,
 990                 .n_banks        = 1,
 991
 992                 /* System boots at address 0x0 */
 993                 /* gpnvm[1] = selects boot code */
 994                 /*     if gpnvm[1] == 0 */
 995                 /*         boot is via "SAMBA" (rom) */
 996                 /*     else */
 997                 /*         boot is via FLASH */
 998                 /*         Selection is via gpnvm[2] */
 999                 /*     endif */
1000                 /*  */
1001                 /* NOTE: banks 0 & 1 switch places */
1002                 /*     if gpnvm[2] == 0 */
1003                 /*         Bank0 is the boot rom */
1004                 /*      else */
1005                 /*         Bank1 is the boot rom */
1006                 /*      endif */
1007 /*              .bank[0] = { */
1008                 {
1009                         {
1010                                 .probed = 0,
1011                                 .pChip  = NULL,
1012                                 .pBank  = NULL,
1013                                 .bank_number = 0,
1014                                 .base_address = FLASH_BANK_BASE_N,
1015                                 .controller_address = 0x400e0A00,
1016                                 .flash_wait_states = 6, /* workaround silicon bug */
1017                                 .present = 1,
1018                                 .size_bytes = 256 * 1024,
1019                                 .nsectors   = 16,
1020                                 .sector_size = 16384,
1021                                 .page_size   = 256,
1022                         },
1023
1024 /*              .bank[1] = { */
1025                         {
1026                                 .present = 0,
1027                                 .probed = 0,
1028                                 .bank_number = 1,
1029                         },
1030                 },
1031         },
1032
1033         {
1034                 .chipid_cidr    = 0x29440960,
1035                 .name           = "at91sam3n4b",
1036                 .total_flash_size     = 256 * 1024,
1037                 .total_sram_size      = 24 * 1024,
1038                 .n_gpnvms       = 3,
1039                 .n_banks        = 1,
1040
1041                 /* System boots at address 0x0 */
1042                 /* gpnvm[1] = selects boot code */
1043                 /*     if gpnvm[1] == 0 */
1044                 /*         boot is via "SAMBA" (rom) */
1045                 /*     else */
1046                 /*         boot is via FLASH */
1047                 /*         Selection is via gpnvm[2] */
1048                 /*     endif */
1049                 /*  */
1050                 /* NOTE: banks 0 & 1 switch places */
1051                 /*     if gpnvm[2] == 0 */
1052                 /*         Bank0 is the boot rom */
1053                 /*      else */
1054                 /*         Bank1 is the boot rom */
1055                 /*      endif */
1056 /*              .bank[0] = { */
1057                 {
1058                         {
1059                                 .probed = 0,
1060                                 .pChip  = NULL,
1061                                 .pBank  = NULL,
1062                                 .bank_number = 0,
1063                                 .base_address = FLASH_BANK_BASE_N,
1064                                 .controller_address = 0x400e0A00,
1065                                 .flash_wait_states = 6, /* workaround silicon bug */
1066                                 .present = 1,
1067                                 .size_bytes = 256 * 1024,
1068                                 .nsectors   = 16,
1069                                 .sector_size = 16384,
1070                                 .page_size   = 256,
1071                         },
1072
1073 /*              .bank[1] = { */
1074                         {
1075                                 .present = 0,
1076                                 .probed = 0,
1077                                 .bank_number = 1,
1078                         },
1079                 },
1080         },
1081
1082         {
1083                 .chipid_cidr    = 0x29340960,
1084                 .name           = "at91sam3n4a",
1085                 .total_flash_size     = 256 * 1024,
1086                 .total_sram_size      = 24 * 1024,
1087                 .n_gpnvms       = 3,
1088                 .n_banks        = 1,
1089
1090                 /* System boots at address 0x0 */
1091                 /* gpnvm[1] = selects boot code */
1092                 /*     if gpnvm[1] == 0 */
1093                 /*         boot is via "SAMBA" (rom) */
1094                 /*     else */
1095                 /*         boot is via FLASH */
1096                 /*         Selection is via gpnvm[2] */
1097                 /*     endif */
1098                 /*  */
1099                 /* NOTE: banks 0 & 1 switch places */
1100                 /*     if gpnvm[2] == 0 */
1101                 /*         Bank0 is the boot rom */
1102                 /*      else */
1103                 /*         Bank1 is the boot rom */
1104                 /*      endif */
1105 /*              .bank[0] = { */
1106                 {
1107                         {
1108                                 .probed = 0,
1109                                 .pChip  = NULL,
1110                                 .pBank  = NULL,
1111                                 .bank_number = 0,
1112                                 .base_address = FLASH_BANK_BASE_N,
1113                                 .controller_address = 0x400e0A00,
1114                                 .flash_wait_states = 6, /* workaround silicon bug */
1115                                 .present = 1,
1116                                 .size_bytes = 256 * 1024,
1117                                 .nsectors   = 16,
1118                                 .sector_size = 16384,
1119                                 .page_size   = 256,
1120                         },
1121
1122 /*              .bank[1] = { */
1123                         {
1124                                 .present = 0,
1125                                 .probed = 0,
1126                                 .bank_number = 1,
1127                         },
1128                 },
1129         },
1130
1131         {
1132                 .chipid_cidr    = 0x29590760,
1133                 .name           = "at91sam3n2c",
1134                 .total_flash_size     = 128 * 1024,
1135                 .total_sram_size      = 16 * 1024,
1136                 .n_gpnvms       = 3,
1137                 .n_banks        = 1,
1138
1139                 /* System boots at address 0x0 */
1140                 /* gpnvm[1] = selects boot code */
1141                 /*     if gpnvm[1] == 0 */
1142                 /*         boot is via "SAMBA" (rom) */
1143                 /*     else */
1144                 /*         boot is via FLASH */
1145                 /*         Selection is via gpnvm[2] */
1146                 /*     endif */
1147                 /*  */
1148                 /* NOTE: banks 0 & 1 switch places */
1149                 /*     if gpnvm[2] == 0 */
1150                 /*         Bank0 is the boot rom */
1151                 /*      else */
1152                 /*         Bank1 is the boot rom */
1153                 /*      endif */
1154 /*              .bank[0] = { */
1155                 {
1156                         {
1157                                 .probed = 0,
1158                                 .pChip  = NULL,
1159                                 .pBank  = NULL,
1160                                 .bank_number = 0,
1161                                 .base_address = FLASH_BANK_BASE_N,
1162                                 .controller_address = 0x400e0A00,
1163                                 .flash_wait_states = 6, /* workaround silicon bug */
1164                                 .present = 1,
1165                                 .size_bytes = 128 * 1024,
1166                                 .nsectors   = 8,
1167                                 .sector_size = 16384,
1168                                 .page_size   = 256,
1169                         },
1170
1171 /*              .bank[1] = { */
1172                         {
1173                                 .present = 0,
1174                                 .probed = 0,
1175                                 .bank_number = 1,
1176                         },
1177                 },
1178         },
1179
1180         {
1181                 .chipid_cidr    = 0x29490760,
1182                 .name           = "at91sam3n2b",
1183                 .total_flash_size     = 128 * 1024,
1184                 .total_sram_size      = 16 * 1024,
1185                 .n_gpnvms       = 3,
1186                 .n_banks        = 1,
1187
1188                 /* System boots at address 0x0 */
1189                 /* gpnvm[1] = selects boot code */
1190                 /*     if gpnvm[1] == 0 */
1191                 /*         boot is via "SAMBA" (rom) */
1192                 /*     else */
1193                 /*         boot is via FLASH */
1194                 /*         Selection is via gpnvm[2] */
1195                 /*     endif */
1196                 /*  */
1197                 /* NOTE: banks 0 & 1 switch places */
1198                 /*     if gpnvm[2] == 0 */
1199                 /*         Bank0 is the boot rom */
1200                 /*      else */
1201                 /*         Bank1 is the boot rom */
1202                 /*      endif */
1203 /*              .bank[0] = { */
1204                 {
1205                         {
1206                                 .probed = 0,
1207                                 .pChip  = NULL,
1208                                 .pBank  = NULL,
1209                                 .bank_number = 0,
1210                                 .base_address = FLASH_BANK_BASE_N,
1211                                 .controller_address = 0x400e0A00,
1212                                 .flash_wait_states = 6, /* workaround silicon bug */
1213                                 .present = 1,
1214                                 .size_bytes = 128 * 1024,
1215                                 .nsectors   = 8,
1216                                 .sector_size = 16384,
1217                                 .page_size   = 256,
1218                         },
1219
1220 /*              .bank[1] = { */
1221                         {
1222                                 .present = 0,
1223                                 .probed = 0,
1224                                 .bank_number = 1,
1225                         },
1226                 },
1227         },
1228
1229         {
1230                 .chipid_cidr    = 0x29390760,
1231                 .name           = "at91sam3n2a",
1232                 .total_flash_size     = 128 * 1024,
1233                 .total_sram_size      = 16 * 1024,
1234                 .n_gpnvms       = 3,
1235                 .n_banks        = 1,
1236
1237                 /* System boots at address 0x0 */
1238                 /* gpnvm[1] = selects boot code */
1239                 /*     if gpnvm[1] == 0 */
1240                 /*         boot is via "SAMBA" (rom) */
1241                 /*     else */
1242                 /*         boot is via FLASH */
1243                 /*         Selection is via gpnvm[2] */
1244                 /*     endif */
1245                 /*  */
1246                 /* NOTE: banks 0 & 1 switch places */
1247                 /*     if gpnvm[2] == 0 */
1248                 /*         Bank0 is the boot rom */
1249                 /*      else */
1250                 /*         Bank1 is the boot rom */
1251                 /*      endif */
1252 /*              .bank[0] = { */
1253                 {
1254                         {
1255                                 .probed = 0,
1256                                 .pChip  = NULL,
1257                                 .pBank  = NULL,
1258                                 .bank_number = 0,
1259                                 .base_address = FLASH_BANK_BASE_N,
1260                                 .controller_address = 0x400e0A00,
1261                                 .flash_wait_states = 6, /* workaround silicon bug */
1262                                 .present = 1,
1263                                 .size_bytes = 128 * 1024,
1264                                 .nsectors   = 8,
1265                                 .sector_size = 16384,
1266                                 .page_size   = 256,
1267                         },
1268
1269 /*              .bank[1] = { */
1270                         {
1271                                 .present = 0,
1272                                 .probed = 0,
1273                                 .bank_number = 1,
1274                         },
1275                 },
1276         },
1277
1278         {
1279                 .chipid_cidr    = 0x29580560,
1280                 .name           = "at91sam3n1c",
1281                 .total_flash_size     = 64 * 1024,
1282                 .total_sram_size      = 8 * 1024,
1283                 .n_gpnvms       = 3,
1284                 .n_banks        = 1,
1285
1286                 /* System boots at address 0x0 */
1287                 /* gpnvm[1] = selects boot code */
1288                 /*     if gpnvm[1] == 0 */
1289                 /*         boot is via "SAMBA" (rom) */
1290                 /*     else */
1291                 /*         boot is via FLASH */
1292                 /*         Selection is via gpnvm[2] */
1293                 /*     endif */
1294                 /*  */
1295                 /* NOTE: banks 0 & 1 switch places */
1296                 /*     if gpnvm[2] == 0 */
1297                 /*         Bank0 is the boot rom */
1298                 /*      else */
1299                 /*         Bank1 is the boot rom */
1300                 /*      endif */
1301 /*              .bank[0] = { */
1302                 {
1303                         {
1304                                 .probed = 0,
1305                                 .pChip  = NULL,
1306                                 .pBank  = NULL,
1307                                 .bank_number = 0,
1308                                 .base_address = FLASH_BANK_BASE_N,
1309                                 .controller_address = 0x400e0A00,
1310                                 .flash_wait_states = 6, /* workaround silicon bug */
1311                                 .present = 1,
1312                                 .size_bytes = 64 * 1024,
1313                                 .nsectors   = 4,
1314                                 .sector_size = 16384,
1315                                 .page_size   = 256,
1316                         },
1317
1318 /*              .bank[1] = { */
1319                         {
1320                                 .present = 0,
1321                                 .probed = 0,
1322                                 .bank_number = 1,
1323                         },
1324                 },
1325         },
1326
1327         {
1328                 .chipid_cidr    = 0x29480560,
1329                 .name           = "at91sam3n1b",
1330                 .total_flash_size     = 64 * 1024,
1331                 .total_sram_size      = 8 * 1024,
1332                 .n_gpnvms       = 3,
1333                 .n_banks        = 1,
1334
1335                 /* System boots at address 0x0 */
1336                 /* gpnvm[1] = selects boot code */
1337                 /*     if gpnvm[1] == 0 */
1338                 /*         boot is via "SAMBA" (rom) */
1339                 /*     else */
1340                 /*         boot is via FLASH */
1341                 /*         Selection is via gpnvm[2] */
1342                 /*     endif */
1343                 /*  */
1344                 /* NOTE: banks 0 & 1 switch places */
1345                 /*     if gpnvm[2] == 0 */
1346                 /*         Bank0 is the boot rom */
1347                 /*      else */
1348                 /*         Bank1 is the boot rom */
1349                 /*      endif */
1350 /*              .bank[0] = { */
1351                 {
1352                         {
1353                                 .probed = 0,
1354                                 .pChip  = NULL,
1355                                 .pBank  = NULL,
1356                                 .bank_number = 0,
1357                                 .base_address = FLASH_BANK_BASE_N,
1358                                 .controller_address = 0x400e0A00,
1359                                 .flash_wait_states = 6, /* workaround silicon bug */
1360                                 .present = 1,
1361                                 .size_bytes = 64 * 1024,
1362                                 .nsectors   = 4,
1363                                 .sector_size = 16384,
1364                                 .page_size   = 256,
1365                         },
1366
1367 /*              .bank[1] = { */
1368                         {
1369                                 .present = 0,
1370                                 .probed = 0,
1371                                 .bank_number = 1,
1372                         },
1373                 },
1374         },
1375
1376         {
1377                 .chipid_cidr    = 0x29380560,
1378                 .name           = "at91sam3n1a",
1379                 .total_flash_size     = 64 * 1024,
1380                 .total_sram_size      = 8 * 1024,
1381                 .n_gpnvms       = 3,
1382                 .n_banks        = 1,
1383
1384                 /* System boots at address 0x0 */
1385                 /* gpnvm[1] = selects boot code */
1386                 /*     if gpnvm[1] == 0 */
1387                 /*         boot is via "SAMBA" (rom) */
1388                 /*     else */
1389                 /*         boot is via FLASH */
1390                 /*         Selection is via gpnvm[2] */
1391                 /*     endif */
1392                 /*  */
1393                 /* NOTE: banks 0 & 1 switch places */
1394                 /*     if gpnvm[2] == 0 */
1395                 /*         Bank0 is the boot rom */
1396                 /*      else */
1397                 /*         Bank1 is the boot rom */
1398                 /*      endif */
1399 /*              .bank[0] = { */
1400                 {
1401                         {
1402                                 .probed = 0,
1403                                 .pChip  = NULL,
1404                                 .pBank  = NULL,
1405                                 .bank_number = 0,
1406                                 .base_address = FLASH_BANK_BASE_N,
1407                                 .controller_address = 0x400e0A00,
1408                                 .flash_wait_states = 6, /* workaround silicon bug */
1409                                 .present = 1,
1410                                 .size_bytes = 64 * 1024,
1411                                 .nsectors   = 4,
1412                                 .sector_size = 16384,
1413                                 .page_size   = 256,
1414                         },
1415
1416 /*              .bank[1] = { */
1417                         {
1418                                 .present = 0,
1419                                 .probed = 0,
1420                                 .bank_number = 1,
1421                         },
1422                 },
1423         },
1424
1425         /* Start at91sam3a series*/
1426         /* System boots at address 0x0 */
1427         /* gpnvm[1] = selects boot code */
1428         /*     if gpnvm[1] == 0 */
1429         /*         boot is via "SAMBA" (rom) */
1430         /*     else */
1431         /*         boot is via FLASH */
1432         /*         Selection is via gpnvm[2] */
1433         /*     endif */
1434         /*  */
1435         /* NOTE: banks 0 & 1 switch places */
1436         /*     if gpnvm[2] == 0 */
1437         /*         Bank0 is the boot rom */
1438         /*      else */
1439         /*         Bank1 is the boot rom */
1440         /*      endif */
1441
1442         {
1443                 .chipid_cidr    = 0x283E0A60,
1444                 .name           = "at91sam3a8c",
1445                 .total_flash_size     = 512 * 1024,
1446                 .total_sram_size      = 96 * 1024,
1447                 .n_gpnvms       = 3,
1448                 .n_banks        = 2,
1449                 {
1450 /*              .bank[0] = { */
1451                   {
1452                         .probed = 0,
1453                         .pChip  = NULL,
1454                         .pBank  = NULL,
1455                         .bank_number = 0,
1456                         .base_address = FLASH_BANK0_BASE_AX,
1457                         .controller_address = 0x400e0a00,
1458                         .flash_wait_states = 6, /* workaround silicon bug */
1459                         .present = 1,
1460                         .size_bytes =  256 * 1024,
1461                         .nsectors   =  16,
1462                         .sector_size = 16384,
1463                         .page_size   = 256,
1464                   },
1465 /*              .bank[1] = { */
1466                   {
1467                         .probed = 0,
1468                         .pChip  = NULL,
1469                         .pBank  = NULL,
1470                         .bank_number = 1,
1471                         .base_address = FLASH_BANK1_BASE_512K_AX,
1472                         .controller_address = 0x400e0c00,
1473                         .flash_wait_states = 6, /* workaround silicon bug */
1474                         .present = 1,
1475                         .size_bytes =  256 * 1024,
1476                         .nsectors   =  16,
1477                         .sector_size = 16384,
1478                         .page_size   = 256,
1479
1480                   },
1481                 },
1482         },
1483         {
1484                 .chipid_cidr    = 0x283B0960,
1485                 .name           = "at91sam3a4c",
1486                 .total_flash_size     = 256 * 1024,
1487                 .total_sram_size      = 64 * 1024,
1488                 .n_gpnvms       = 3,
1489                 .n_banks        = 2,
1490                 {
1491 /*              .bank[0] = { */
1492                   {
1493                         .probed = 0,
1494                         .pChip  = NULL,
1495                         .pBank  = NULL,
1496                         .bank_number = 0,
1497                         .base_address = FLASH_BANK0_BASE_AX,
1498                         .controller_address = 0x400e0a00,
1499                         .flash_wait_states = 6, /* workaround silicon bug */
1500                         .present = 1,
1501                         .size_bytes =  128 * 1024,
1502                         .nsectors   =  8,
1503                         .sector_size = 16384,
1504                         .page_size   = 256,
1505                   },
1506 /*              .bank[1] = { */
1507                   {
1508                         .probed = 0,
1509                         .pChip  = NULL,
1510                         .pBank  = NULL,
1511                         .bank_number = 1,
1512                         .base_address = FLASH_BANK1_BASE_256K_AX,
1513                         .controller_address = 0x400e0c00,
1514                         .flash_wait_states = 6, /* workaround silicon bug */
1515                         .present = 1,
1516                         .size_bytes =  128 * 1024,
1517                         .nsectors   =  8,
1518                         .sector_size = 16384,
1519                         .page_size   = 256,
1520
1521                   },
1522                 },
1523         },
1524
1525         /* Start at91sam3x* series */
1526         /* System boots at address 0x0 */
1527         /* gpnvm[1] = selects boot code */
1528         /*     if gpnvm[1] == 0 */
1529         /*         boot is via "SAMBA" (rom) */
1530         /*     else */
1531         /*         boot is via FLASH */
1532         /*         Selection is via gpnvm[2] */
1533         /*     endif */
1534         /*  */
1535         /* NOTE: banks 0 & 1 switch places */
1536         /*     if gpnvm[2] == 0 */
1537         /*         Bank0 is the boot rom */
1538         /*      else */
1539         /*         Bank1 is the boot rom */
1540         /*      endif */
1541         /*at91sam3x8h - ES has an incorrect CIDR of 0x286E0A20*/
1542         {
1543                 .chipid_cidr    = 0x286E0A20,
1544                 .name           = "at91sam3x8h - ES",
1545                 .total_flash_size     = 512 * 1024,
1546                 .total_sram_size      = 96 * 1024,
1547                 .n_gpnvms       = 3,
1548                 .n_banks        = 2,
1549                 {
1550 /*              .bank[0] = { */
1551                   {
1552                         .probed = 0,
1553                         .pChip  = NULL,
1554                         .pBank  = NULL,
1555                         .bank_number = 0,
1556                         .base_address = FLASH_BANK0_BASE_AX,
1557                         .controller_address = 0x400e0a00,
1558                         .flash_wait_states = 6, /* workaround silicon bug */
1559                         .present = 1,
1560                         .size_bytes =  256 * 1024,
1561                         .nsectors   =  16,
1562                         .sector_size = 16384,
1563                         .page_size   = 256,
1564                   },
1565 /*              .bank[1] = { */
1566                   {
1567                         .probed = 0,
1568                         .pChip  = NULL,
1569                         .pBank  = NULL,
1570                         .bank_number = 1,
1571                         .base_address = FLASH_BANK1_BASE_512K_AX,
1572                         .controller_address = 0x400e0c00,
1573                         .flash_wait_states = 6, /* workaround silicon bug */
1574                         .present = 1,
1575                         .size_bytes =  256 * 1024,
1576                         .nsectors   =  16,
1577                         .sector_size = 16384,
1578                         .page_size   = 256,
1579
1580                   },
1581                 },
1582         },
1583         /*at91sam3x8h - ES2 and up uses the correct CIDR of 0x286E0A60*/
1584         {
1585                 .chipid_cidr    = 0x286E0A60,
1586                 .name           = "at91sam3x8h",
1587                 .total_flash_size     = 512 * 1024,
1588                 .total_sram_size      = 96 * 1024,
1589                 .n_gpnvms       = 3,
1590                 .n_banks        = 2,
1591                 {
1592 /*              .bank[0] = { */
1593                   {
1594                         .probed = 0,
1595                         .pChip  = NULL,
1596                         .pBank  = NULL,
1597                         .bank_number = 0,
1598                         .base_address = FLASH_BANK0_BASE_AX,
1599                         .controller_address = 0x400e0a00,
1600                         .flash_wait_states = 6, /* workaround silicon bug */
1601                         .present = 1,
1602                         .size_bytes =  256 * 1024,
1603                         .nsectors   =  16,
1604                         .sector_size = 16384,
1605                         .page_size   = 256,
1606                   },
1607 /*              .bank[1] = { */
1608                   {
1609                         .probed = 0,
1610                         .pChip  = NULL,
1611                         .pBank  = NULL,
1612                         .bank_number = 1,
1613                         .base_address = FLASH_BANK1_BASE_512K_AX,
1614                         .controller_address = 0x400e0c00,
1615                         .flash_wait_states = 6, /* workaround silicon bug */
1616                         .present = 1,
1617                         .size_bytes =  256 * 1024,
1618                         .nsectors   =  16,
1619                         .sector_size = 16384,
1620                         .page_size   = 256,
1621
1622                   },
1623                 },
1624         },
1625         {
1626                 .chipid_cidr    = 0x285E0A60,
1627                 .name           = "at91sam3x8e",
1628                 .total_flash_size     = 512 * 1024,
1629                 .total_sram_size      = 96 * 1024,
1630                 .n_gpnvms       = 3,
1631                 .n_banks        = 2,
1632                 {
1633 /*              .bank[0] = { */
1634                   {
1635                         .probed = 0,
1636                         .pChip  = NULL,
1637                         .pBank  = NULL,
1638                         .bank_number = 0,
1639                         .base_address = FLASH_BANK0_BASE_AX,
1640                         .controller_address = 0x400e0a00,
1641                         .flash_wait_states = 6, /* workaround silicon bug */
1642                         .present = 1,
1643                         .size_bytes =  256 * 1024,
1644                         .nsectors   =  16,
1645                         .sector_size = 16384,
1646                         .page_size   = 256,
1647                   },
1648 /*              .bank[1] = { */
1649                   {
1650                         .probed = 0,
1651                         .pChip  = NULL,
1652                         .pBank  = NULL,
1653                         .bank_number = 1,
1654                         .base_address = FLASH_BANK1_BASE_512K_AX,
1655                         .controller_address = 0x400e0c00,
1656                         .flash_wait_states = 6, /* workaround silicon bug */
1657                         .present = 1,
1658                         .size_bytes =  256 * 1024,
1659                         .nsectors   =  16,
1660                         .sector_size = 16384,
1661                         .page_size   = 256,
1662
1663                   },
1664                 },
1665         },
1666         {
1667                 .chipid_cidr    = 0x284E0A60,
1668                 .name           = "at91sam3x8c",
1669                 .total_flash_size     = 512 * 1024,
1670                 .total_sram_size      = 96 * 1024,
1671                 .n_gpnvms       = 3,
1672                 .n_banks        = 2,
1673                 {
1674 /*              .bank[0] = { */
1675                   {
1676                         .probed = 0,
1677                         .pChip  = NULL,
1678                         .pBank  = NULL,
1679                         .bank_number = 0,
1680                         .base_address = FLASH_BANK0_BASE_AX,
1681                         .controller_address = 0x400e0a00,
1682                         .flash_wait_states = 6, /* workaround silicon bug */
1683                         .present = 1,
1684                         .size_bytes =  256 * 1024,
1685                         .nsectors   =  16,
1686                         .sector_size = 16384,
1687                         .page_size   = 256,
1688                   },
1689 /*              .bank[1] = { */
1690                   {
1691                         .probed = 0,
1692                         .pChip  = NULL,
1693                         .pBank  = NULL,
1694                         .bank_number = 1,
1695                         .base_address = FLASH_BANK1_BASE_512K_AX ,
1696                         .controller_address = 0x400e0c00,
1697                         .flash_wait_states = 6, /* workaround silicon bug */
1698                         .present = 1,
1699                         .size_bytes =  256 * 1024,
1700                         .nsectors   =  16,
1701                         .sector_size = 16384,
1702                         .page_size   = 256,
1703
1704                   },
1705                 },
1706         },
1707         {
1708                 .chipid_cidr    = 0x285B0960,
1709                 .name           = "at91sam3x4e",
1710                 .total_flash_size     = 256 * 1024,
1711                 .total_sram_size      = 64 * 1024,
1712                 .n_gpnvms       = 3,
1713                 .n_banks        = 2,
1714                 {
1715 /*              .bank[0] = { */
1716                   {
1717                         .probed = 0,
1718                         .pChip  = NULL,
1719                         .pBank  = NULL,
1720                         .bank_number = 0,
1721                         .base_address = FLASH_BANK0_BASE_AX,
1722                         .controller_address = 0x400e0a00,
1723                         .flash_wait_states = 6, /* workaround silicon bug */
1724                         .present = 1,
1725                         .size_bytes =  128 * 1024,
1726                         .nsectors   =  8,
1727                         .sector_size = 16384,
1728                         .page_size   = 256,
1729                   },
1730 /*              .bank[1] = { */
1731                   {
1732                         .probed = 0,
1733                         .pChip  = NULL,
1734                         .pBank  = NULL,
1735                         .bank_number = 1,
1736                         .base_address = FLASH_BANK1_BASE_256K_AX,
1737                         .controller_address = 0x400e0c00,
1738                         .flash_wait_states = 6, /* workaround silicon bug */
1739                         .present = 1,
1740                         .size_bytes =  128 * 1024,
1741                         .nsectors   =  8,
1742                         .sector_size = 16384,
1743                         .page_size   = 256,
1744
1745                   },
1746                 },
1747         },
1748         {
1749                 .chipid_cidr    = 0x284B0960,
1750                 .name           = "at91sam3x4c",
1751                 .total_flash_size     = 256 * 1024,
1752                 .total_sram_size      = 64 * 1024,
1753                 .n_gpnvms       = 3,
1754                 .n_banks        = 2,
1755                 {
1756 /*              .bank[0] = { */
1757                   {
1758                         .probed = 0,
1759                         .pChip  = NULL,
1760                         .pBank  = NULL,
1761                         .bank_number = 0,
1762                         .base_address = FLASH_BANK0_BASE_AX,
1763                         .controller_address = 0x400e0a00,
1764                         .flash_wait_states = 6, /* workaround silicon bug */
1765                         .present = 1,
1766                         .size_bytes =  128 * 1024,
1767                         .nsectors   =  8,
1768                         .sector_size = 16384,
1769                         .page_size   = 256,
1770                   },
1771 /*              .bank[1] = { */
1772                   {
1773                         .probed = 0,
1774                         .pChip  = NULL,
1775                         .pBank  = NULL,
1776                         .bank_number = 1,
1777                         .base_address = FLASH_BANK1_BASE_256K_AX,
1778                         .controller_address = 0x400e0c00,
1779                         .flash_wait_states = 6, /* workaround silicon bug */
1780                         .present = 1,
1781                         .size_bytes =  128 * 1024,
1782                         .nsectors   =  8,
1783                         .sector_size = 16384,
1784                         .page_size   = 256,
1785
1786                   },
1787                 },
1788         },
1789         /* terminate */
1790         {
1791                 .chipid_cidr    = 0,
1792                 .name                   = NULL,
1793         }
1794 };
1795
1796 /* Globals above */
1797 /***********************************************************************
1798  **********************************************************************
1799  **********************************************************************
1800  **********************************************************************
1801  **********************************************************************
1802  **********************************************************************/
1803 /* *ATMEL* style code - from the SAM3 driver code */
1804
1805 /**
1806  * Get the current status of the EEFC and
1807  * the value of some status bits (LOCKE, PROGE).
1808  * @param pPrivate - info about the bank
1809  * @param v        - result goes here
1810  */
1811 static int EFC_GetStatus(struct sam3_bank_private *pPrivate, uint32_t *v)
1812 {
1813         int r;
1814         r = target_read_u32(pPrivate->pChip->target,
1815                         pPrivate->controller_address + offset_EFC_FSR,
1816                         v);
1817         LOG_DEBUG("Status: 0x%08x (lockerror: %d, cmderror: %d, ready: %d)",
1818                 (unsigned int)(*v),
1819                 ((unsigned int)((*v >> 2) & 1)),
1820                 ((unsigned int)((*v >> 1) & 1)),
1821                 ((unsigned int)((*v >> 0) & 1)));
1822
1823         return r;
1824 }
1825
1826 /**
1827  * Get the result of the last executed command.
1828  * @param pPrivate - info about the bank
1829  * @param v        - result goes here
1830  */
1831 static int EFC_GetResult(struct sam3_bank_private *pPrivate, uint32_t *v)
1832 {
1833         int r;
1834         uint32_t rv;
1835         r = target_read_u32(pPrivate->pChip->target,
1836                         pPrivate->controller_address + offset_EFC_FRR,
1837                         &rv);
1838         if (v)
1839                 *v = rv;
1840         LOG_DEBUG("Result: 0x%08x", ((unsigned int)(rv)));
1841         return r;
1842 }
1843
1844 static int EFC_StartCommand(struct sam3_bank_private *pPrivate,
1845         unsigned command, unsigned argument)
1846 {
1847         uint32_t n, v;
1848         int r;
1849         int retry;
1850
1851         retry = 0;
1852 do_retry:
1853
1854         /* Check command & argument */
1855         switch (command) {
1856
1857                 case AT91C_EFC_FCMD_WP:
1858                 case AT91C_EFC_FCMD_WPL:
1859                 case AT91C_EFC_FCMD_EWP:
1860                 case AT91C_EFC_FCMD_EWPL:
1861                 /* case AT91C_EFC_FCMD_EPL: */
1862                 /* case AT91C_EFC_FCMD_EPA: */
1863                 case AT91C_EFC_FCMD_SLB:
1864                 case AT91C_EFC_FCMD_CLB:
1865                         n = (pPrivate->size_bytes / pPrivate->page_size);
1866                         if (argument >= n)
1867                                 LOG_ERROR("*BUG*: Embedded flash has only %u pages", (unsigned)(n));
1868                         break;
1869
1870                 case AT91C_EFC_FCMD_SFB:
1871                 case AT91C_EFC_FCMD_CFB:
1872                         if (argument >= pPrivate->pChip->details.n_gpnvms) {
1873                                 LOG_ERROR("*BUG*: Embedded flash has only %d GPNVMs",
1874                                                 pPrivate->pChip->details.n_gpnvms);
1875                         }
1876                         break;
1877
1878                 case AT91C_EFC_FCMD_GETD:
1879                 case AT91C_EFC_FCMD_EA:
1880                 case AT91C_EFC_FCMD_GLB:
1881                 case AT91C_EFC_FCMD_GFB:
1882                 case AT91C_EFC_FCMD_STUI:
1883                 case AT91C_EFC_FCMD_SPUI:
1884                         if (argument != 0)
1885                                 LOG_ERROR("Argument is meaningless for cmd: %d", command);
1886                         break;
1887                 default:
1888                         LOG_ERROR("Unknown command %d", command);
1889                         break;
1890         }
1891
1892         if (command == AT91C_EFC_FCMD_SPUI) {
1893                 /* this is a very special situation. */
1894                 /* Situation (1) - error/retry - see below */
1895                 /*      And we are being called recursively */
1896                 /* Situation (2) - normal, finished reading unique id */
1897         } else {
1898                 /* it should be "ready" */
1899                 EFC_GetStatus(pPrivate, &v);
1900                 if (v & 1) {
1901                         /* then it is ready */
1902                         /* we go on */
1903                 } else {
1904                         if (retry) {
1905                                 /* we have done this before */
1906                                 /* the controller is not responding. */
1907                                 LOG_ERROR("flash controller(%d) is not ready! Error",
1908                                         pPrivate->bank_number);
1909                                 return ERROR_FAIL;
1910                         } else {
1911                                 retry++;
1912                                 LOG_ERROR("Flash controller(%d) is not ready, attempting reset",
1913                                         pPrivate->bank_number);
1914                                 /* we do that by issuing the *STOP* command */
1915                                 EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0);
1916                                 /* above is recursive, and further recursion is blocked by */
1917                                 /* if (command == AT91C_EFC_FCMD_SPUI) above */
1918                                 goto do_retry;
1919                         }
1920                 }
1921         }
1922
1923         v = (0x5A << 24) | (argument << 8) | command;
1924         LOG_DEBUG("Command: 0x%08x", ((unsigned int)(v)));
1925         r = target_write_u32(pPrivate->pBank->target,
1926                         pPrivate->controller_address + offset_EFC_FCR, v);
1927         if (r != ERROR_OK)
1928                 LOG_DEBUG("Error Write failed");
1929         return r;
1930 }
1931
1932 /**
1933  * Performs the given command and wait until its completion (or an error).
1934  * @param pPrivate - info about the bank
1935  * @param command  - Command to perform.
1936  * @param argument - Optional command argument.
1937  * @param status   - put command status bits here
1938  */
1939 static int EFC_PerformCommand(struct sam3_bank_private *pPrivate,
1940         unsigned command,
1941         unsigned argument,
1942         uint32_t *status)
1943 {
1944
1945         int r;
1946         uint32_t v;
1947         long long ms_now, ms_end;
1948
1949         /* default */
1950         if (status)
1951                 *status = 0;
1952
1953         r = EFC_StartCommand(pPrivate, command, argument);
1954         if (r != ERROR_OK)
1955                 return r;
1956
1957         ms_end = 500 + timeval_ms();
1958
1959         do {
1960                 r = EFC_GetStatus(pPrivate, &v);
1961                 if (r != ERROR_OK)
1962                         return r;
1963                 ms_now = timeval_ms();
1964                 if (ms_now > ms_end) {
1965                         /* error */
1966                         LOG_ERROR("Command timeout");
1967                         return ERROR_FAIL;
1968                 }
1969         } while ((v & 1) == 0);
1970
1971         /* error bits.. */
1972         if (status)
1973                 *status = (v & 0x6);
1974         return ERROR_OK;
1975
1976 }
1977
1978 /**
1979  * Read the unique ID.
1980  * @param pPrivate - info about the bank
1981  * The unique ID is stored in the 'pPrivate' structure.
1982  */
1983 static int FLASHD_ReadUniqueID(struct sam3_bank_private *pPrivate)
1984 {
1985         int r;
1986         uint32_t v;
1987         int x;
1988         /* assume 0 */
1989         pPrivate->pChip->cfg.unique_id[0] = 0;
1990         pPrivate->pChip->cfg.unique_id[1] = 0;
1991         pPrivate->pChip->cfg.unique_id[2] = 0;
1992         pPrivate->pChip->cfg.unique_id[3] = 0;
1993
1994         LOG_DEBUG("Begin");
1995         r = EFC_StartCommand(pPrivate, AT91C_EFC_FCMD_STUI, 0);
1996         if (r < 0)
1997                 return r;
1998
1999         for (x = 0; x < 4; x++) {
2000                 r = target_read_u32(pPrivate->pChip->target,
2001                                 pPrivate->pBank->base + (x * 4),
2002                                 &v);
2003                 if (r < 0)
2004                         return r;
2005                 pPrivate->pChip->cfg.unique_id[x] = v;
2006         }
2007
2008         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SPUI, 0, NULL);
2009         LOG_DEBUG("End: R=%d, id = 0x%08x, 0x%08x, 0x%08x, 0x%08x",
2010                 r,
2011                 (unsigned int)(pPrivate->pChip->cfg.unique_id[0]),
2012                 (unsigned int)(pPrivate->pChip->cfg.unique_id[1]),
2013                 (unsigned int)(pPrivate->pChip->cfg.unique_id[2]),
2014                 (unsigned int)(pPrivate->pChip->cfg.unique_id[3]));
2015         return r;
2016
2017 }
2018
2019 /**
2020  * Erases the entire flash.
2021  * @param pPrivate - the info about the bank.
2022  */
2023 static int FLASHD_EraseEntireBank(struct sam3_bank_private *pPrivate)
2024 {
2025         LOG_DEBUG("Here");
2026         return EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_EA, 0, NULL);
2027 }
2028
2029 /**
2030  * Gets current GPNVM state.
2031  * @param pPrivate - info about the bank.
2032  * @param gpnvm    -  GPNVM bit index.
2033  * @param puthere  - result stored here.
2034  */
2035 /* ------------------------------------------------------------------------------ */
2036 static int FLASHD_GetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm, unsigned *puthere)
2037 {
2038         uint32_t v;
2039         int r;
2040
2041         LOG_DEBUG("Here");
2042         if (pPrivate->bank_number != 0) {
2043                 LOG_ERROR("GPNVM only works with Bank0");
2044                 return ERROR_FAIL;
2045         }
2046
2047         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2048                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2049                         gpnvm, pPrivate->pChip->details.n_gpnvms);
2050                 return ERROR_FAIL;
2051         }
2052
2053         /* Get GPNVMs status */
2054         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GFB, 0, NULL);
2055         if (r != ERROR_OK) {
2056                 LOG_ERROR("Failed");
2057                 return r;
2058         }
2059
2060         r = EFC_GetResult(pPrivate, &v);
2061
2062         if (puthere) {
2063                 /* Check if GPNVM is set */
2064                 /* get the bit and make it a 0/1 */
2065                 *puthere = (v >> gpnvm) & 1;
2066         }
2067
2068         return r;
2069 }
2070
2071 /**
2072  * Clears the selected GPNVM bit.
2073  * @param pPrivate info about the bank
2074  * @param gpnvm GPNVM index.
2075  * @returns 0 if successful; otherwise returns an error code.
2076  */
2077 static int FLASHD_ClrGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2078 {
2079         int r;
2080         unsigned v;
2081
2082         LOG_DEBUG("Here");
2083         if (pPrivate->bank_number != 0) {
2084                 LOG_ERROR("GPNVM only works with Bank0");
2085                 return ERROR_FAIL;
2086         }
2087
2088         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2089                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2090                         gpnvm, pPrivate->pChip->details.n_gpnvms);
2091                 return ERROR_FAIL;
2092         }
2093
2094         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2095         if (r != ERROR_OK) {
2096                 LOG_DEBUG("Failed: %d", r);
2097                 return r;
2098         }
2099         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CFB, gpnvm, NULL);
2100         LOG_DEBUG("End: %d", r);
2101         return r;
2102 }
2103
2104 /**
2105  * Sets the selected GPNVM bit.
2106  * @param pPrivate info about the bank
2107  * @param gpnvm GPNVM index.
2108  */
2109 static int FLASHD_SetGPNVM(struct sam3_bank_private *pPrivate, unsigned gpnvm)
2110 {
2111         int r;
2112         unsigned v;
2113
2114         if (pPrivate->bank_number != 0) {
2115                 LOG_ERROR("GPNVM only works with Bank0");
2116                 return ERROR_FAIL;
2117         }
2118
2119         if (gpnvm >= pPrivate->pChip->details.n_gpnvms) {
2120                 LOG_ERROR("Invalid GPNVM %d, max: %d, ignored",
2121                         gpnvm, pPrivate->pChip->details.n_gpnvms);
2122                 return ERROR_FAIL;
2123         }
2124
2125         r = FLASHD_GetGPNVM(pPrivate, gpnvm, &v);
2126         if (r != ERROR_OK)
2127                 return r;
2128         if (v) {
2129                 /* already set */
2130                 r = ERROR_OK;
2131         } else {
2132                 /* set it */
2133                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SFB, gpnvm, NULL);
2134         }
2135         return r;
2136 }
2137
2138 /**
2139  * Returns a bit field (at most 64) of locked regions within a page.
2140  * @param pPrivate info about the bank
2141  * @param v where to store locked bits
2142  */
2143 static int FLASHD_GetLockBits(struct sam3_bank_private *pPrivate, uint32_t *v)
2144 {
2145         int r;
2146         LOG_DEBUG("Here");
2147         r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_GLB, 0, NULL);
2148         if (r == ERROR_OK)
2149                 r = EFC_GetResult(pPrivate, v);
2150         LOG_DEBUG("End: %d", r);
2151         return r;
2152 }
2153
2154 /**
2155  * Unlocks all the regions in the given address range.
2156  * @param pPrivate info about the bank
2157  * @param start_sector first sector to unlock
2158  * @param end_sector last (inclusive) to unlock
2159  */
2160
2161 static int FLASHD_Unlock(struct sam3_bank_private *pPrivate,
2162         unsigned start_sector,
2163         unsigned end_sector)
2164 {
2165         int r;
2166         uint32_t status;
2167         uint32_t pg;
2168         uint32_t pages_per_sector;
2169
2170         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2171
2172         /* Unlock all pages */
2173         while (start_sector <= end_sector) {
2174                 pg = start_sector * pages_per_sector;
2175
2176                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_CLB, pg, &status);
2177                 if (r != ERROR_OK)
2178                         return r;
2179                 start_sector++;
2180         }
2181
2182         return ERROR_OK;
2183 }
2184
2185 /**
2186  * Locks regions
2187  * @param pPrivate - info about the bank
2188  * @param start_sector - first sector to lock
2189  * @param end_sector   - last sector (inclusive) to lock
2190  */
2191 static int FLASHD_Lock(struct sam3_bank_private *pPrivate,
2192         unsigned start_sector,
2193         unsigned end_sector)
2194 {
2195         uint32_t status;
2196         uint32_t pg;
2197         uint32_t pages_per_sector;
2198         int r;
2199
2200         pages_per_sector = pPrivate->sector_size / pPrivate->page_size;
2201
2202         /* Lock all pages */
2203         while (start_sector <= end_sector) {
2204                 pg = start_sector * pages_per_sector;
2205
2206                 r = EFC_PerformCommand(pPrivate, AT91C_EFC_FCMD_SLB, pg, &status);
2207                 if (r != ERROR_OK)
2208                         return r;
2209                 start_sector++;
2210         }
2211         return ERROR_OK;
2212 }
2213
2214 /****** END SAM3 CODE ********/
2215
2216 /* begin helpful debug code */
2217 /* print the fieldname, the field value, in dec & hex, and return field value */
2218 static uint32_t sam3_reg_fieldname(struct sam3_chip *pChip,
2219         const char *regname,
2220         uint32_t value,
2221         unsigned shift,
2222         unsigned width)
2223 {
2224         uint32_t v;
2225         int hwidth, dwidth;
2226
2227
2228         /* extract the field */
2229         v = value >> shift;
2230         v = v & ((1 << width)-1);
2231         if (width <= 16) {
2232                 hwidth = 4;
2233                 dwidth = 5;
2234         } else {
2235                 hwidth = 8;
2236                 dwidth = 12;
2237         }
2238
2239         /* show the basics */
2240         LOG_USER_N("\t%*s: %*d [0x%0*x] ",
2241                 REG_NAME_WIDTH, regname,
2242                 dwidth, v,
2243                 hwidth, v);
2244         return v;
2245 }
2246
2247 static const char _unknown[] = "unknown";
2248 static const char *const eproc_names[] = {
2249         _unknown,                                       /* 0 */
2250         "arm946es",                                     /* 1 */
2251         "arm7tdmi",                                     /* 2 */
2252         "cortex-m3",                            /* 3 */
2253         "arm920t",                                      /* 4 */
2254         "arm926ejs",                            /* 5 */
2255         _unknown,                                       /* 6 */
2256         _unknown,                                       /* 7 */
2257         _unknown,                                       /* 8 */
2258         _unknown,                                       /* 9 */
2259         _unknown,                                       /* 10 */
2260         _unknown,                                       /* 11 */
2261         _unknown,                                       /* 12 */
2262         _unknown,                                       /* 13 */
2263         _unknown,                                       /* 14 */
2264         _unknown,                                       /* 15 */
2265 };
2266
2267 #define nvpsize2 nvpsize                /* these two tables are identical */
2268 static const char *const nvpsize[] = {
2269         "none",                                         /*  0 */
2270         "8K bytes",                                     /*  1 */
2271         "16K bytes",                            /*  2 */
2272         "32K bytes",                            /*  3 */
2273         _unknown,                                       /*  4 */
2274         "64K bytes",                            /*  5 */
2275         _unknown,                                       /*  6 */
2276         "128K bytes",                           /*  7 */
2277         _unknown,                                       /*  8 */
2278         "256K bytes",                           /*  9 */
2279         "512K bytes",                           /* 10 */
2280         _unknown,                                       /* 11 */
2281         "1024K bytes",                          /* 12 */
2282         _unknown,                                       /* 13 */
2283         "2048K bytes",                          /* 14 */
2284         _unknown,                                       /* 15 */
2285 };
2286
2287 static const char *const sramsize[] = {
2288         "48K Bytes",                            /*  0 */
2289         "1K Bytes",                                     /*  1 */
2290         "2K Bytes",                                     /*  2 */
2291         "6K Bytes",                                     /*  3 */
2292         "112K Bytes",                           /*  4 */
2293         "4K Bytes",                                     /*  5 */
2294         "80K Bytes",                            /*  6 */
2295         "160K Bytes",                           /*  7 */
2296         "8K Bytes",                                     /*  8 */
2297         "16K Bytes",                            /*  9 */
2298         "32K Bytes",                            /* 10 */
2299         "64K Bytes",                            /* 11 */
2300         "128K Bytes",                           /* 12 */
2301         "256K Bytes",                           /* 13 */
2302         "96K Bytes",                            /* 14 */
2303         "512K Bytes",                           /* 15 */
2304
2305 };
2306
2307 static const struct archnames { unsigned value; const char *name; } archnames[] = {
2308         { 0x19,  "AT91SAM9xx Series"                                            },
2309         { 0x29,  "AT91SAM9XExx Series"                                          },
2310         { 0x34,  "AT91x34 Series"                                                       },
2311         { 0x37,  "CAP7 Series"                                                          },
2312         { 0x39,  "CAP9 Series"                                                          },
2313         { 0x3B,  "CAP11 Series"                                                         },
2314         { 0x40,  "AT91x40 Series"                                                       },
2315         { 0x42,  "AT91x42 Series"                                                       },
2316         { 0x55,  "AT91x55 Series"                                                       },
2317         { 0x60,  "AT91SAM7Axx Series"                                           },
2318         { 0x61,  "AT91SAM7AQxx Series"                                          },
2319         { 0x63,  "AT91x63 Series"                                                       },
2320         { 0x70,  "AT91SAM7Sxx Series"                                           },
2321         { 0x71,  "AT91SAM7XCxx Series"                                          },
2322         { 0x72,  "AT91SAM7SExx Series"                                          },
2323         { 0x73,  "AT91SAM7Lxx Series"                                           },
2324         { 0x75,  "AT91SAM7Xxx Series"                                           },
2325         { 0x76,  "AT91SAM7SLxx Series"                                          },
2326         { 0x80,  "ATSAM3UxC Series (100-pin version)"           },
2327         { 0x81,  "ATSAM3UxE Series (144-pin version)"           },
2328         { 0x83,  "ATSAM3AxC Series (100-pin version)"           },
2329         { 0x84,  "ATSAM3XxC Series (100-pin version)"           },
2330         { 0x85,  "ATSAM3XxE Series (144-pin version)"           },
2331         { 0x86,  "ATSAM3XxG Series (208/217-pin version)"       },
2332         { 0x88,  "ATSAM3SxA Series (48-pin version)"            },
2333         { 0x89,  "ATSAM3SxB Series (64-pin version)"            },
2334         { 0x8A,  "ATSAM3SxC Series (100-pin version)"           },
2335         { 0x92,  "AT91x92 Series"                                                       },
2336         { 0x93,  "ATSAM3NxA Series (48-pin version)"            },
2337         { 0x94,  "ATSAM3NxB Series (64-pin version)"            },
2338         { 0x95,  "ATSAM3NxC Series (100-pin version)"           },
2339         { 0x98,  "ATSAM3SDxA Series (48-pin version)"           },
2340         { 0x99,  "ATSAM3SDxB Series (64-pin version)"           },
2341         { 0x9A,  "ATSAM3SDxC Series (100-pin version)"          },
2342         { 0xA5,  "ATSAM5A"                                                              },
2343         { 0xF0,  "AT75Cxx Series"                                                       },
2344         { -1, NULL },
2345 };
2346
2347 static const char *const nvptype[] = {
2348         "rom",  /* 0 */
2349         "romless or onchip flash",      /* 1 */
2350         "embedded flash memory",/* 2 */
2351         "rom(nvpsiz) + embedded flash (nvpsiz2)",       /* 3 */
2352         "sram emulating flash", /* 4 */
2353         _unknown,       /* 5 */
2354         _unknown,       /* 6 */
2355         _unknown,       /* 7 */
2356 };
2357
2358 static const char *_yes_or_no(uint32_t v)
2359 {
2360         if (v)
2361                 return "YES";
2362         else
2363                 return "NO";
2364 }
2365
2366 static const char *const _rc_freq[] = {
2367         "4 MHz", "8 MHz", "12 MHz", "reserved"
2368 };
2369
2370 static void sam3_explain_ckgr_mor(struct sam3_chip *pChip)
2371 {
2372         uint32_t v;
2373         uint32_t rcen;
2374
2375         v = sam3_reg_fieldname(pChip, "MOSCXTEN", pChip->cfg.CKGR_MOR, 0, 1);
2376         LOG_USER("(main xtal enabled: %s)", _yes_or_no(v));
2377         v = sam3_reg_fieldname(pChip, "MOSCXTBY", pChip->cfg.CKGR_MOR, 1, 1);
2378         LOG_USER("(main osc bypass: %s)", _yes_or_no(v));
2379         rcen = sam3_reg_fieldname(pChip, "MOSCRCEN", pChip->cfg.CKGR_MOR, 3, 1);
2380         LOG_USER("(onchip RC-OSC enabled: %s)", _yes_or_no(rcen));
2381         v = sam3_reg_fieldname(pChip, "MOSCRCF", pChip->cfg.CKGR_MOR, 4, 3);
2382         LOG_USER("(onchip RC-OSC freq: %s)", _rc_freq[v]);
2383
2384         pChip->cfg.rc_freq = 0;
2385         if (rcen) {
2386                 switch (v) {
2387                         default:
2388                                 pChip->cfg.rc_freq = 0;
2389                                 break;
2390                         case 0:
2391                                 pChip->cfg.rc_freq = 4 * 1000 * 1000;
2392                                 break;
2393                         case 1:
2394                                 pChip->cfg.rc_freq = 8 * 1000 * 1000;
2395                                 break;
2396                         case 2:
2397                                 pChip->cfg.rc_freq = 12 * 1000 * 1000;
2398                                 break;
2399                 }
2400         }
2401
2402         v = sam3_reg_fieldname(pChip, "MOSCXTST", pChip->cfg.CKGR_MOR, 8, 8);
2403         LOG_USER("(startup clks, time= %f uSecs)",
2404                 ((float)(v * 1000000)) / ((float)(pChip->cfg.slow_freq)));
2405         v = sam3_reg_fieldname(pChip, "MOSCSEL", pChip->cfg.CKGR_MOR, 24, 1);
2406         LOG_USER("(mainosc source: %s)",
2407                 v ? "external xtal" : "internal RC");
2408
2409         v = sam3_reg_fieldname(pChip, "CFDEN", pChip->cfg.CKGR_MOR, 25, 1);
2410         LOG_USER("(clock failure enabled: %s)",
2411                 _yes_or_no(v));
2412 }
2413
2414 static void sam3_explain_chipid_cidr(struct sam3_chip *pChip)
2415 {
2416         int x;
2417         uint32_t v;
2418         const char *cp;
2419
2420         sam3_reg_fieldname(pChip, "Version", pChip->cfg.CHIPID_CIDR, 0, 5);
2421         LOG_USER_N("\n");
2422
2423         v = sam3_reg_fieldname(pChip, "EPROC", pChip->cfg.CHIPID_CIDR, 5, 3);
2424         LOG_USER("%s", eproc_names[v]);
2425
2426         v = sam3_reg_fieldname(pChip, "NVPSIZE", pChip->cfg.CHIPID_CIDR, 8, 4);
2427         LOG_USER("%s", nvpsize[v]);
2428
2429         v = sam3_reg_fieldname(pChip, "NVPSIZE2", pChip->cfg.CHIPID_CIDR, 12, 4);
2430         LOG_USER("%s", nvpsize2[v]);
2431
2432         v = sam3_reg_fieldname(pChip, "SRAMSIZE", pChip->cfg.CHIPID_CIDR, 16, 4);
2433         LOG_USER("%s", sramsize[v]);
2434
2435         v = sam3_reg_fieldname(pChip, "ARCH", pChip->cfg.CHIPID_CIDR, 20, 8);
2436         cp = _unknown;
2437         for (x = 0; archnames[x].name; x++) {
2438                 if (v == archnames[x].value) {
2439                         cp = archnames[x].name;
2440                         break;
2441                 }
2442         }
2443
2444         LOG_USER("%s", cp);
2445
2446         v = sam3_reg_fieldname(pChip, "NVPTYP", pChip->cfg.CHIPID_CIDR, 28, 3);
2447         LOG_USER("%s", nvptype[v]);
2448
2449         v = sam3_reg_fieldname(pChip, "EXTID", pChip->cfg.CHIPID_CIDR, 31, 1);
2450         LOG_USER("(exists: %s)", _yes_or_no(v));
2451 }
2452
2453 static void sam3_explain_ckgr_mcfr(struct sam3_chip *pChip)
2454 {
2455         uint32_t v;
2456
2457         v = sam3_reg_fieldname(pChip, "MAINFRDY", pChip->cfg.CKGR_MCFR, 16, 1);
2458         LOG_USER("(main ready: %s)", _yes_or_no(v));
2459
2460         v = sam3_reg_fieldname(pChip, "MAINF", pChip->cfg.CKGR_MCFR, 0, 16);
2461
2462         v = (v * pChip->cfg.slow_freq) / 16;
2463         pChip->cfg.mainosc_freq = v;
2464
2465         LOG_USER("(%3.03f Mhz (%d.%03dkhz slowclk)",
2466                 _tomhz(v),
2467                 pChip->cfg.slow_freq / 1000,
2468                 pChip->cfg.slow_freq % 1000);
2469 }
2470
2471 static void sam3_explain_ckgr_plla(struct sam3_chip *pChip)
2472 {
2473         uint32_t mula, diva;
2474
2475         diva = sam3_reg_fieldname(pChip, "DIVA", pChip->cfg.CKGR_PLLAR, 0, 8);
2476         LOG_USER_N("\n");
2477         mula = sam3_reg_fieldname(pChip, "MULA", pChip->cfg.CKGR_PLLAR, 16, 11);
2478         LOG_USER_N("\n");
2479         pChip->cfg.plla_freq = 0;
2480         if (mula == 0)
2481                 LOG_USER("\tPLLA Freq: (Disabled,mula = 0)");
2482         else if (diva == 0)
2483                 LOG_USER("\tPLLA Freq: (Disabled,diva = 0)");
2484         else if (diva >= 1) {
2485                 pChip->cfg.plla_freq = (pChip->cfg.mainosc_freq * (mula + 1) / diva);
2486                 LOG_USER("\tPLLA Freq: %3.03f MHz",
2487                         _tomhz(pChip->cfg.plla_freq));
2488         }
2489 }
2490
2491 static void sam3_explain_mckr(struct sam3_chip *pChip)
2492 {
2493         uint32_t css, pres, fin = 0;
2494         int pdiv = 0;
2495         const char *cp = NULL;
2496
2497         css = sam3_reg_fieldname(pChip, "CSS", pChip->cfg.PMC_MCKR, 0, 2);
2498         switch (css & 3) {
2499                 case 0:
2500                         fin = pChip->cfg.slow_freq;
2501                         cp = "slowclk";
2502                         break;
2503                 case 1:
2504                         fin = pChip->cfg.mainosc_freq;
2505                         cp  = "mainosc";
2506                         break;
2507                 case 2:
2508                         fin = pChip->cfg.plla_freq;
2509                         cp  = "plla";
2510                         break;
2511                 case 3:
2512                         if (pChip->cfg.CKGR_UCKR & (1 << 16)) {
2513                                 fin = 480 * 1000 * 1000;
2514                                 cp = "upll";
2515                         } else {
2516                                 fin = 0;
2517                                 cp  = "upll (*ERROR* UPLL is disabled)";
2518                         }
2519                         break;
2520                 default:
2521                         assert(0);
2522                         break;
2523         }
2524
2525         LOG_USER("%s (%3.03f Mhz)",
2526                 cp,
2527                 _tomhz(fin));
2528         pres = sam3_reg_fieldname(pChip, "PRES", pChip->cfg.PMC_MCKR, 4, 3);
2529         switch (pres & 0x07) {
2530                 case 0:
2531                         pdiv = 1;
2532                         cp = "selected clock";
2533                         break;
2534                 case 1:
2535                         pdiv = 2;
2536                         cp = "clock/2";
2537                         break;
2538                 case 2:
2539                         pdiv = 4;
2540                         cp = "clock/4";
2541                         break;
2542                 case 3:
2543                         pdiv = 8;
2544                         cp = "clock/8";
2545                         break;
2546                 case 4:
2547                         pdiv = 16;
2548                         cp = "clock/16";
2549                         break;
2550                 case 5:
2551                         pdiv = 32;
2552                         cp = "clock/32";
2553                         break;
2554                 case 6:
2555                         pdiv = 64;
2556                         cp = "clock/64";
2557                         break;
2558                 case 7:
2559                         pdiv = 6;
2560                         cp = "clock/6";
2561                         break;
2562                 default:
2563                         assert(0);
2564                         break;
2565         }
2566         LOG_USER("(%s)", cp);
2567         fin = fin / pdiv;
2568         /* sam3 has a *SINGLE* clock - */
2569         /* other at91 series parts have divisors for these. */
2570         pChip->cfg.cpu_freq = fin;
2571         pChip->cfg.mclk_freq = fin;
2572         pChip->cfg.fclk_freq = fin;
2573         LOG_USER("\t\tResult CPU Freq: %3.03f",
2574                 _tomhz(fin));
2575 }
2576
2577 #if 0
2578 static struct sam3_chip *target2sam3(struct target *pTarget)
2579 {
2580         struct sam3_chip *pChip;
2581
2582         if (pTarget == NULL)
2583                 return NULL;
2584
2585         pChip = all_sam3_chips;
2586         while (pChip) {
2587                 if (pChip->target == pTarget)
2588                         break;  /* return below */
2589                 else
2590                         pChip = pChip->next;
2591         }
2592         return pChip;
2593 }
2594 #endif
2595
2596 static uint32_t *sam3_get_reg_ptr(struct sam3_cfg *pCfg, const struct sam3_reg_list *pList)
2597 {
2598         /* this function exists to help */
2599         /* keep funky offsetof() errors */
2600         /* and casting from causing bugs */
2601
2602         /* By using prototypes - we can detect what would */
2603         /* be casting errors. */
2604
2605         return (uint32_t *)(void *)(((char *)(pCfg)) + pList->struct_offset);
2606 }
2607
2608
2609 #define SAM3_ENTRY(NAME, FUNC)  { .address = SAM3_ ## NAME, .struct_offset = offsetof( \
2610                                                   struct sam3_cfg, \
2611                                                   NAME), # NAME, FUNC }
2612 static const struct sam3_reg_list sam3_all_regs[] = {
2613         SAM3_ENTRY(CKGR_MOR, sam3_explain_ckgr_mor),
2614         SAM3_ENTRY(CKGR_MCFR, sam3_explain_ckgr_mcfr),
2615         SAM3_ENTRY(CKGR_PLLAR, sam3_explain_ckgr_plla),
2616         SAM3_ENTRY(CKGR_UCKR, NULL),
2617         SAM3_ENTRY(PMC_FSMR, NULL),
2618         SAM3_ENTRY(PMC_FSPR, NULL),
2619         SAM3_ENTRY(PMC_IMR, NULL),
2620         SAM3_ENTRY(PMC_MCKR, sam3_explain_mckr),
2621         SAM3_ENTRY(PMC_PCK0, NULL),
2622         SAM3_ENTRY(PMC_PCK1, NULL),
2623         SAM3_ENTRY(PMC_PCK2, NULL),
2624         SAM3_ENTRY(PMC_PCSR, NULL),
2625         SAM3_ENTRY(PMC_SCSR, NULL),
2626         SAM3_ENTRY(PMC_SR, NULL),
2627         SAM3_ENTRY(CHIPID_CIDR, sam3_explain_chipid_cidr),
2628         SAM3_ENTRY(CHIPID_CIDR2, sam3_explain_chipid_cidr),
2629         SAM3_ENTRY(CHIPID_EXID, NULL),
2630         SAM3_ENTRY(CHIPID_EXID2, NULL),
2631         /* TERMINATE THE LIST */
2632         { .name = NULL }
2633 };
2634 #undef SAM3_ENTRY
2635
2636 static struct sam3_bank_private *get_sam3_bank_private(struct flash_bank *bank)
2637 {
2638         return (struct sam3_bank_private *)(bank->driver_priv);
2639 }
2640
2641 /**
2642  * Given a pointer to where it goes in the structure,
2643  * determine the register name, address from the all registers table.
2644  */
2645 static const struct sam3_reg_list *sam3_GetReg(struct sam3_chip *pChip, uint32_t *goes_here)
2646 {
2647         const struct sam3_reg_list *pReg;
2648
2649         pReg = &(sam3_all_regs[0]);
2650         while (pReg->name) {
2651                 uint32_t *pPossible;
2652
2653                 /* calculate where this one go.. */
2654                 /* it is "possibly" this register. */
2655
2656                 pPossible = ((uint32_t *)(void *)(((char *)(&(pChip->cfg))) + pReg->struct_offset));
2657
2658                 /* well? Is it this register */
2659                 if (pPossible == goes_here) {
2660                         /* Jump for joy! */
2661                         return pReg;
2662                 }
2663
2664                 /* next... */
2665                 pReg++;
2666         }
2667         /* This is *TOTAL*PANIC* - we are totally screwed. */
2668         LOG_ERROR("INVALID SAM3 REGISTER");
2669         return NULL;
2670 }
2671
2672 static int sam3_ReadThisReg(struct sam3_chip *pChip, uint32_t *goes_here)
2673 {
2674         const struct sam3_reg_list *pReg;
2675         int r;
2676
2677         pReg = sam3_GetReg(pChip, goes_here);
2678         if (!pReg)
2679                 return ERROR_FAIL;
2680
2681         r = target_read_u32(pChip->target, pReg->address, goes_here);
2682         if (r != ERROR_OK) {
2683                 LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Err: %d",
2684                         pReg->name, (unsigned)(pReg->address), r);
2685         }
2686         return r;
2687 }
2688
2689 static int sam3_ReadAllRegs(struct sam3_chip *pChip)
2690 {
2691         int r;
2692         const struct sam3_reg_list *pReg;
2693
2694         pReg = &(sam3_all_regs[0]);
2695         while (pReg->name) {
2696                 r = sam3_ReadThisReg(pChip,
2697                                 sam3_get_reg_ptr(&(pChip->cfg), pReg));
2698                 if (r != ERROR_OK) {
2699                         LOG_ERROR("Cannot read SAM3 register: %s @ 0x%08x, Error: %d",
2700                                 pReg->name, ((unsigned)(pReg->address)), r);
2701                         return r;
2702                 }
2703                 pReg++;
2704         }
2705
2706         /* Chip identification register
2707         *
2708         * Unfortunately, the chip identification register is not at
2709         * a constant address across all of the SAM3 series'. As a
2710         * consequence, a simple heuristic is used to find where it's
2711         * at...
2712         *
2713         * If the contents at the first address is zero, then we know
2714         * that the second address is where the chip id register is.
2715         * We can deduce this because for those SAM's that have the
2716         * chip id @ 0x400e0940, the first address, 0x400e0740, is
2717         * located in the memory map of the Power Management Controller
2718         * (PMC). Furthermore, the address is not used by the PMC.
2719         * So when read, the memory controller returns zero.*/
2720         if (pChip->cfg.CHIPID_CIDR == 0)        {
2721                 /*Put the correct CIDR and EXID values in the pChip structure */
2722                 pChip->cfg.CHIPID_CIDR = pChip->cfg.CHIPID_CIDR2;
2723                 pChip->cfg.CHIPID_EXID = pChip->cfg.CHIPID_EXID2;
2724         }
2725         return ERROR_OK;
2726 }
2727
2728 static int sam3_GetInfo(struct sam3_chip *pChip)
2729 {
2730         const struct sam3_reg_list *pReg;
2731         uint32_t regval;
2732
2733         pReg = &(sam3_all_regs[0]);
2734         while (pReg->name) {
2735                 /* display all regs */
2736                 LOG_DEBUG("Start: %s", pReg->name);
2737                 regval = *sam3_get_reg_ptr(&(pChip->cfg), pReg);
2738                 LOG_USER("%*s: [0x%08x] -> 0x%08x",
2739                         REG_NAME_WIDTH,
2740                         pReg->name,
2741                         pReg->address,
2742                         regval);
2743                 if (pReg->explain_func)
2744                         (*(pReg->explain_func))(pChip);
2745                 LOG_DEBUG("End: %s", pReg->name);
2746                 pReg++;
2747         }
2748         LOG_USER("   rc-osc: %3.03f MHz", _tomhz(pChip->cfg.rc_freq));
2749         LOG_USER("  mainosc: %3.03f MHz", _tomhz(pChip->cfg.mainosc_freq));
2750         LOG_USER("     plla: %3.03f MHz", _tomhz(pChip->cfg.plla_freq));
2751         LOG_USER(" cpu-freq: %3.03f MHz", _tomhz(pChip->cfg.cpu_freq));
2752         LOG_USER("mclk-freq: %3.03f MHz", _tomhz(pChip->cfg.mclk_freq));
2753
2754         LOG_USER(" UniqueId: 0x%08x 0x%08x 0x%08x 0x%08x",
2755                 pChip->cfg.unique_id[0],
2756                 pChip->cfg.unique_id[1],
2757                 pChip->cfg.unique_id[2],
2758                 pChip->cfg.unique_id[3]);
2759
2760         return ERROR_OK;
2761 }
2762
2763 static int sam3_erase_check(struct flash_bank *bank)
2764 {
2765         int x;
2766
2767         LOG_DEBUG("Here");
2768         if (bank->target->state != TARGET_HALTED) {
2769                 LOG_ERROR("Target not halted");
2770                 return ERROR_TARGET_NOT_HALTED;
2771         }
2772         if (0 == bank->num_sectors) {
2773                 LOG_ERROR("Target: not supported/not probed");
2774                 return ERROR_FAIL;
2775         }
2776
2777         LOG_INFO("sam3 - supports auto-erase, erase_check ignored");
2778         for (x = 0; x < bank->num_sectors; x++)
2779                 bank->sectors[x].is_erased = 1;
2780
2781         LOG_DEBUG("Done");
2782         return ERROR_OK;
2783 }
2784
2785 static int sam3_protect_check(struct flash_bank *bank)
2786 {
2787         int r;
2788         uint32_t v = 0;
2789         unsigned x;
2790         struct sam3_bank_private *pPrivate;
2791
2792         LOG_DEBUG("Begin");
2793         if (bank->target->state != TARGET_HALTED) {
2794                 LOG_ERROR("Target not halted");
2795                 return ERROR_TARGET_NOT_HALTED;
2796         }
2797
2798         pPrivate = get_sam3_bank_private(bank);
2799         if (!pPrivate) {
2800                 LOG_ERROR("no private for this bank?");
2801                 return ERROR_FAIL;
2802         }
2803         if (!(pPrivate->probed))
2804                 return ERROR_FLASH_BANK_NOT_PROBED;
2805
2806         r = FLASHD_GetLockBits(pPrivate, &v);
2807         if (r != ERROR_OK) {
2808                 LOG_DEBUG("Failed: %d", r);
2809                 return r;
2810         }
2811
2812         for (x = 0; x < pPrivate->nsectors; x++)
2813                 bank->sectors[x].is_protected = (!!(v & (1 << x)));
2814         LOG_DEBUG("Done");
2815         return ERROR_OK;
2816 }
2817
2818 FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
2819 {
2820         struct sam3_chip *pChip;
2821
2822         pChip = all_sam3_chips;
2823
2824         /* is this an existing chip? */
2825         while (pChip) {
2826                 if (pChip->target == bank->target)
2827                         break;
2828                 pChip = pChip->next;
2829         }
2830
2831         if (!pChip) {
2832                 /* this is a *NEW* chip */
2833                 pChip = calloc(1, sizeof(struct sam3_chip));
2834                 if (!pChip) {
2835                         LOG_ERROR("NO RAM!");
2836                         return ERROR_FAIL;
2837                 }
2838                 pChip->target = bank->target;
2839                 /* insert at head */
2840                 pChip->next = all_sam3_chips;
2841                 all_sam3_chips = pChip;
2842                 pChip->target = bank->target;
2843                 /* assumption is this runs at 32khz */
2844                 pChip->cfg.slow_freq = 32768;
2845                 pChip->probed = 0;
2846         }
2847
2848         switch (bank->base) {
2849                 default:
2850                         LOG_ERROR("Address 0x%08x invalid bank address (try 0x%08x or 0x%08x "
2851                         "[at91sam3u series] or 0x%08x [at91sam3s series] or "
2852                         "0x%08x [at91sam3n series] or 0x%08x or 0x%08x or 0x%08x[at91sam3ax series] )",
2853                         ((unsigned int)(bank->base)),
2854                         ((unsigned int)(FLASH_BANK0_BASE_U)),
2855                         ((unsigned int)(FLASH_BANK1_BASE_U)),
2856                         ((unsigned int)(FLASH_BANK_BASE_S)),
2857                         ((unsigned int)(FLASH_BANK_BASE_N)),
2858                         ((unsigned int)(FLASH_BANK0_BASE_AX)),
2859                     ((unsigned int)(FLASH_BANK1_BASE_256K_AX)),
2860                     ((unsigned int)(FLASH_BANK1_BASE_512K_AX)));
2861                         return ERROR_FAIL;
2862                         break;
2863
2864                 /* at91sam3s and at91sam3n series only has bank 0*/
2865                 /* at91sam3u and at91sam3ax series has the same address for bank 0*/
2866                 case FLASH_BANK_BASE_S:
2867                 case FLASH_BANK0_BASE_U:
2868                         bank->driver_priv = &(pChip->details.bank[0]);
2869                         bank->bank_number = 0;
2870                         pChip->details.bank[0].pChip = pChip;
2871                         pChip->details.bank[0].pBank = bank;
2872                         break;
2873
2874                 /* Bank 1 of at91sam3u or at91sam3ax series */
2875                 case FLASH_BANK1_BASE_U:
2876                 case FLASH_BANK1_BASE_256K_AX:
2877                 case FLASH_BANK1_BASE_512K_AX:
2878                         bank->driver_priv = &(pChip->details.bank[1]);
2879                         bank->bank_number = 1;
2880                         pChip->details.bank[1].pChip = pChip;
2881                         pChip->details.bank[1].pBank = bank;
2882                         break;
2883         }
2884
2885         /* we initialize after probing. */
2886         return ERROR_OK;
2887 }
2888
2889 static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
2890 {
2891         const struct sam3_chip_details *pDetails;
2892         struct sam3_chip *pChip;
2893         struct flash_bank *saved_banks[SAM3_MAX_FLASH_BANKS];
2894         unsigned x;
2895
2896         LOG_DEBUG("Begin");
2897         pDetails = all_sam3_details;
2898         while (pDetails->name) {
2899                 /* Compare cidr without version bits */
2900                 if (pDetails->chipid_cidr == (pPrivate->pChip->cfg.CHIPID_CIDR & 0xFFFFFFE0))
2901                         break;
2902                 else
2903                         pDetails++;
2904         }
2905         if (pDetails->name == NULL) {
2906                 LOG_ERROR("SAM3 ChipID 0x%08x not found in table (perhaps you can ID this chip?)",
2907                         (unsigned int)(pPrivate->pChip->cfg.CHIPID_CIDR));
2908                 /* Help the victim, print details about the chip */
2909                 LOG_INFO("SAM3 CHIPID_CIDR: 0x%08x decodes as follows",
2910                         pPrivate->pChip->cfg.CHIPID_CIDR);
2911                 sam3_explain_chipid_cidr(pPrivate->pChip);
2912                 return ERROR_FAIL;
2913         }
2914
2915         /* DANGER: THERE ARE DRAGONS HERE */
2916
2917         /* get our pChip - it is going */
2918         /* to be over-written shortly */
2919         pChip = pPrivate->pChip;
2920
2921         /* Note that, in reality: */
2922         /*  */
2923         /*     pPrivate = &(pChip->details.bank[0]) */
2924         /* or  pPrivate = &(pChip->details.bank[1]) */
2925         /*  */
2926
2927         /* save the "bank" pointers */
2928         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++)
2929                 saved_banks[x] = pChip->details.bank[x].pBank;
2930
2931         /* Overwrite the "details" structure. */
2932         memcpy(&(pPrivate->pChip->details),
2933                 pDetails,
2934                 sizeof(pPrivate->pChip->details));
2935
2936         /* now fix the ghosted pointers */
2937         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2938                 pChip->details.bank[x].pChip = pChip;
2939                 pChip->details.bank[x].pBank = saved_banks[x];
2940         }
2941
2942         /* update the *BANK*SIZE* */
2943
2944         LOG_DEBUG("End");
2945         return ERROR_OK;
2946 }
2947
2948 static int _sam3_probe(struct flash_bank *bank, int noise)
2949 {
2950         unsigned x;
2951         int r;
2952         struct sam3_bank_private *pPrivate;
2953
2954
2955         LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
2956         if (bank->target->state != TARGET_HALTED) {
2957                 LOG_ERROR("Target not halted");
2958                 return ERROR_TARGET_NOT_HALTED;
2959         }
2960
2961         pPrivate = get_sam3_bank_private(bank);
2962         if (!pPrivate) {
2963                 LOG_ERROR("Invalid/unknown bank number");
2964                 return ERROR_FAIL;
2965         }
2966
2967         r = sam3_ReadAllRegs(pPrivate->pChip);
2968         if (r != ERROR_OK)
2969                 return r;
2970
2971         LOG_DEBUG("Here");
2972         if (pPrivate->pChip->probed)
2973                 r = sam3_GetInfo(pPrivate->pChip);
2974         else
2975                 r = sam3_GetDetails(pPrivate);
2976         if (r != ERROR_OK)
2977                 return r;
2978
2979         /* update the flash bank size */
2980         for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
2981                 if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
2982                         bank->size = pPrivate->pChip->details.bank[x].size_bytes;
2983                         break;
2984                 }
2985         }
2986
2987         if (bank->sectors == NULL) {
2988                 bank->sectors = calloc(pPrivate->nsectors, (sizeof((bank->sectors)[0])));
2989                 if (bank->sectors == NULL) {
2990                         LOG_ERROR("No memory!");
2991                         return ERROR_FAIL;
2992                 }
2993                 bank->num_sectors = pPrivate->nsectors;
2994
2995                 for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
2996                         bank->sectors[x].size = pPrivate->sector_size;
2997                         bank->sectors[x].offset = x * (pPrivate->sector_size);
2998                         /* mark as unknown */
2999                         bank->sectors[x].is_erased = -1;
3000                         bank->sectors[x].is_protected = -1;
3001                 }
3002         }
3003
3004         pPrivate->probed = 1;
3005
3006         r = sam3_protect_check(bank);
3007         if (r != ERROR_OK)
3008                 return r;
3009
3010         LOG_DEBUG("Bank = %d, nbanks = %d",
3011                 pPrivate->bank_number, pPrivate->pChip->details.n_banks);
3012         if ((pPrivate->bank_number + 1) == pPrivate->pChip->details.n_banks) {
3013                 /* read unique id, */
3014                 /* it appears to be associated with the *last* flash bank. */
3015                 FLASHD_ReadUniqueID(pPrivate);
3016         }
3017
3018         return r;
3019 }
3020
3021 static int sam3_probe(struct flash_bank *bank)
3022 {
3023         return _sam3_probe(bank, 1);
3024 }
3025
3026 static int sam3_auto_probe(struct flash_bank *bank)
3027 {
3028         return _sam3_probe(bank, 0);
3029 }
3030
3031 static int sam3_erase(struct flash_bank *bank, int first, int last)
3032 {
3033         struct sam3_bank_private *pPrivate;
3034         int r;
3035
3036         LOG_DEBUG("Here");
3037         if (bank->target->state != TARGET_HALTED) {
3038                 LOG_ERROR("Target not halted");
3039                 return ERROR_TARGET_NOT_HALTED;
3040         }
3041
3042         r = sam3_auto_probe(bank);
3043         if (r != ERROR_OK) {
3044                 LOG_DEBUG("Here,r=%d", r);
3045                 return r;
3046         }
3047
3048         pPrivate = get_sam3_bank_private(bank);
3049         if (!(pPrivate->probed))
3050                 return ERROR_FLASH_BANK_NOT_PROBED;
3051
3052         if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
3053                 /* whole chip */
3054                 LOG_DEBUG("Here");
3055                 return FLASHD_EraseEntireBank(pPrivate);
3056         }
3057         LOG_INFO("sam3 auto-erases while programming (request ignored)");
3058         return ERROR_OK;
3059 }
3060
3061 static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
3062 {
3063         struct sam3_bank_private *pPrivate;
3064         int r;
3065
3066         LOG_DEBUG("Here");
3067         if (bank->target->state != TARGET_HALTED) {
3068                 LOG_ERROR("Target not halted");
3069                 return ERROR_TARGET_NOT_HALTED;
3070         }
3071
3072         pPrivate = get_sam3_bank_private(bank);
3073         if (!(pPrivate->probed))
3074                 return ERROR_FLASH_BANK_NOT_PROBED;
3075
3076         if (set)
3077                 r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
3078         else
3079                 r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
3080         LOG_DEBUG("End: r=%d", r);
3081
3082         return r;
3083
3084 }
3085
3086 static int sam3_info(struct flash_bank *bank, char *buf, int buf_size)
3087 {
3088         if (bank->target->state != TARGET_HALTED) {
3089                 LOG_ERROR("Target not halted");
3090                 return ERROR_TARGET_NOT_HALTED;
3091         }
3092         buf[0] = 0;
3093         return ERROR_OK;
3094 }
3095
3096 static int sam3_page_read(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3097 {
3098         uint32_t adr;
3099         int r;
3100
3101         adr = pagenum * pPrivate->page_size;
3102         adr += pPrivate->base_address;
3103
3104         r = target_read_memory(pPrivate->pChip->target,
3105                         adr,
3106                         4,                                      /* THIS*MUST*BE* in 32bit values */
3107                         pPrivate->page_size / 4,
3108                         buf);
3109         if (r != ERROR_OK)
3110                 LOG_ERROR("SAM3: Flash program failed to read page phys address: 0x%08x",
3111                         (unsigned int)(adr));
3112         return r;
3113 }
3114
3115 /* The code below is basically this: */
3116 /* compiled with */
3117 /* arm-none-eabi-gcc -mthumb -mcpu = cortex-m3 -O9 -S ./foobar.c -o foobar.s */
3118 /*  */
3119 /* Only the *CPU* can write to the flash buffer. */
3120 /* the DAP cannot... so - we download this 28byte thing */
3121 /* Run the algorithm - (below) */
3122 /* to program the device */
3123 /*  */
3124 /* ======================================== */
3125 /* #include <stdint.h> */
3126 /*  */
3127 /* struct foo { */
3128 /*   uint32_t *dst; */
3129 /*   const uint32_t *src; */
3130 /*   int   n; */
3131 /*   volatile uint32_t *base; */
3132 /*   uint32_t   cmd; */
3133 /* }; */
3134 /*  */
3135 /*  */
3136 /* uint32_t sam3_function(struct foo *p) */
3137 /* { */
3138 /*   volatile uint32_t *v; */
3139 /*   uint32_t *d; */
3140 /*   const uint32_t *s; */
3141 /*   int   n; */
3142 /*   uint32_t r; */
3143 /*  */
3144 /*   d = p->dst; */
3145 /*   s = p->src; */
3146 /*   n = p->n; */
3147 /*  */
3148 /*   do { */
3149 /*     *d++ = *s++; */
3150 /*   } while (--n) */
3151 /*     ; */
3152 /*  */
3153 /*   v = p->base; */
3154 /*  */
3155 /*   v[ 1 ] = p->cmd; */
3156 /*   do { */
3157 /*     r = v[8/4]; */
3158 /*   } while (!(r&1)) */
3159 /*     ; */
3160 /*   return r; */
3161 /* } */
3162 /* ======================================== */
3163
3164 static const uint8_t
3165         sam3_page_write_opcodes[] = {
3166         /*  24 0000 0446                mov     r4, r0 */
3167         0x04, 0x46,
3168         /*  25 0002 6168                ldr     r1, [r4, #4] */
3169         0x61, 0x68,
3170         /*  26 0004 0068                ldr     r0, [r0, #0] */
3171         0x00, 0x68,
3172         /*  27 0006 A268                ldr     r2, [r4, #8] */
3173         0xa2, 0x68,
3174         /*  28                          @ lr needed for prologue */
3175         /*  29                  .L2: */
3176         /*  30 0008 51F8043B            ldr     r3, [r1], #4 */
3177         0x51, 0xf8, 0x04, 0x3b,
3178         /*  31 000c 12F1FF32            adds    r2, r2, #-1 */
3179         0x12, 0xf1, 0xff, 0x32,
3180         /*  32 0010 40F8043B            str     r3, [r0], #4 */
3181         0x40, 0xf8, 0x04, 0x3b,
3182         /*  33 0014 F8D1                bne     .L2 */
3183         0xf8, 0xd1,
3184         /*  34 0016 E268                ldr     r2, [r4, #12] */
3185         0xe2, 0x68,
3186         /*  35 0018 2369                ldr     r3, [r4, #16] */
3187         0x23, 0x69,
3188         /*  36 001a 5360                str     r3, [r2, #4] */
3189         0x53, 0x60,
3190         /*  37 001c 0832                adds    r2, r2, #8 */
3191         0x08, 0x32,
3192         /*  38                  .L4: */
3193         /*  39 001e 1068                ldr     r0, [r2, #0] */
3194         0x10, 0x68,
3195         /*  40 0020 10F0010F            tst     r0, #1 */
3196         0x10, 0xf0, 0x01, 0x0f,
3197         /*  41 0024 FBD0                beq     .L4 */
3198         0xfb, 0xd0,
3199         0x00, 0xBE                              /* bkpt #0 */
3200 };
3201
3202 static int sam3_page_write(struct sam3_bank_private *pPrivate, unsigned pagenum, uint8_t *buf)
3203 {
3204         uint32_t adr;
3205         uint32_t status;
3206         uint32_t fmr;   /* EEFC Flash Mode Register */
3207         int r;
3208
3209         adr = pagenum * pPrivate->page_size;
3210         adr += pPrivate->base_address;
3211
3212         /* Get flash mode register value */
3213         r = target_read_u32(pPrivate->pChip->target, pPrivate->controller_address, &fmr);
3214         if (r != ERROR_OK)
3215                 LOG_DEBUG("Error Read failed: read flash mode register");
3216
3217         /* Clear flash wait state field */
3218         fmr &= 0xfffff0ff;
3219
3220         /* set FWS (flash wait states) field in the FMR (flash mode register) */
3221         fmr |= (pPrivate->flash_wait_states << 8);
3222
3223         LOG_DEBUG("Flash Mode: 0x%08x", ((unsigned int)(fmr)));
3224         r = target_write_u32(pPrivate->pBank->target, pPrivate->controller_address, fmr);
3225         if (r != ERROR_OK)
3226                 LOG_DEBUG("Error Write failed: set flash mode register");
3227
3228         LOG_DEBUG("Wr Page %u @ phys address: 0x%08x", pagenum, (unsigned int)(adr));
3229         r = target_write_memory(pPrivate->pChip->target,
3230                         adr,
3231                         4,                                      /* THIS*MUST*BE* in 32bit values */
3232                         pPrivate->page_size / 4,
3233                         buf);
3234         if (r != ERROR_OK) {
3235                 LOG_ERROR("SAM3: Failed to write (buffer) page at phys address 0x%08x",
3236                         (unsigned int)(adr));
3237                 return r;
3238         }
3239
3240         r = EFC_PerformCommand(pPrivate,
3241                         /* send Erase & Write Page */
3242                         AT91C_EFC_FCMD_EWP,
3243                         pagenum,
3244                         &status);
3245
3246         if (r != ERROR_OK)
3247                 LOG_ERROR("SAM3: Error performing Erase & Write page @ phys address 0x%08x",
3248                         (unsigned int)(adr));
3249         if (status & (1 << 2)) {
3250                 LOG_ERROR("SAM3: Page @ Phys address 0x%08x is locked", (unsigned int)(adr));
3251                 return ERROR_FAIL;
3252         }
3253         if (status & (1 << 1)) {
3254                 LOG_ERROR("SAM3: Flash Command error @phys address 0x%08x", (unsigned int)(adr));
3255                 return ERROR_FAIL;
3256         }
3257         return ERROR_OK;
3258 }
3259
3260 static int sam3_write(struct flash_bank *bank,
3261         uint8_t *buffer,
3262         uint32_t offset,
3263         uint32_t count)
3264 {
3265         int n;
3266         unsigned page_cur;
3267         unsigned page_end;
3268         int r;
3269         unsigned page_offset;
3270         struct sam3_bank_private *pPrivate;
3271         uint8_t *pagebuffer;
3272
3273         /* incase we bail further below, set this to null */
3274         pagebuffer = NULL;
3275
3276         /* ignore dumb requests */
3277         if (count == 0) {
3278                 r = ERROR_OK;
3279                 goto done;
3280         }
3281
3282         if (bank->target->state != TARGET_HALTED) {
3283                 LOG_ERROR("Target not halted");
3284                 r = ERROR_TARGET_NOT_HALTED;
3285                 goto done;
3286         }
3287
3288         pPrivate = get_sam3_bank_private(bank);
3289         if (!(pPrivate->probed)) {
3290                 r = ERROR_FLASH_BANK_NOT_PROBED;
3291                 goto done;
3292         }
3293
3294         if ((offset + count) > pPrivate->size_bytes) {
3295                 LOG_ERROR("Flash write error - past end of bank");
3296                 LOG_ERROR(" offset: 0x%08x, count 0x%08x, BankEnd: 0x%08x",
3297                         (unsigned int)(offset),
3298                         (unsigned int)(count),
3299                         (unsigned int)(pPrivate->size_bytes));
3300                 r = ERROR_FAIL;
3301                 goto done;
3302         }
3303
3304         pagebuffer = malloc(pPrivate->page_size);
3305         if (!pagebuffer) {
3306                 LOG_ERROR("No memory for %d Byte page buffer", (int)(pPrivate->page_size));
3307                 r = ERROR_FAIL;
3308                 goto done;
3309         }
3310
3311         /* what page do we start & end in? */
3312         page_cur = offset / pPrivate->page_size;
3313         page_end = (offset + count - 1) / pPrivate->page_size;
3314
3315         LOG_DEBUG("Offset: 0x%08x, Count: 0x%08x", (unsigned int)(offset), (unsigned int)(count));
3316         LOG_DEBUG("Page start: %d, Page End: %d", (int)(page_cur), (int)(page_end));
3317
3318         /* Special case: all one page */
3319         /*  */
3320         /* Otherwise: */
3321         /*    (1) non-aligned start */
3322         /*    (2) body pages */
3323         /*    (3) non-aligned end. */
3324
3325         /* Handle special case - all one page. */
3326         if (page_cur == page_end) {
3327                 LOG_DEBUG("Special case, all in one page");
3328                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3329                 if (r != ERROR_OK)
3330                         goto done;
3331
3332                 page_offset = (offset & (pPrivate->page_size-1));
3333                 memcpy(pagebuffer + page_offset,
3334                         buffer,
3335                         count);
3336
3337                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3338                 if (r != ERROR_OK)
3339                         goto done;
3340                 r = ERROR_OK;
3341                 goto done;
3342         }
3343
3344         /* non-aligned start */
3345         page_offset = offset & (pPrivate->page_size - 1);
3346         if (page_offset) {
3347                 LOG_DEBUG("Not-Aligned start");
3348                 /* read the partial */
3349                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3350                 if (r != ERROR_OK)
3351                         goto done;
3352
3353                 /* over-write with new data */
3354                 n = (pPrivate->page_size - page_offset);
3355                 memcpy(pagebuffer + page_offset,
3356                         buffer,
3357                         n);
3358
3359                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3360                 if (r != ERROR_OK)
3361                         goto done;
3362
3363                 count  -= n;
3364                 offset += n;
3365                 buffer += n;
3366                 page_cur++;
3367         }
3368
3369         /* By checking that offset is correct here, we also
3370         fix a clang warning */
3371         assert(offset % pPrivate->page_size == 0);
3372
3373         /* intermediate large pages */
3374         /* also - the final *terminal* */
3375         /* if that terminal page is a full page */
3376         LOG_DEBUG("Full Page Loop: cur=%d, end=%d, count = 0x%08x",
3377                 (int)page_cur, (int)page_end, (unsigned int)(count));
3378
3379         while ((page_cur < page_end) &&
3380                         (count >= pPrivate->page_size)) {
3381                 r = sam3_page_write(pPrivate, page_cur, buffer);
3382                 if (r != ERROR_OK)
3383                         goto done;
3384                 count -= pPrivate->page_size;
3385                 buffer += pPrivate->page_size;
3386                 page_cur += 1;
3387         }
3388
3389         /* terminal partial page? */
3390         if (count) {
3391                 LOG_DEBUG("Terminal partial page, count = 0x%08x", (unsigned int)(count));
3392                 /* we have a partial page */
3393                 r = sam3_page_read(pPrivate, page_cur, pagebuffer);
3394                 if (r != ERROR_OK)
3395                         goto done;
3396                                         /* data goes at start */
3397                 memcpy(pagebuffer, buffer, count);
3398                 r = sam3_page_write(pPrivate, page_cur, pagebuffer);
3399                 if (r != ERROR_OK)
3400                         goto done;
3401         }
3402         LOG_DEBUG("Done!");
3403         r = ERROR_OK;
3404 done:
3405         if (pagebuffer)
3406                 free(pagebuffer);
3407         return r;
3408 }
3409
3410 COMMAND_HANDLER(sam3_handle_info_command)
3411 {
3412         struct sam3_chip *pChip;
3413         pChip = get_current_sam3(CMD_CTX);
3414         if (!pChip)
3415                 return ERROR_OK;
3416
3417         unsigned x;
3418         int r;
3419
3420         /* bank0 must exist before we can do anything */
3421         if (pChip->details.bank[0].pBank == NULL) {
3422                 x = 0;
3423 need_define:
3424                 command_print(CMD_CTX,
3425                         "Please define bank %d via command: flash bank %s ... ",
3426                         x,
3427                         at91sam3_flash.name);
3428                 return ERROR_FAIL;
3429         }
3430
3431         /* if bank 0 is not probed, then probe it */
3432         if (!(pChip->details.bank[0].probed)) {
3433                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3434                 if (r != ERROR_OK)
3435                         return ERROR_FAIL;
3436         }
3437         /* above guarantees the "chip details" structure is valid */
3438         /* and thus, bank private areas are valid */
3439         /* and we have a SAM3 chip, what a concept! */
3440
3441         /* auto-probe other banks, 0 done above */
3442         for (x = 1; x < SAM3_MAX_FLASH_BANKS; x++) {
3443                 /* skip banks not present */
3444                 if (!(pChip->details.bank[x].present))
3445                         continue;
3446
3447                 if (pChip->details.bank[x].pBank == NULL)
3448                         goto need_define;
3449
3450                 if (pChip->details.bank[x].probed)
3451                         continue;
3452
3453                 r = sam3_auto_probe(pChip->details.bank[x].pBank);
3454                 if (r != ERROR_OK)
3455                         return r;
3456         }
3457
3458         r = sam3_GetInfo(pChip);
3459         if (r != ERROR_OK) {
3460                 LOG_DEBUG("Sam3Info, Failed %d", r);
3461                 return r;
3462         }
3463
3464         return ERROR_OK;
3465 }
3466
3467 COMMAND_HANDLER(sam3_handle_gpnvm_command)
3468 {
3469         unsigned x, v;
3470         int r, who;
3471         struct sam3_chip *pChip;
3472
3473         pChip = get_current_sam3(CMD_CTX);
3474         if (!pChip)
3475                 return ERROR_OK;
3476
3477         if (pChip->target->state != TARGET_HALTED) {
3478                 LOG_ERROR("sam3 - target not halted");
3479                 return ERROR_TARGET_NOT_HALTED;
3480         }
3481
3482         if (pChip->details.bank[0].pBank == NULL) {
3483                 command_print(CMD_CTX, "Bank0 must be defined first via: flash bank %s ...",
3484                         at91sam3_flash.name);
3485                 return ERROR_FAIL;
3486         }
3487         if (!pChip->details.bank[0].probed) {
3488                 r = sam3_auto_probe(pChip->details.bank[0].pBank);
3489                 if (r != ERROR_OK)
3490                         return r;
3491         }
3492
3493         switch (CMD_ARGC) {
3494                 default:
3495                         return ERROR_COMMAND_SYNTAX_ERROR;
3496                         break;
3497                 case 0:
3498                         goto showall;
3499                         break;
3500                 case 1:
3501                         who = -1;
3502                         break;
3503                 case 2:
3504                         if ((0 == strcmp(CMD_ARGV[0], "show")) && (0 == strcmp(CMD_ARGV[1], "all")))
3505                                 who = -1;
3506                         else {
3507                                 uint32_t v32;
3508                                 COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
3509                                 who = v32;
3510                         }
3511                         break;
3512         }
3513
3514         if (0 == strcmp("show", CMD_ARGV[0])) {
3515                 if (who == -1) {
3516 showall:
3517                         r = ERROR_OK;
3518                         for (x = 0; x < pChip->details.n_gpnvms; x++) {
3519                                 r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), x, &v);
3520                                 if (r != ERROR_OK)
3521                                         break;
3522                                 command_print(CMD_CTX, "sam3-gpnvm%u: %u", x, v);
3523                         }
3524                         return r;
3525                 }
3526                 if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
3527                         r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
3528                         command_print(CMD_CTX, "sam3-gpnvm%u: %u", who, v);
3529                         return r;
3530                 } else {
3531                         command_print(CMD_CTX, "sam3-gpnvm invalid GPNVM: %u", who);
3532                         return ERROR_COMMAND_SYNTAX_ERROR;
3533                 }
3534         }
3535
3536         if (who == -1) {
3537                 command_print(CMD_CTX, "Missing GPNVM number");
3538                 return ERROR_COMMAND_SYNTAX_ERROR;
3539         }
3540
3541         if (0 == strcmp("set", CMD_ARGV[0]))
3542                 r = FLASHD_SetGPNVM(&(pChip->details.bank[0]), who);
3543         else if ((0 == strcmp("clr", CMD_ARGV[0])) ||
3544                  (0 == strcmp("clear", CMD_ARGV[0])))                   /* quietly accept both */
3545                 r = FLASHD_ClrGPNVM(&(pChip->details.bank[0]), who);
3546         else {
3547                 command_print(CMD_CTX, "Unknown command: %s", CMD_ARGV[0]);
3548                 r = ERROR_COMMAND_SYNTAX_ERROR;
3549         }
3550         return r;
3551 }
3552
3553 COMMAND_HANDLER(sam3_handle_slowclk_command)
3554 {
3555         struct sam3_chip *pChip;
3556
3557         pChip = get_current_sam3(CMD_CTX);
3558         if (!pChip)
3559                 return ERROR_OK;
3560
3561         switch (CMD_ARGC) {
3562                 case 0:
3563                         /* show */
3564                         break;
3565                 case 1:
3566                 {
3567                         /* set */
3568                         uint32_t v;
3569                         COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], v);
3570                         if (v > 200000) {
3571                                 /* absurd slow clock of 200Khz? */
3572                                 command_print(CMD_CTX, "Absurd/illegal slow clock freq: %d\n", (int)(v));
3573                                 return ERROR_COMMAND_SYNTAX_ERROR;
3574                         }
3575                         pChip->cfg.slow_freq = v;
3576                         break;
3577                 }
3578                 default:
3579                         /* error */
3580                         command_print(CMD_CTX, "Too many parameters");
3581                         return ERROR_COMMAND_SYNTAX_ERROR;
3582                         break;
3583         }
3584         command_print(CMD_CTX, "Slowclk freq: %d.%03dkhz",
3585                 (int)(pChip->cfg.slow_freq / 1000),
3586                 (int)(pChip->cfg.slow_freq % 1000));
3587         return ERROR_OK;
3588 }
3589
3590 static const struct command_registration at91sam3_exec_command_handlers[] = {
3591         {
3592                 .name = "gpnvm",
3593                 .handler = sam3_handle_gpnvm_command,
3594                 .mode = COMMAND_EXEC,
3595                 .usage = "[('clr'|'set'|'show') bitnum]",
3596                 .help = "Without arguments, shows all bits in the gpnvm "
3597                         "register.  Otherwise, clears, sets, or shows one "
3598                         "General Purpose Non-Volatile Memory (gpnvm) bit.",
3599         },
3600         {
3601                 .name = "info",
3602                 .handler = sam3_handle_info_command,
3603                 .mode = COMMAND_EXEC,
3604                 .help = "Print information about the current at91sam3 chip"
3605                         "and its flash configuration.",
3606         },
3607         {
3608                 .name = "slowclk",
3609                 .handler = sam3_handle_slowclk_command,
3610                 .mode = COMMAND_EXEC,
3611                 .usage = "[clock_hz]",
3612                 .help = "Display or set the slowclock frequency "
3613                         "(default 32768 Hz).",
3614         },
3615         COMMAND_REGISTRATION_DONE
3616 };
3617 static const struct command_registration at91sam3_command_handlers[] = {
3618         {
3619                 .name = "at91sam3",
3620                 .mode = COMMAND_ANY,
3621                 .help = "at91sam3 flash command group",
3622                 .usage = "",
3623                 .chain = at91sam3_exec_command_handlers,
3624         },
3625         COMMAND_REGISTRATION_DONE
3626 };
3627
3628 struct flash_driver at91sam3_flash = {
3629         .name = "at91sam3",
3630         .commands = at91sam3_command_handlers,
3631         .flash_bank_command = sam3_flash_bank_command,
3632         .erase = sam3_erase,
3633         .protect = sam3_protect,
3634         .write = sam3_write,
3635         .read = default_flash_read,
3636         .probe = sam3_probe,
3637         .auto_probe = sam3_auto_probe,
3638         .erase_check = sam3_erase_check,
3639         .protect_check = sam3_protect_check,
3640         .info = sam3_info,
3641 };