1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
27 #define SAMD_NUM_SECTORS 16
29 #define SAMD_FLASH 0x00000000 /* physical Flash memory */
30 #define SAMD_DSU 0x41002000 /* Device Service Unit */
31 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
33 #define SAMD_DSU_DID 0x18 /* Device ID register */
35 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
36 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
37 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
38 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
39 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
40 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
41 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
43 #define SAMD_CMDEX_KEY 0xA5UL
44 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
46 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
47 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
48 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
49 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
50 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
51 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
52 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
53 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
54 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
55 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
56 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
57 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
59 /* Known identifiers */
60 #define SAMD_PROCESSOR_M0 0x01
61 #define SAMD_FAMILY_D 0x00
62 #define SAMD_SERIES_20 0x00
63 #define SAMD_SERIES_21 0x01
72 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
73 static const struct samd_part samd20_parts[] = {
74 { 0x0, "SAMD20J18A", 256, 32 },
75 { 0x1, "SAMD20J17A", 128, 16 },
76 { 0x2, "SAMD20J16A", 64, 8 },
77 { 0x3, "SAMD20J15A", 32, 4 },
78 { 0x4, "SAMD20J14A", 16, 2 },
79 { 0x5, "SAMD20G18A", 256, 32 },
80 { 0x6, "SAMD20G17A", 128, 16 },
81 { 0x7, "SAMD20G16A", 64, 8 },
82 { 0x8, "SAMD20G15A", 32, 4 },
83 { 0x9, "SAMD20G14A", 16, 2 },
84 { 0xB, "SAMD20E17A", 128, 16 },
85 { 0xC, "SAMD20E16A", 64, 8 },
86 { 0xD, "SAMD20E15A", 32, 4 },
87 { 0xE, "SAMD20E14A", 16, 2 },
90 /* Known SAMD21 parts. */
91 static const struct samd_part samd21_parts[] = {
92 { 0x0, "SAMD21J18A", 256, 32 },
93 { 0x1, "SAMD21J17A", 128, 16 },
94 { 0x2, "SAMD21J16A", 64, 8 },
95 { 0x3, "SAMD21J15A", 32, 4 },
96 { 0x4, "SAMD21J14A", 16, 2 },
97 { 0x5, "SAMD21G18A", 256, 32 },
98 { 0x6, "SAMD21G17A", 128, 16 },
99 { 0x7, "SAMD21G16A", 64, 8 },
100 { 0x8, "SAMD21G15A", 32, 4 },
101 { 0x9, "SAMD21G14A", 16, 2 },
102 { 0xA, "SAMD21E18A", 256, 32 },
103 { 0xB, "SAMD21E17A", 128, 16 },
104 { 0xC, "SAMD21E16A", 64, 8 },
105 { 0xD, "SAMD21E15A", 32, 4 },
106 { 0xE, "SAMD21E14A", 16, 2 },
109 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
110 * processor ID, family ID, and series ID are used to determine which exact
111 * family this is and then we can use the corresponding table. */
116 const struct samd_part *parts;
120 /* Known SAMD families */
121 static const struct samd_family samd_families[] = {
122 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
123 samd20_parts, ARRAY_SIZE(samd20_parts) },
124 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
125 samd21_parts, ARRAY_SIZE(samd21_parts) },
134 struct target *target;
135 struct samd_info *next;
138 static struct samd_info *samd_chips;
140 static const struct samd_part *samd_find_part(uint32_t id)
142 uint8_t processor = (id >> 28);
143 uint8_t family = (id >> 24) & 0x0F;
144 uint8_t series = (id >> 16) & 0xFF;
145 uint8_t devsel = id & 0xFF;
147 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
148 if (samd_families[i].processor == processor &&
149 samd_families[i].series == series &&
150 samd_families[i].family == family) {
151 for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
152 if (samd_families[i].parts[j].id == devsel)
153 return &samd_families[i].parts[j];
161 static int samd_protect_check(struct flash_bank *bank)
166 res = target_read_u16(bank->target,
167 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
171 /* Lock bits are active-low */
172 for (int i = 0; i < bank->num_sectors; i++)
173 bank->sectors[i].is_protected = !(lock & (1<<i));
178 static int samd_probe(struct flash_bank *bank)
182 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
183 const struct samd_part *part;
188 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
189 if (res != ERROR_OK) {
190 LOG_ERROR("Couldn't read Device ID register");
194 part = samd_find_part(id);
196 LOG_ERROR("Couldn't find part correspoding to DID %08" PRIx32, id);
200 res = target_read_u32(bank->target,
201 SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m);
202 if (res != ERROR_OK) {
203 LOG_ERROR("Couldn't read NVM Parameters register");
207 bank->size = part->flash_kb * 1024;
209 chip->sector_size = bank->size / SAMD_NUM_SECTORS;
211 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n) so
212 * 0 is 8KB and 7 is 1024KB. */
213 chip->page_size = (8 << ((param >> 16) & 0x7));
214 /* The NVMP field (bits 15:0) indicates the total number of pages */
215 chip->num_pages = param & 0xFFFF;
217 /* Sanity check: the total flash size in the DSU should match the page size
218 * multiplied by the number of pages. */
219 if (bank->size != chip->num_pages * chip->page_size) {
220 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
221 "Identified %uKB Flash but NVMCTRL reports %u %uB pages",
222 part->flash_kb, chip->num_pages, chip->page_size);
225 /* Allocate the sector table */
226 bank->num_sectors = SAMD_NUM_SECTORS;
227 bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
231 /* Fill out the sector information: all SAMD sectors are the same size and
232 * there is always a fixed number of them. */
233 for (int i = 0; i < bank->num_sectors; i++) {
234 bank->sectors[i].size = chip->sector_size;
235 bank->sectors[i].offset = i * chip->sector_size;
236 /* mark as unknown */
237 bank->sectors[i].is_erased = -1;
238 bank->sectors[i].is_protected = -1;
241 samd_protect_check(bank);
246 LOG_INFO("SAMD MCU: %s (%uKB Flash, %uKB RAM)", part->name,
247 part->flash_kb, part->ram_kb);
252 static int samd_protect(struct flash_bank *bank, int set, int first, int last)
255 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
257 for (int s = first; s <= last; s++) {
258 /* Load an address that is within this sector (we use offset 0) */
259 res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
260 s * chip->sector_size);
264 /* Tell the controller to lock that sector */
265 res = target_write_u16(bank->target,
266 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
267 SAMD_NVM_CMD(SAMD_NVM_CMD_LR));
272 samd_protect_check(bank);
277 static bool samd_check_error(struct flash_bank *bank)
283 ret = target_read_u16(bank->target,
284 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
285 if (ret != ERROR_OK) {
286 LOG_ERROR("Can't read NVM status");
290 if (status & 0x001C) {
291 if (status & (1 << 4)) /* NVME */
292 LOG_ERROR("SAMD: NVM Error");
293 if (status & (1 << 3)) /* LOCKE */
294 LOG_ERROR("SAMD: NVM lock error");
295 if (status & (1 << 2)) /* PROGE */
296 LOG_ERROR("SAMD: NVM programming error");
303 /* Clear the error conditions by writing a one to them */
304 ret = target_write_u16(bank->target,
305 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
307 LOG_ERROR("Can't clear NVM error conditions");
312 static int samd_erase_row(struct flash_bank *bank, uint32_t address)
317 /* Set an address contained in the row to be erased */
318 res = target_write_u32(bank->target,
319 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
320 if (res == ERROR_OK) {
321 /* Issue the Erase Row command to erase that row */
322 res = target_write_u16(bank->target,
323 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
324 SAMD_NVM_CMD(SAMD_NVM_CMD_ER));
326 /* Check (and clear) error conditions */
327 error = samd_check_error(bank);
330 if (res != ERROR_OK || error) {
331 LOG_ERROR("Failed to erase row containing %08X" PRIx32, address);
338 static int samd_erase(struct flash_bank *bank, int first, int last)
342 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
344 if (bank->target->state != TARGET_HALTED) {
345 LOG_ERROR("Target not halted");
347 return ERROR_TARGET_NOT_HALTED;
351 if (samd_probe(bank) != ERROR_OK)
352 return ERROR_FLASH_BANK_NOT_PROBED;
355 /* Make sure the sectors make sense. */
356 if (first >= bank->num_sectors || last >= bank->num_sectors) {
357 LOG_ERROR("Erase range %d - %d not valid (%d sectors total)",
358 first, last, bank->num_sectors);
362 /* The SAMD NVM has row erase granularity. There are four pages in a row
363 * and the number of rows in a sector depends on the sector size, which in
364 * turn depends on the Flash capacity as there is a fixed number of
366 rows_in_sector = chip->sector_size / (chip->page_size * 4);
368 /* For each sector to be erased */
369 for (int s = first; s <= last; s++) {
370 /* For each row in that sector */
371 for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
372 res = samd_erase_row(bank, r * chip->page_size * 4);
373 if (res != ERROR_OK) {
374 LOG_ERROR("SAMD: failed to erase sector %d", s);
379 bank->sectors[s].is_erased = 1;
385 /* Write an entire row (four pages) from host buffer 'buf' to row-aligned
386 * 'address' in the Flash. */
387 static int samd_write_row(struct flash_bank *bank, uint32_t address,
391 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
393 /* Erase the row that we'll be writing to */
394 res = samd_erase_row(bank, address);
398 /* Now write the pages in this row. */
399 for (unsigned int i = 0; i < 4; i++) {
402 /* Write the page contents to the target's page buffer. A page write
403 * is issued automatically once the last location is written in the
404 * page buffer (ie: a complete page has been written out). */
405 res = target_write_memory(bank->target, address, 4,
406 chip->page_size / 4, buf);
407 if (res != ERROR_OK) {
408 LOG_ERROR("%s: %d", __func__, __LINE__);
412 error = samd_check_error(bank);
417 address += chip->page_size;
418 buf += chip->page_size;
424 /* Write partial contents into row-aligned 'address' on the Flash from host
425 * buffer 'buf' by writing 'nb' of 'buf' at 'row_offset' into the Flash row. */
426 static int samd_write_row_partial(struct flash_bank *bank, uint32_t address,
427 const uint8_t *buf, uint32_t row_offset, uint32_t nb)
430 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
431 uint32_t row_size = chip->page_size * 4;
432 uint8_t *rb = malloc(row_size);
436 assert(row_offset + nb < row_size);
437 assert((address % row_size) == 0);
439 /* Retrieve the full row contents from Flash */
440 res = target_read_memory(bank->target, address, 4, row_size / 4, rb);
441 if (res != ERROR_OK) {
446 /* Insert our partial row over the data from Flash */
447 memcpy(rb + (row_offset % row_size), buf, nb);
449 /* Write the row back out */
450 res = samd_write_row(bank, address, rb);
456 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
457 uint32_t offset, uint32_t count)
462 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
463 uint32_t row_size = chip->page_size * 4;
465 if (bank->target->state != TARGET_HALTED) {
466 LOG_ERROR("Target not halted");
468 return ERROR_TARGET_NOT_HALTED;
472 if (samd_probe(bank) != ERROR_OK)
473 return ERROR_FLASH_BANK_NOT_PROBED;
476 if (offset % row_size) {
477 /* We're starting at an unaligned offset so we'll write a partial row
478 * comprising that offset and up to the end of that row. */
479 nb = row_size - (offset % row_size);
482 } else if (count < row_size) {
483 /* We're writing an aligned but partial row. */
487 address = (offset / row_size) * row_size + bank->base;
490 res = samd_write_row_partial(bank, address, buffer,
491 offset % row_size, nb);
495 /* We're done with the row contents */
501 /* There's at least one aligned row to write out. */
502 if (count >= row_size) {
503 int nr = count / row_size + ((count % row_size) ? 1 : 0);
506 for (unsigned int i = address / row_size;
507 (i < (address / row_size) + nr) && count > 0; i++) {
508 address = (i * row_size) + bank->base;
510 if (count >= row_size) {
511 res = samd_write_row(bank, address, buffer + (r * row_size));
512 /* Advance one row */
516 res = samd_write_row_partial(bank, address,
517 buffer + (r * row_size), 0, count);
518 /* We're done after this. */
533 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
535 struct samd_info *chip = samd_chips;
538 if (chip->target == bank->target)
544 /* Create a new chip */
545 chip = calloc(1, sizeof(*chip));
549 chip->target = bank->target;
550 chip->probed = false;
552 bank->driver_priv = chip;
554 /* Insert it into the chips list (at head) */
555 chip->next = samd_chips;
559 if (bank->base != SAMD_FLASH) {
560 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
561 "[at91samd series] )",
562 bank->base, SAMD_FLASH);
569 COMMAND_HANDLER(samd_handle_info_command)
574 static const struct command_registration at91samd_exec_command_handlers[] = {
577 .handler = samd_handle_info_command,
578 .mode = COMMAND_EXEC,
579 .help = "Print information about the current at91samd chip"
580 "and its flash configuration.",
582 COMMAND_REGISTRATION_DONE
585 static const struct command_registration at91samd_command_handlers[] = {
589 .help = "at91samd flash command group",
591 .chain = at91samd_exec_command_handlers,
593 COMMAND_REGISTRATION_DONE
596 struct flash_driver at91samd_flash = {
598 .commands = at91samd_command_handlers,
599 .flash_bank_command = samd_flash_bank_command,
601 .protect = samd_protect,
603 .read = default_flash_read,
605 .auto_probe = samd_probe,
606 .erase_check = default_flash_blank_check,
607 .protect_check = samd_protect_check,