1 /***************************************************************************
2 * Copyright (C) 2013 by Andrey Yurovsky *
3 * Andrey Yurovsky <yurovsky@gmail.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
27 #define SAMD_NUM_SECTORS 16
29 #define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
30 #define SAMD_DSU 0x41002000 /* Device Service Unit */
31 #define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
33 #define SAMD_DSU_DID 0x18 /* Device ID register */
35 #define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
36 #define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
37 #define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
38 #define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
39 #define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
40 #define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
41 #define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
43 #define SAMD_CMDEX_KEY 0xA5UL
44 #define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
46 /* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
47 #define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
48 #define SAMD_NVM_CMD_WP 0x04 /* Write Page */
49 #define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
50 #define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
51 #define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
52 #define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
53 #define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
54 #define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
55 #define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
56 #define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
57 #define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
59 /* Known identifiers */
60 #define SAMD_PROCESSOR_M0 0x01
61 #define SAMD_FAMILY_D 0x00
62 #define SAMD_SERIES_20 0x00
63 #define SAMD_SERIES_21 0x01
64 #define SAMD_SERIES_10 0x02
65 #define SAMD_SERIES_11 0x03
74 /* Known SAMD10 parts */
75 static const struct samd_part samd10_parts[] = {
76 { 0x0, "SAMD10D14AMU", 16, 4 },
77 { 0x1, "SAMD10D13AMU", 8, 4 },
78 { 0x2, "SAMD10D12AMU", 4, 4 },
79 { 0x3, "SAMD10D14ASU", 16, 4 },
80 { 0x4, "SAMD10D13ASU", 8, 4 },
81 { 0x5, "SAMD10D12ASU", 4, 4 },
82 { 0x6, "SAMD10C14A", 16, 4 },
83 { 0x7, "SAMD10C13A", 8, 4 },
84 { 0x8, "SAMD10C12A", 4, 4 },
87 /* Known SAMD11 parts */
88 static const struct samd_part samd11_parts[] = {
89 { 0x0, "SAMD11D14AMU", 16, 4 },
90 { 0x1, "SAMD11D13AMU", 8, 4 },
91 { 0x2, "SAMD11D12AMU", 4, 4 },
92 { 0x3, "SAMD11D14ASU", 16, 4 },
93 { 0x4, "SAMD11D13ASU", 8, 4 },
94 { 0x5, "SAMD11D12ASU", 4, 4 },
95 { 0x6, "SAMD11C14A", 16, 4 },
96 { 0x7, "SAMD11C13A", 8, 4 },
97 { 0x8, "SAMD11C12A", 4, 4 },
100 /* Known SAMD20 parts. See Table 12-8 in 42129F–SAM–10/2013 */
101 static const struct samd_part samd20_parts[] = {
102 { 0x0, "SAMD20J18A", 256, 32 },
103 { 0x1, "SAMD20J17A", 128, 16 },
104 { 0x2, "SAMD20J16A", 64, 8 },
105 { 0x3, "SAMD20J15A", 32, 4 },
106 { 0x4, "SAMD20J14A", 16, 2 },
107 { 0x5, "SAMD20G18A", 256, 32 },
108 { 0x6, "SAMD20G17A", 128, 16 },
109 { 0x7, "SAMD20G16A", 64, 8 },
110 { 0x8, "SAMD20G15A", 32, 4 },
111 { 0x9, "SAMD20G14A", 16, 2 },
112 { 0xB, "SAMD20E17A", 128, 16 },
113 { 0xC, "SAMD20E16A", 64, 8 },
114 { 0xD, "SAMD20E15A", 32, 4 },
115 { 0xE, "SAMD20E14A", 16, 2 },
118 /* Known SAMD21 parts. */
119 static const struct samd_part samd21_parts[] = {
120 { 0x0, "SAMD21J18A", 256, 32 },
121 { 0x1, "SAMD21J17A", 128, 16 },
122 { 0x2, "SAMD21J16A", 64, 8 },
123 { 0x3, "SAMD21J15A", 32, 4 },
124 { 0x4, "SAMD21J14A", 16, 2 },
125 { 0x5, "SAMD21G18A", 256, 32 },
126 { 0x6, "SAMD21G17A", 128, 16 },
127 { 0x7, "SAMD21G16A", 64, 8 },
128 { 0x8, "SAMD21G15A", 32, 4 },
129 { 0x9, "SAMD21G14A", 16, 2 },
130 { 0xA, "SAMD21E18A", 256, 32 },
131 { 0xB, "SAMD21E17A", 128, 16 },
132 { 0xC, "SAMD21E16A", 64, 8 },
133 { 0xD, "SAMD21E15A", 32, 4 },
134 { 0xE, "SAMD21E14A", 16, 2 },
137 /* Each family of parts contains a parts table in the DEVSEL field of DID. The
138 * processor ID, family ID, and series ID are used to determine which exact
139 * family this is and then we can use the corresponding table. */
144 const struct samd_part *parts;
148 /* Known SAMD families */
149 static const struct samd_family samd_families[] = {
150 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
151 samd20_parts, ARRAY_SIZE(samd20_parts) },
152 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
153 samd21_parts, ARRAY_SIZE(samd21_parts) },
154 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
155 samd10_parts, ARRAY_SIZE(samd10_parts) },
156 { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
157 samd11_parts, ARRAY_SIZE(samd11_parts) },
166 struct target *target;
167 struct samd_info *next;
170 static struct samd_info *samd_chips;
172 static const struct samd_part *samd_find_part(uint32_t id)
174 uint8_t processor = (id >> 28);
175 uint8_t family = (id >> 24) & 0x0F;
176 uint8_t series = (id >> 16) & 0xFF;
177 uint8_t devsel = id & 0xFF;
179 for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
180 if (samd_families[i].processor == processor &&
181 samd_families[i].series == series &&
182 samd_families[i].family == family) {
183 for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
184 if (samd_families[i].parts[j].id == devsel)
185 return &samd_families[i].parts[j];
193 static int samd_protect_check(struct flash_bank *bank)
198 res = target_read_u16(bank->target,
199 SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
203 /* Lock bits are active-low */
204 for (int i = 0; i < bank->num_sectors; i++)
205 bank->sectors[i].is_protected = !(lock & (1<<i));
210 static int samd_probe(struct flash_bank *bank)
214 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
215 const struct samd_part *part;
220 res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
221 if (res != ERROR_OK) {
222 LOG_ERROR("Couldn't read Device ID register");
226 part = samd_find_part(id);
228 LOG_ERROR("Couldn't find part correspoding to DID %08" PRIx32, id);
232 res = target_read_u32(bank->target,
233 SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m);
234 if (res != ERROR_OK) {
235 LOG_ERROR("Couldn't read NVM Parameters register");
239 bank->size = part->flash_kb * 1024;
241 chip->sector_size = bank->size / SAMD_NUM_SECTORS;
243 /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n) so
244 * 0 is 8KB and 7 is 1024KB. */
245 chip->page_size = (8 << ((param >> 16) & 0x7));
246 /* The NVMP field (bits 15:0) indicates the total number of pages */
247 chip->num_pages = param & 0xFFFF;
249 /* Sanity check: the total flash size in the DSU should match the page size
250 * multiplied by the number of pages. */
251 if (bank->size != chip->num_pages * chip->page_size) {
252 LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
253 "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
254 part->flash_kb, chip->num_pages, chip->page_size);
257 /* Allocate the sector table */
258 bank->num_sectors = SAMD_NUM_SECTORS;
259 bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
263 /* Fill out the sector information: all SAMD sectors are the same size and
264 * there is always a fixed number of them. */
265 for (int i = 0; i < bank->num_sectors; i++) {
266 bank->sectors[i].size = chip->sector_size;
267 bank->sectors[i].offset = i * chip->sector_size;
268 /* mark as unknown */
269 bank->sectors[i].is_erased = -1;
270 bank->sectors[i].is_protected = -1;
273 samd_protect_check(bank);
278 LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
279 part->flash_kb, part->ram_kb);
284 static int samd_protect(struct flash_bank *bank, int set, int first, int last)
287 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
291 for (int s = first; s <= last; s++) {
292 if (set != bank->sectors[s].is_protected) {
293 /* Load an address that is within this sector (we use offset 0) */
294 res = target_write_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
295 s * chip->sector_size);
299 /* Tell the controller to lock that sector */
301 uint16_t cmd = (set) ?
302 SAMD_NVM_CMD(SAMD_NVM_CMD_LR) :
303 SAMD_NVM_CMD(SAMD_NVM_CMD_UR);
305 res = target_write_u16(bank->target,
306 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
313 samd_protect_check(bank);
318 static bool samd_check_error(struct flash_bank *bank)
324 ret = target_read_u16(bank->target,
325 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
326 if (ret != ERROR_OK) {
327 LOG_ERROR("Can't read NVM status");
331 if (status & 0x001C) {
332 if (status & (1 << 4)) /* NVME */
333 LOG_ERROR("SAMD: NVM Error");
334 if (status & (1 << 3)) /* LOCKE */
335 LOG_ERROR("SAMD: NVM lock error");
336 if (status & (1 << 2)) /* PROGE */
337 LOG_ERROR("SAMD: NVM programming error");
344 /* Clear the error conditions by writing a one to them */
345 ret = target_write_u16(bank->target,
346 SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
348 LOG_ERROR("Can't clear NVM error conditions");
353 static int samd_erase_row(struct flash_bank *bank, uint32_t address)
358 /* Set an address contained in the row to be erased */
359 res = target_write_u32(bank->target,
360 SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
361 if (res == ERROR_OK) {
362 /* Issue the Erase Row command to erase that row */
363 res = target_write_u16(bank->target,
364 SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA,
365 SAMD_NVM_CMD(SAMD_NVM_CMD_ER));
367 /* Check (and clear) error conditions */
368 error = samd_check_error(bank);
371 if (res != ERROR_OK || error) {
372 LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
379 static int samd_erase(struct flash_bank *bank, int first, int last)
383 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
385 if (bank->target->state != TARGET_HALTED) {
386 LOG_ERROR("Target not halted");
388 return ERROR_TARGET_NOT_HALTED;
392 if (samd_probe(bank) != ERROR_OK)
393 return ERROR_FLASH_BANK_NOT_PROBED;
396 /* The SAMD NVM has row erase granularity. There are four pages in a row
397 * and the number of rows in a sector depends on the sector size, which in
398 * turn depends on the Flash capacity as there is a fixed number of
400 rows_in_sector = chip->sector_size / (chip->page_size * 4);
402 /* For each sector to be erased */
403 for (int s = first; s <= last; s++) {
404 if (bank->sectors[s].is_protected) {
405 LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s);
406 return ERROR_FLASH_OPERATION_FAILED;
409 if (!bank->sectors[s].is_erased) {
410 /* For each row in that sector */
411 for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
412 res = samd_erase_row(bank, r * chip->page_size * 4);
413 if (res != ERROR_OK) {
414 LOG_ERROR("SAMD: failed to erase sector %d", s);
419 bank->sectors[s].is_erased = 1;
426 static struct flash_sector *samd_find_sector_by_address(struct flash_bank *bank, uint32_t address)
428 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
430 for (int i = 0; i < bank->num_sectors; i++) {
431 if (bank->sectors[i].offset <= address &&
432 address < bank->sectors[i].offset + chip->sector_size)
433 return &bank->sectors[i];
438 /* Write an entire row (four pages) from host buffer 'buf' to row-aligned
439 * 'address' in the Flash. */
440 static int samd_write_row(struct flash_bank *bank, uint32_t address,
444 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
446 struct flash_sector *sector = samd_find_sector_by_address(bank, address);
449 LOG_ERROR("Can't find sector corresponding to address 0x%08" PRIx32, address);
450 return ERROR_FLASH_OPERATION_FAILED;
453 if (sector->is_protected) {
454 LOG_ERROR("Trying to write to a protected sector at 0x%08" PRIx32, address);
455 return ERROR_FLASH_OPERATION_FAILED;
458 /* Erase the row that we'll be writing to */
459 res = samd_erase_row(bank, address);
463 /* Now write the pages in this row. */
464 for (unsigned int i = 0; i < 4; i++) {
467 /* Write the page contents to the target's page buffer. A page write
468 * is issued automatically once the last location is written in the
469 * page buffer (ie: a complete page has been written out). */
470 res = target_write_memory(bank->target, address, 4,
471 chip->page_size / 4, buf);
472 if (res != ERROR_OK) {
473 LOG_ERROR("%s: %d", __func__, __LINE__);
477 error = samd_check_error(bank);
482 address += chip->page_size;
483 buf += chip->page_size;
486 sector->is_erased = 0;
491 /* Write partial contents into row-aligned 'address' on the Flash from host
492 * buffer 'buf' by writing 'nb' of 'buf' at 'row_offset' into the Flash row. */
493 static int samd_write_row_partial(struct flash_bank *bank, uint32_t address,
494 const uint8_t *buf, uint32_t row_offset, uint32_t nb)
497 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
498 uint32_t row_size = chip->page_size * 4;
499 uint8_t *rb = malloc(row_size);
503 assert(row_offset + nb < row_size);
504 assert((address % row_size) == 0);
506 /* Retrieve the full row contents from Flash */
507 res = target_read_memory(bank->target, address, 4, row_size / 4, rb);
508 if (res != ERROR_OK) {
513 /* Insert our partial row over the data from Flash */
514 memcpy(rb + (row_offset % row_size), buf, nb);
516 /* Write the row back out */
517 res = samd_write_row(bank, address, rb);
523 static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
524 uint32_t offset, uint32_t count)
529 struct samd_info *chip = (struct samd_info *)bank->driver_priv;
530 uint32_t row_size = chip->page_size * 4;
532 if (bank->target->state != TARGET_HALTED) {
533 LOG_ERROR("Target not halted");
535 return ERROR_TARGET_NOT_HALTED;
539 if (samd_probe(bank) != ERROR_OK)
540 return ERROR_FLASH_BANK_NOT_PROBED;
543 if (offset % row_size) {
544 /* We're starting at an unaligned offset so we'll write a partial row
545 * comprising that offset and up to the end of that row. */
546 nb = row_size - (offset % row_size);
549 } else if (count < row_size) {
550 /* We're writing an aligned but partial row. */
554 address = (offset / row_size) * row_size + bank->base;
557 res = samd_write_row_partial(bank, address, buffer,
558 offset % row_size, nb);
562 /* We're done with the row contents */
568 /* There's at least one aligned row to write out. */
569 if (count >= row_size) {
570 int nr = count / row_size + ((count % row_size) ? 1 : 0);
573 for (unsigned int i = address / row_size;
574 (i < (address / row_size) + nr) && count > 0; i++) {
575 address = (i * row_size) + bank->base;
577 if (count >= row_size) {
578 res = samd_write_row(bank, address, buffer + (r * row_size));
579 /* Advance one row */
583 res = samd_write_row_partial(bank, address,
584 buffer + (r * row_size), 0, count);
585 /* We're done after this. */
600 FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
602 struct samd_info *chip = samd_chips;
605 if (chip->target == bank->target)
611 /* Create a new chip */
612 chip = calloc(1, sizeof(*chip));
616 chip->target = bank->target;
617 chip->probed = false;
619 bank->driver_priv = chip;
621 /* Insert it into the chips list (at head) */
622 chip->next = samd_chips;
626 if (bank->base != SAMD_FLASH) {
627 LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
628 "[at91samd series] )",
629 bank->base, SAMD_FLASH);
636 COMMAND_HANDLER(samd_handle_info_command)
641 static const struct command_registration at91samd_exec_command_handlers[] = {
644 .handler = samd_handle_info_command,
645 .mode = COMMAND_EXEC,
646 .help = "Print information about the current at91samd chip"
647 "and its flash configuration.",
649 COMMAND_REGISTRATION_DONE
652 static const struct command_registration at91samd_command_handlers[] = {
656 .help = "at91samd flash command group",
658 .chain = at91samd_exec_command_handlers,
660 COMMAND_REGISTRATION_DONE
663 struct flash_driver at91samd_flash = {
665 .commands = at91samd_command_handlers,
666 .flash_bank_command = samd_flash_bank_command,
668 .protect = samd_protect,
670 .read = default_flash_read,
672 .auto_probe = samd_probe,
673 .erase_check = default_flash_blank_check,
674 .protect_check = samd_protect_check,