1 /***************************************************************************
2 * Copyright (C) 2005, 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * Copyright (C) 2009 Michael Schwingen *
5 * michael@schwingen.org *
6 * Copyright (C) 2010 Øyvind Harboe <oyvind.harboe@zylin.com> *
7 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
9 * This program is free software; you can redistribute it and/or modify *
10 * it under the terms of the GNU General Public License as published by *
11 * the Free Software Foundation; either version 2 of the License, or *
12 * (at your option) any later version. *
14 * This program is distributed in the hope that it will be useful, *
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
17 * GNU General Public License for more details. *
19 * You should have received a copy of the GNU General Public License *
20 * along with this program; if not, write to the *
21 * Free Software Foundation, Inc., *
22 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
23 ***************************************************************************/
31 #include <target/arm.h>
32 #include <target/armv7m.h>
33 #include <helper/binarybuffer.h>
34 #include <target/algorithm.h>
37 #define CFI_MAX_BUS_WIDTH 4
38 #define CFI_MAX_CHIP_WIDTH 4
40 /* defines internal maximum size for code fragment in cfi_intel_write_block() */
41 #define CFI_MAX_INTEL_CODESIZE 256
43 static struct cfi_unlock_addresses cfi_unlock_addresses[] =
45 [CFI_UNLOCK_555_2AA] = { .unlock1 = 0x555, .unlock2 = 0x2aa },
46 [CFI_UNLOCK_5555_2AAA] = { .unlock1 = 0x5555, .unlock2 = 0x2aaa },
49 /* CFI fixups foward declarations */
50 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param);
51 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param);
52 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param);
53 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param);
55 /* fixup after reading cmdset 0002 primary query table */
56 static const struct cfi_fixup cfi_0002_fixups[] = {
57 {CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
58 {CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
59 {CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
60 {CFI_MFR_SST, 0x00D7, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
61 {CFI_MFR_SST, 0x2780, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
62 {CFI_MFR_SST, 0x236d, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
63 {CFI_MFR_ATMEL, 0x00C8, cfi_fixup_reversed_erase_regions, NULL},
64 {CFI_MFR_ST, 0x22C4, cfi_fixup_reversed_erase_regions, NULL}, /* M29W160ET */
65 {CFI_MFR_FUJITSU, 0x22ea, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
66 {CFI_MFR_FUJITSU, 0x226b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
67 {CFI_MFR_AMIC, 0xb31a, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
68 {CFI_MFR_MX, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
69 {CFI_MFR_AMD, 0x225b, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_555_2AA]},
70 {CFI_MFR_ANY, CFI_ID_ANY, cfi_fixup_0002_erase_regions, NULL},
71 {CFI_MFR_ST, 0x227E, cfi_fixup_0002_write_buffer, NULL}, /* M29W128G */
75 /* fixup after reading cmdset 0001 primary query table */
76 static const struct cfi_fixup cfi_0001_fixups[] = {
80 static void cfi_fixup(struct flash_bank *bank, const struct cfi_fixup *fixups)
82 struct cfi_flash_bank *cfi_info = bank->driver_priv;
83 const struct cfi_fixup *f;
85 for (f = fixups; f->fixup; f++)
87 if (((f->mfr == CFI_MFR_ANY) || (f->mfr == cfi_info->manufacturer)) &&
88 ((f->id == CFI_ID_ANY) || (f->id == cfi_info->device_id)))
90 f->fixup(bank, f->param);
95 /* inline uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset) */
96 static __inline__ uint32_t flash_address(struct flash_bank *bank, int sector, uint32_t offset)
98 struct cfi_flash_bank *cfi_info = bank->driver_priv;
100 if (cfi_info->x16_as_x8) offset *= 2;
102 /* while the sector list isn't built, only accesses to sector 0 work */
104 return bank->base + offset * bank->bus_width;
109 LOG_ERROR("BUG: sector list not yet built");
112 return bank->base + bank->sectors[sector].offset + offset * bank->bus_width;
116 static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
120 /* clear whole buffer, to ensure bits that exceed the bus_width
123 for (i = 0; i < CFI_MAX_BUS_WIDTH; i++)
126 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
128 for (i = bank->bus_width; i > 0; i--)
130 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
135 for (i = 1; i <= bank->bus_width; i++)
137 *cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
142 static int cfi_send_command(struct flash_bank *bank, uint8_t cmd, uint32_t address)
144 uint8_t command[CFI_MAX_BUS_WIDTH];
146 cfi_command(bank, cmd, command);
147 return target_write_memory(bank->target, address, bank->bus_width, 1, command);
150 /* read unsigned 8-bit value from the bank
151 * flash banks are expected to be made of similar chips
152 * the query result should be the same for all
154 static int cfi_query_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
156 struct target *target = bank->target;
157 uint8_t data[CFI_MAX_BUS_WIDTH];
160 retval = target_read_memory(target, flash_address(bank, sector, offset),
161 bank->bus_width, 1, data);
162 if (retval != ERROR_OK)
165 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
168 *val = data[bank->bus_width - 1];
173 /* read unsigned 8-bit value from the bank
174 * in case of a bank made of multiple chips,
175 * the individual values are ORed
177 static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint8_t *val)
179 struct target *target = bank->target;
180 uint8_t data[CFI_MAX_BUS_WIDTH];
184 retval = target_read_memory(target, flash_address(bank, sector, offset),
185 bank->bus_width, 1, data);
186 if (retval != ERROR_OK)
189 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
191 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
199 for (i = 0; i < bank->bus_width / bank->chip_width; i++)
200 value |= data[bank->bus_width - 1 - i];
207 static int cfi_query_u16(struct flash_bank *bank, int sector, uint32_t offset, uint16_t *val)
209 struct target *target = bank->target;
210 struct cfi_flash_bank *cfi_info = bank->driver_priv;
211 uint8_t data[CFI_MAX_BUS_WIDTH * 2];
214 if (cfi_info->x16_as_x8)
217 for (i = 0;i < 2;i++)
219 retval = target_read_memory(target, flash_address(bank, sector, offset + i),
220 bank->bus_width, 1, &data[i * bank->bus_width]);
221 if (retval != ERROR_OK)
226 retval = target_read_memory(target, flash_address(bank, sector, offset),
227 bank->bus_width, 2, data);
228 if (retval != ERROR_OK)
232 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
233 *val = data[0] | data[bank->bus_width] << 8;
235 *val = data[bank->bus_width - 1] | data[(2 * bank->bus_width) - 1] << 8;
240 static int cfi_query_u32(struct flash_bank *bank, int sector, uint32_t offset, uint32_t *val)
242 struct target *target = bank->target;
243 struct cfi_flash_bank *cfi_info = bank->driver_priv;
244 uint8_t data[CFI_MAX_BUS_WIDTH * 4];
247 if (cfi_info->x16_as_x8)
250 for (i = 0;i < 4;i++)
252 retval = target_read_memory(target, flash_address(bank, sector, offset + i),
253 bank->bus_width, 1, &data[i * bank->bus_width]);
254 if (retval != ERROR_OK)
260 retval = target_read_memory(target, flash_address(bank, sector, offset),
261 bank->bus_width, 4, data);
262 if (retval != ERROR_OK)
266 if (bank->target->endianness == TARGET_LITTLE_ENDIAN)
267 *val = data[0] | data[bank->bus_width] << 8 |
268 data[bank->bus_width * 2] << 16 | data[bank->bus_width * 3] << 24;
270 *val = data[bank->bus_width - 1] | data[(2* bank->bus_width) - 1] << 8 |
271 data[(3 * bank->bus_width) - 1] << 16 | data[(4 * bank->bus_width) - 1] << 24;
276 static int cfi_reset(struct flash_bank *bank)
278 struct cfi_flash_bank *cfi_info = bank->driver_priv;
279 int retval = ERROR_OK;
281 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
286 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
291 if (cfi_info->manufacturer == 0x20 &&
292 (cfi_info->device_id == 0x227E || cfi_info->device_id == 0x7E))
294 /* Numonix M29W128G is cmd 0xFF intolerant - causes internal undefined state
295 * so we send an extra 0xF0 reset to fix the bug */
296 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x00))) != ERROR_OK)
305 static void cfi_intel_clear_status_register(struct flash_bank *bank)
307 struct target *target = bank->target;
309 if (target->state != TARGET_HALTED)
311 LOG_ERROR("BUG: attempted to clear status register while target wasn't halted");
315 cfi_send_command(bank, 0x50, flash_address(bank, 0, 0x0));
318 static int cfi_intel_wait_status_busy(struct flash_bank *bank, int timeout, uint8_t *val)
322 int retval = ERROR_OK;
328 LOG_ERROR("timeout while waiting for WSM to become ready");
332 retval = cfi_get_u8(bank, 0, 0x0, &status);
333 if (retval != ERROR_OK)
342 /* mask out bit 0 (reserved) */
343 status = status & 0xfe;
345 LOG_DEBUG("status: 0x%x", status);
349 LOG_ERROR("status register: 0x%x", status);
351 LOG_ERROR("Block Lock-Bit Detected, Operation Abort");
353 LOG_ERROR("Program suspended");
355 LOG_ERROR("Low Programming Voltage Detected, Operation Aborted");
357 LOG_ERROR("Program Error / Error in Setting Lock-Bit");
359 LOG_ERROR("Error in Block Erasure or Clear Lock-Bits");
361 LOG_ERROR("Block Erase Suspended");
363 cfi_intel_clear_status_register(bank);
372 static int cfi_spansion_wait_status_busy(struct flash_bank *bank, int timeout)
374 uint8_t status, oldstatus;
375 struct cfi_flash_bank *cfi_info = bank->driver_priv;
378 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
379 if (retval != ERROR_OK)
383 retval = cfi_get_u8(bank, 0, 0x0, &status);
385 if (retval != ERROR_OK)
388 if ((status ^ oldstatus) & 0x40) {
389 if (status & cfi_info->status_poll_mask & 0x20) {
390 retval = cfi_get_u8(bank, 0, 0x0, &oldstatus);
391 if (retval != ERROR_OK)
393 retval = cfi_get_u8(bank, 0, 0x0, &status);
394 if (retval != ERROR_OK)
396 if ((status ^ oldstatus) & 0x40) {
397 LOG_ERROR("dq5 timeout, status: 0x%x", status);
398 return(ERROR_FLASH_OPERATION_FAILED);
400 LOG_DEBUG("status: 0x%x", status);
404 } else { /* no toggle: finished, OK */
405 LOG_DEBUG("status: 0x%x", status);
411 } while (timeout-- > 0);
413 LOG_ERROR("timeout, status: 0x%x", status);
415 return(ERROR_FLASH_BUSY);
418 static int cfi_read_intel_pri_ext(struct flash_bank *bank)
421 struct cfi_flash_bank *cfi_info = bank->driver_priv;
422 struct cfi_intel_pri_ext *pri_ext;
424 if (cfi_info->pri_ext)
425 free(cfi_info->pri_ext);
427 pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
430 LOG_ERROR("Out of memory");
433 cfi_info->pri_ext = pri_ext;
435 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
436 if (retval != ERROR_OK)
438 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
439 if (retval != ERROR_OK)
441 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
442 if (retval != ERROR_OK)
445 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
447 if ((retval = cfi_reset(bank)) != ERROR_OK)
451 LOG_ERROR("Could not read bank flash bank information");
452 return ERROR_FLASH_BANK_INVALID;
455 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
456 if (retval != ERROR_OK)
458 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
459 if (retval != ERROR_OK)
462 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
463 pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
465 retval = cfi_query_u32(bank, 0, cfi_info->pri_addr + 5, &pri_ext->feature_support);
466 if (retval != ERROR_OK)
468 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->suspend_cmd_support);
469 if (retval != ERROR_OK)
471 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xa, &pri_ext->blk_status_reg_mask);
472 if (retval != ERROR_OK)
475 LOG_DEBUG("feature_support: 0x%" PRIx32 ", suspend_cmd_support: "
476 "0x%x, blk_status_reg_mask: 0x%x",
477 pri_ext->feature_support,
478 pri_ext->suspend_cmd_support,
479 pri_ext->blk_status_reg_mask);
481 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xc, &pri_ext->vcc_optimal);
482 if (retval != ERROR_OK)
484 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xd, &pri_ext->vpp_optimal);
485 if (retval != ERROR_OK)
488 LOG_DEBUG("Vcc opt: %x.%x, Vpp opt: %u.%x",
489 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
490 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
492 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0xe, &pri_ext->num_protection_fields);
493 if (retval != ERROR_OK)
495 if (pri_ext->num_protection_fields != 1)
497 LOG_WARNING("expected one protection register field, but found %i",
498 pri_ext->num_protection_fields);
501 retval = cfi_query_u16(bank, 0, cfi_info->pri_addr + 0xf, &pri_ext->prot_reg_addr);
502 if (retval != ERROR_OK)
504 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x11, &pri_ext->fact_prot_reg_size);
505 if (retval != ERROR_OK)
507 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0x12, &pri_ext->user_prot_reg_size);
508 if (retval != ERROR_OK)
511 LOG_DEBUG("protection_fields: %i, prot_reg_addr: 0x%x, "
512 "factory pre-programmed: %i, user programmable: %i",
513 pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
514 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
519 static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
522 struct cfi_flash_bank *cfi_info = bank->driver_priv;
523 struct cfi_spansion_pri_ext *pri_ext;
525 if (cfi_info->pri_ext)
526 free(cfi_info->pri_ext);
528 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
531 LOG_ERROR("Out of memory");
534 cfi_info->pri_ext = pri_ext;
536 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &pri_ext->pri[0]);
537 if (retval != ERROR_OK)
539 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &pri_ext->pri[1]);
540 if (retval != ERROR_OK)
542 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &pri_ext->pri[2]);
543 if (retval != ERROR_OK)
546 if ((pri_ext->pri[0] != 'P') || (pri_ext->pri[1] != 'R') || (pri_ext->pri[2] != 'I'))
548 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
552 LOG_ERROR("Could not read spansion bank information");
553 return ERROR_FLASH_BANK_INVALID;
556 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &pri_ext->major_version);
557 if (retval != ERROR_OK)
559 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &pri_ext->minor_version);
560 if (retval != ERROR_OK)
563 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", pri_ext->pri[0], pri_ext->pri[1],
564 pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
566 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &pri_ext->SiliconRevision);
567 if (retval != ERROR_OK)
569 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &pri_ext->EraseSuspend);
570 if (retval != ERROR_OK)
572 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &pri_ext->BlkProt);
573 if (retval != ERROR_OK)
575 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &pri_ext->TmpBlkUnprotect);
576 if (retval != ERROR_OK)
578 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 9, &pri_ext->BlkProtUnprot);
579 if (retval != ERROR_OK)
581 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 10, &pri_ext->SimultaneousOps);
582 if (retval != ERROR_OK)
584 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 11, &pri_ext->BurstMode);
585 if (retval != ERROR_OK)
587 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 12, &pri_ext->PageMode);
588 if (retval != ERROR_OK)
590 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 13, &pri_ext->VppMin);
591 if (retval != ERROR_OK)
593 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 14, &pri_ext->VppMax);
594 if (retval != ERROR_OK)
596 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 15, &pri_ext->TopBottom);
597 if (retval != ERROR_OK)
600 LOG_DEBUG("Silicon Revision: 0x%x, Erase Suspend: 0x%x, Block protect: 0x%x",
601 pri_ext->SiliconRevision, pri_ext->EraseSuspend, pri_ext->BlkProt);
603 LOG_DEBUG("Temporary Unprotect: 0x%x, Block Protect Scheme: 0x%x, "
604 "Simultaneous Ops: 0x%x", pri_ext->TmpBlkUnprotect,
605 pri_ext->BlkProtUnprot, pri_ext->SimultaneousOps);
607 LOG_DEBUG("Burst Mode: 0x%x, Page Mode: 0x%x, ", pri_ext->BurstMode, pri_ext->PageMode);
610 LOG_DEBUG("Vpp min: %u.%x, Vpp max: %u.%x",
611 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
612 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
614 LOG_DEBUG("WP# protection 0x%x", pri_ext->TopBottom);
616 /* default values for implementation specific workarounds */
617 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
618 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
619 pri_ext->_reversed_geometry = 0;
624 static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
627 struct cfi_atmel_pri_ext atmel_pri_ext;
628 struct cfi_flash_bank *cfi_info = bank->driver_priv;
629 struct cfi_spansion_pri_ext *pri_ext;
631 if (cfi_info->pri_ext)
632 free(cfi_info->pri_ext);
634 pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
637 LOG_ERROR("Out of memory");
641 /* ATMEL devices use the same CFI primary command set (0x2) as AMD/Spansion,
642 * but a different primary extended query table.
643 * We read the atmel table, and prepare a valid AMD/Spansion query table.
646 memset(pri_ext, 0, sizeof(struct cfi_spansion_pri_ext));
648 cfi_info->pri_ext = pri_ext;
650 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 0, &atmel_pri_ext.pri[0]);
651 if (retval != ERROR_OK)
653 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 1, &atmel_pri_ext.pri[1]);
654 if (retval != ERROR_OK)
656 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 2, &atmel_pri_ext.pri[2]);
657 if (retval != ERROR_OK)
660 if ((atmel_pri_ext.pri[0] != 'P') || (atmel_pri_ext.pri[1] != 'R')
661 || (atmel_pri_ext.pri[2] != 'I'))
663 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
667 LOG_ERROR("Could not read atmel bank information");
668 return ERROR_FLASH_BANK_INVALID;
671 pri_ext->pri[0] = atmel_pri_ext.pri[0];
672 pri_ext->pri[1] = atmel_pri_ext.pri[1];
673 pri_ext->pri[2] = atmel_pri_ext.pri[2];
675 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 3, &atmel_pri_ext.major_version);
676 if (retval != ERROR_OK)
678 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 4, &atmel_pri_ext.minor_version);
679 if (retval != ERROR_OK)
682 LOG_DEBUG("pri: '%c%c%c', version: %c.%c", atmel_pri_ext.pri[0],
683 atmel_pri_ext.pri[1], atmel_pri_ext.pri[2],
684 atmel_pri_ext.major_version, atmel_pri_ext.minor_version);
686 pri_ext->major_version = atmel_pri_ext.major_version;
687 pri_ext->minor_version = atmel_pri_ext.minor_version;
689 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 5, &atmel_pri_ext.features);
690 if (retval != ERROR_OK)
692 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 6, &atmel_pri_ext.bottom_boot);
693 if (retval != ERROR_OK)
695 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 7, &atmel_pri_ext.burst_mode);
696 if (retval != ERROR_OK)
698 retval = cfi_query_u8(bank, 0, cfi_info->pri_addr + 8, &atmel_pri_ext.page_mode);
699 if (retval != ERROR_OK)
702 LOG_DEBUG("features: 0x%2.2x, bottom_boot: 0x%2.2x, burst_mode: 0x%2.2x, page_mode: 0x%2.2x",
703 atmel_pri_ext.features, atmel_pri_ext.bottom_boot,
704 atmel_pri_ext.burst_mode, atmel_pri_ext.page_mode);
706 if (atmel_pri_ext.features & 0x02)
707 pri_ext->EraseSuspend = 2;
709 if (atmel_pri_ext.bottom_boot)
710 pri_ext->TopBottom = 2;
712 pri_ext->TopBottom = 3;
714 pri_ext->_unlock1 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock1;
715 pri_ext->_unlock2 = cfi_unlock_addresses[CFI_UNLOCK_555_2AA].unlock2;
720 static int cfi_read_0002_pri_ext(struct flash_bank *bank)
722 struct cfi_flash_bank *cfi_info = bank->driver_priv;
724 if (cfi_info->manufacturer == CFI_MFR_ATMEL)
726 return cfi_read_atmel_pri_ext(bank);
730 return cfi_read_spansion_pri_ext(bank);
734 static int cfi_spansion_info(struct flash_bank *bank, char *buf, int buf_size)
737 struct cfi_flash_bank *cfi_info = bank->driver_priv;
738 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
740 printed = snprintf(buf, buf_size, "\nSpansion primary algorithm extend information:\n");
744 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
745 pri_ext->pri[1], pri_ext->pri[2],
746 pri_ext->major_version, pri_ext->minor_version);
750 printed = snprintf(buf, buf_size, "Silicon Rev.: 0x%x, Address Sensitive unlock: 0x%x\n",
751 (pri_ext->SiliconRevision) >> 2,
752 (pri_ext->SiliconRevision) & 0x03);
756 printed = snprintf(buf, buf_size, "Erase Suspend: 0x%x, Sector Protect: 0x%x\n",
757 pri_ext->EraseSuspend,
762 printed = snprintf(buf, buf_size, "VppMin: %u.%x, VppMax: %u.%x\n",
763 (pri_ext->VppMin & 0xf0) >> 4, pri_ext->VppMin & 0x0f,
764 (pri_ext->VppMax & 0xf0) >> 4, pri_ext->VppMax & 0x0f);
769 static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
772 struct cfi_flash_bank *cfi_info = bank->driver_priv;
773 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
775 printed = snprintf(buf, buf_size, "\nintel primary algorithm extend information:\n");
779 printed = snprintf(buf, buf_size, "pri: '%c%c%c', version: %c.%c\n", pri_ext->pri[0],
780 pri_ext->pri[1], pri_ext->pri[2], pri_ext->major_version, pri_ext->minor_version);
784 printed = snprintf(buf, buf_size, "feature_support: 0x%" PRIx32 ", "
785 "suspend_cmd_support: 0x%x, blk_status_reg_mask: 0x%x\n",
786 pri_ext->feature_support, pri_ext->suspend_cmd_support, pri_ext->blk_status_reg_mask);
790 printed = snprintf(buf, buf_size, "Vcc opt: %x.%x, Vpp opt: %u.%x\n",
791 (pri_ext->vcc_optimal & 0xf0) >> 4, pri_ext->vcc_optimal & 0x0f,
792 (pri_ext->vpp_optimal & 0xf0) >> 4, pri_ext->vpp_optimal & 0x0f);
796 printed = snprintf(buf, buf_size, "protection_fields: %i, prot_reg_addr: 0x%x, "
797 "factory pre-programmed: %i, user programmable: %i\n",
798 pri_ext->num_protection_fields, pri_ext->prot_reg_addr,
799 1 << pri_ext->fact_prot_reg_size, 1 << pri_ext->user_prot_reg_size);
804 /* flash_bank cfi <base> <size> <chip_width> <bus_width> <target#> [options]
806 FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
808 struct cfi_flash_bank *cfi_info;
812 LOG_WARNING("incomplete flash_bank cfi configuration");
813 return ERROR_FLASH_BANK_INVALID;
817 * - not exceed max value;
819 * - be equal to a power of 2.
820 * bus must be wide enought to hold one chip */
821 if ((bank->chip_width > CFI_MAX_CHIP_WIDTH)
822 || (bank->bus_width > CFI_MAX_BUS_WIDTH)
823 || (bank->chip_width == 0)
824 || (bank->bus_width == 0)
825 || (bank->chip_width & (bank->chip_width - 1))
826 || (bank->bus_width & (bank->bus_width - 1))
827 || (bank->chip_width > bank->bus_width))
829 LOG_ERROR("chip and bus width have to specified in bytes");
830 return ERROR_FLASH_BANK_INVALID;
833 cfi_info = malloc(sizeof(struct cfi_flash_bank));
834 cfi_info->probed = 0;
835 cfi_info->erase_region_info = NULL;
836 cfi_info->pri_ext = NULL;
837 bank->driver_priv = cfi_info;
839 cfi_info->write_algorithm = NULL;
841 cfi_info->x16_as_x8 = 0;
842 cfi_info->jedec_probe = 0;
843 cfi_info->not_cfi = 0;
845 for (unsigned i = 6; i < CMD_ARGC; i++)
847 if (strcmp(CMD_ARGV[i], "x16_as_x8") == 0)
849 cfi_info->x16_as_x8 = 1;
851 else if (strcmp(CMD_ARGV[i], "jedec_probe") == 0)
853 cfi_info->jedec_probe = 1;
857 cfi_info->write_algorithm = NULL;
859 /* bank wasn't probed yet */
860 cfi_info->qry[0] = 0xff;
865 static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
868 struct cfi_flash_bank *cfi_info = bank->driver_priv;
871 cfi_intel_clear_status_register(bank);
873 for (i = first; i <= last; i++)
875 if ((retval = cfi_send_command(bank, 0x20, flash_address(bank, i, 0x0))) != ERROR_OK)
880 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
886 retval = cfi_intel_wait_status_busy(bank, cfi_info->block_erase_timeout, &status);
887 if (retval != ERROR_OK)
891 bank->sectors[i].is_erased = 1;
894 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
899 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%" PRIx32 , i, bank->base);
900 return ERROR_FLASH_OPERATION_FAILED;
904 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
907 static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
910 struct cfi_flash_bank *cfi_info = bank->driver_priv;
911 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
914 for (i = first; i <= last; i++)
916 if ((retval = cfi_send_command(bank, 0xaa,
917 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
922 if ((retval = cfi_send_command(bank, 0x55,
923 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
928 if ((retval = cfi_send_command(bank, 0x80,
929 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
934 if ((retval = cfi_send_command(bank, 0xaa,
935 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
940 if ((retval = cfi_send_command(bank, 0x55,
941 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
946 if ((retval = cfi_send_command(bank, 0x30,
947 flash_address(bank, i, 0x0))) != ERROR_OK)
952 if (cfi_spansion_wait_status_busy(bank, cfi_info->block_erase_timeout) == ERROR_OK)
954 bank->sectors[i].is_erased = 1;
958 if ((retval = cfi_send_command(bank, 0xf0,
959 flash_address(bank, 0, 0x0))) != ERROR_OK)
964 LOG_ERROR("couldn't erase block %i of flash bank at base 0x%"
965 PRIx32, i, bank->base);
966 return ERROR_FLASH_OPERATION_FAILED;
970 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
973 static int cfi_erase(struct flash_bank *bank, int first, int last)
975 struct cfi_flash_bank *cfi_info = bank->driver_priv;
977 if (bank->target->state != TARGET_HALTED)
979 LOG_ERROR("Target not halted");
980 return ERROR_TARGET_NOT_HALTED;
983 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
985 return ERROR_FLASH_SECTOR_INVALID;
988 if (cfi_info->qry[0] != 'Q')
989 return ERROR_FLASH_BANK_NOT_PROBED;
991 switch (cfi_info->pri_id)
995 return cfi_intel_erase(bank, first, last);
998 return cfi_spansion_erase(bank, first, last);
1001 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
1008 static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
1011 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1012 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
1016 /* if the device supports neither legacy lock/unlock (bit 3) nor
1017 * instant individual block locking (bit 5).
1019 if (!(pri_ext->feature_support & 0x28))
1021 LOG_ERROR("lock/unlock not supported on flash");
1022 return ERROR_FLASH_OPERATION_FAILED;
1025 cfi_intel_clear_status_register(bank);
1027 for (i = first; i <= last; i++)
1029 if ((retval = cfi_send_command(bank, 0x60, flash_address(bank, i, 0x0))) != ERROR_OK)
1035 if ((retval = cfi_send_command(bank, 0x01, flash_address(bank, i, 0x0))) != ERROR_OK)
1039 bank->sectors[i].is_protected = 1;
1043 if ((retval = cfi_send_command(bank, 0xd0, flash_address(bank, i, 0x0))) != ERROR_OK)
1047 bank->sectors[i].is_protected = 0;
1050 /* instant individual block locking doesn't require reading of the status register */
1051 if (!(pri_ext->feature_support & 0x20))
1053 /* Clear lock bits operation may take up to 1.4s */
1055 retval = cfi_intel_wait_status_busy(bank, 1400, &status);
1056 if (retval != ERROR_OK)
1061 uint8_t block_status;
1062 /* read block lock bit, to verify status */
1063 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
1067 retval = cfi_get_u8(bank, i, 0x2, &block_status);
1068 if (retval != ERROR_OK)
1071 if ((block_status & 0x1) != set)
1073 LOG_ERROR("couldn't change block lock status (set = %i, block_status = 0x%2.2x)",
1075 if ((retval = cfi_send_command(bank, 0x70,
1076 flash_address(bank, 0, 0x55))) != ERROR_OK)
1081 retval = cfi_intel_wait_status_busy(bank, 10, &status);
1082 if (retval != ERROR_OK)
1086 return ERROR_FLASH_OPERATION_FAILED;
1096 /* if the device doesn't support individual block lock bits set/clear,
1097 * all blocks have been unlocked in parallel, so we set those that should be protected
1099 if ((!set) && (!(pri_ext->feature_support & 0x20)))
1101 /* FIX!!! this code path is broken!!!
1103 * The correct approach is:
1105 * 1. read out current protection status
1107 * 2. override read out protection status w/unprotected.
1109 * 3. re-protect what should be protected.
1112 for (i = 0; i < bank->num_sectors; i++)
1114 if (bank->sectors[i].is_protected == 1)
1116 cfi_intel_clear_status_register(bank);
1118 if ((retval = cfi_send_command(bank, 0x60,
1119 flash_address(bank, i, 0x0))) != ERROR_OK)
1124 if ((retval = cfi_send_command(bank, 0x01,
1125 flash_address(bank, i, 0x0))) != ERROR_OK)
1131 retval = cfi_intel_wait_status_busy(bank, 100, &status);
1132 if (retval != ERROR_OK)
1138 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
1141 static int cfi_protect(struct flash_bank *bank, int set, int first, int last)
1143 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1145 if (bank->target->state != TARGET_HALTED)
1147 LOG_ERROR("Target not halted");
1148 return ERROR_TARGET_NOT_HALTED;
1151 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
1153 LOG_ERROR("Invalid sector range");
1154 return ERROR_FLASH_SECTOR_INVALID;
1157 if (cfi_info->qry[0] != 'Q')
1158 return ERROR_FLASH_BANK_NOT_PROBED;
1160 switch (cfi_info->pri_id)
1164 return cfi_intel_protect(bank, set, first, last);
1167 LOG_WARNING("protect: cfi primary command set %i unsupported", cfi_info->pri_id);
1172 /* Convert code image to target endian */
1173 /* FIXME create general block conversion fcts in target.c?) */
1174 static void cfi_fix_code_endian(struct target *target, uint8_t *dest,
1175 const uint32_t *src, uint32_t count)
1178 for (i = 0; i< count; i++)
1180 target_buffer_set_u32(target, dest, *src);
1186 static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
1188 struct target *target = bank->target;
1190 uint8_t buf[CFI_MAX_BUS_WIDTH];
1191 cfi_command(bank, cmd, buf);
1192 switch (bank->bus_width)
1198 return target_buffer_get_u16(target, buf);
1201 return target_buffer_get_u32(target, buf);
1204 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1209 static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
1210 uint32_t address, uint32_t count)
1212 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1213 struct target *target = bank->target;
1214 struct reg_param reg_params[7];
1215 struct arm_algorithm armv4_5_info;
1216 struct working_area *source;
1217 uint32_t buffer_size = 32768;
1218 uint32_t write_command_val, busy_pattern_val, error_pattern_val;
1220 /* algorithm register usage:
1221 * r0: source address (in RAM)
1222 * r1: target address (in Flash)
1224 * r3: flash write command
1225 * r4: status byte (returned to host)
1226 * r5: busy test pattern
1227 * r6: error test pattern
1230 /* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
1231 static const uint32_t word_32_code[] = {
1232 0xe4904004, /* loop: ldr r4, [r0], #4 */
1233 0xe5813000, /* str r3, [r1] */
1234 0xe5814000, /* str r4, [r1] */
1235 0xe5914000, /* busy: ldr r4, [r1] */
1236 0xe0047005, /* and r7, r4, r5 */
1237 0xe1570005, /* cmp r7, r5 */
1238 0x1afffffb, /* bne busy */
1239 0xe1140006, /* tst r4, r6 */
1240 0x1a000003, /* bne done */
1241 0xe2522001, /* subs r2, r2, #1 */
1242 0x0a000001, /* beq done */
1243 0xe2811004, /* add r1, r1 #4 */
1244 0xeafffff2, /* b loop */
1245 0xeafffffe /* done: b -2 */
1248 /* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
1249 static const uint32_t word_16_code[] = {
1250 0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
1251 0xe1c130b0, /* strh r3, [r1] */
1252 0xe1c140b0, /* strh r4, [r1] */
1253 0xe1d140b0, /* busy ldrh r4, [r1] */
1254 0xe0047005, /* and r7, r4, r5 */
1255 0xe1570005, /* cmp r7, r5 */
1256 0x1afffffb, /* bne busy */
1257 0xe1140006, /* tst r4, r6 */
1258 0x1a000003, /* bne done */
1259 0xe2522001, /* subs r2, r2, #1 */
1260 0x0a000001, /* beq done */
1261 0xe2811002, /* add r1, r1 #2 */
1262 0xeafffff2, /* b loop */
1263 0xeafffffe /* done: b -2 */
1266 /* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
1267 static const uint32_t word_8_code[] = {
1268 0xe4d04001, /* loop: ldrb r4, [r0], #1 */
1269 0xe5c13000, /* strb r3, [r1] */
1270 0xe5c14000, /* strb r4, [r1] */
1271 0xe5d14000, /* busy ldrb r4, [r1] */
1272 0xe0047005, /* and r7, r4, r5 */
1273 0xe1570005, /* cmp r7, r5 */
1274 0x1afffffb, /* bne busy */
1275 0xe1140006, /* tst r4, r6 */
1276 0x1a000003, /* bne done */
1277 0xe2522001, /* subs r2, r2, #1 */
1278 0x0a000001, /* beq done */
1279 0xe2811001, /* add r1, r1 #1 */
1280 0xeafffff2, /* b loop */
1281 0xeafffffe /* done: b -2 */
1283 uint8_t target_code[4*CFI_MAX_INTEL_CODESIZE];
1284 const uint32_t *target_code_src;
1285 uint32_t target_code_size;
1286 int retval = ERROR_OK;
1289 cfi_intel_clear_status_register(bank);
1291 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1292 armv4_5_info.core_mode = ARM_MODE_SVC;
1293 armv4_5_info.core_state = ARM_STATE_ARM;
1295 /* If we are setting up the write_algorith, we need target_code_src */
1296 /* if not we only need target_code_size. */
1298 /* However, we don't want to create multiple code paths, so we */
1299 /* do the unecessary evaluation of target_code_src, which the */
1300 /* compiler will probably nicely optimize away if not needed */
1302 /* prepare algorithm code for target endian */
1303 switch (bank->bus_width)
1306 target_code_src = word_8_code;
1307 target_code_size = sizeof(word_8_code);
1310 target_code_src = word_16_code;
1311 target_code_size = sizeof(word_16_code);
1314 target_code_src = word_32_code;
1315 target_code_size = sizeof(word_32_code);
1318 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1319 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1322 /* flash write code */
1323 if (!cfi_info->write_algorithm)
1325 if (target_code_size > sizeof(target_code))
1327 LOG_WARNING("Internal error - target code buffer to small. "
1328 "Increase CFI_MAX_INTEL_CODESIZE and recompile.");
1329 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1331 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1333 /* Get memory for block write handler */
1334 retval = target_alloc_working_area(target, target_code_size, &cfi_info->write_algorithm);
1335 if (retval != ERROR_OK)
1337 LOG_WARNING("No working area available, can't do block memory writes");
1338 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1341 /* write algorithm code to working area */
1342 retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1343 target_code_size, target_code);
1344 if (retval != ERROR_OK)
1346 LOG_ERROR("Unable to write block write code to target");
1351 /* Get a workspace buffer for the data to flash starting with 32k size.
1352 Half size until buffer would be smaller 256 Bytem then fail back */
1353 /* FIXME Why 256 bytes, why not 32 bytes (smallest flash write page */
1354 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1357 if (buffer_size <= 256)
1359 LOG_WARNING("no large enough working area available, can't do block memory writes");
1360 retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1365 /* setup algo registers */
1366 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1367 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1368 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
1369 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
1370 init_reg_param(®_params[4], "r4", 32, PARAM_IN);
1371 init_reg_param(®_params[5], "r5", 32, PARAM_OUT);
1372 init_reg_param(®_params[6], "r6", 32, PARAM_OUT);
1374 /* prepare command and status register patterns */
1375 write_command_val = cfi_command_val(bank, 0x40);
1376 busy_pattern_val = cfi_command_val(bank, 0x80);
1377 error_pattern_val = cfi_command_val(bank, 0x7e);
1379 LOG_DEBUG("Using target buffer at 0x%08" PRIx32 " and of size 0x%04" PRIx32,
1380 source->address, buffer_size);
1382 /* Programming main loop */
1385 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1388 if ((retval = target_write_buffer(target, source->address,
1389 thisrun_count, buffer)) != ERROR_OK)
1394 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1395 buf_set_u32(reg_params[1].value, 0, 32, address);
1396 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1398 buf_set_u32(reg_params[3].value, 0, 32, write_command_val);
1399 buf_set_u32(reg_params[5].value, 0, 32, busy_pattern_val);
1400 buf_set_u32(reg_params[6].value, 0, 32, error_pattern_val);
1402 LOG_DEBUG("Write 0x%04" PRIx32 " bytes to flash at 0x%08" PRIx32 , thisrun_count, address);
1404 /* Execute algorithm, assume breakpoint for last instruction */
1405 retval = target_run_algorithm(target, 0, NULL, 7, reg_params,
1406 cfi_info->write_algorithm->address,
1407 cfi_info->write_algorithm->address + target_code_size - sizeof(uint32_t),
1408 10000, /* 10s should be enough for max. 32k of data */
1411 /* On failure try a fall back to direct word writes */
1412 if (retval != ERROR_OK)
1414 cfi_intel_clear_status_register(bank);
1415 LOG_ERROR("Execution of flash algorythm failed. Can't fall back. Please report.");
1416 retval = ERROR_FLASH_OPERATION_FAILED;
1417 /* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
1418 /* FIXME To allow fall back or recovery, we must save the actual status
1419 * somewhere, so that a higher level code can start recovery. */
1423 /* Check return value from algo code */
1424 wsm_error = buf_get_u32(reg_params[4].value, 0, 32) & error_pattern_val;
1427 /* read status register (outputs debug inforation) */
1429 cfi_intel_wait_status_busy(bank, 100, &status);
1430 cfi_intel_clear_status_register(bank);
1431 retval = ERROR_FLASH_OPERATION_FAILED;
1435 buffer += thisrun_count;
1436 address += thisrun_count;
1437 count -= thisrun_count;
1442 /* free up resources */
1445 target_free_working_area(target, source);
1447 if (cfi_info->write_algorithm)
1449 target_free_working_area(target, cfi_info->write_algorithm);
1450 cfi_info->write_algorithm = NULL;
1453 destroy_reg_param(®_params[0]);
1454 destroy_reg_param(®_params[1]);
1455 destroy_reg_param(®_params[2]);
1456 destroy_reg_param(®_params[3]);
1457 destroy_reg_param(®_params[4]);
1458 destroy_reg_param(®_params[5]);
1459 destroy_reg_param(®_params[6]);
1464 static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
1465 uint32_t address, uint32_t count)
1467 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1468 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1469 struct target *target = bank->target;
1470 struct reg_param reg_params[10];
1471 struct arm_algorithm armv4_5_info;
1472 struct working_area *source;
1473 uint32_t buffer_size = 32768;
1475 int retval = ERROR_OK;
1477 /* input parameters - */
1478 /* R0 = source address */
1479 /* R1 = destination address */
1480 /* R2 = number of writes */
1481 /* R3 = flash write command */
1482 /* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
1483 /* output parameters - */
1484 /* R5 = 0x80 ok 0x00 bad */
1485 /* temp registers - */
1486 /* R6 = value read from flash to test status */
1487 /* R7 = holding register */
1488 /* unlock registers - */
1489 /* R8 = unlock1_addr */
1490 /* R9 = unlock1_cmd */
1491 /* R10 = unlock2_addr */
1492 /* R11 = unlock2_cmd */
1494 /* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
1495 static const uint32_t armv4_5_word_32_code[] = {
1496 /* 00008100 <sp_32_code>: */
1497 0xe4905004, /* ldr r5, [r0], #4 */
1498 0xe5889000, /* str r9, [r8] */
1499 0xe58ab000, /* str r11, [r10] */
1500 0xe5883000, /* str r3, [r8] */
1501 0xe5815000, /* str r5, [r1] */
1502 0xe1a00000, /* nop */
1504 /* 00008110 <sp_32_busy>: */
1505 0xe5916000, /* ldr r6, [r1] */
1506 0xe0257006, /* eor r7, r5, r6 */
1507 0xe0147007, /* ands r7, r4, r7 */
1508 0x0a000007, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1509 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1510 0x0afffff9, /* beq 8110 <sp_32_busy> ; b if DQ5 low */
1511 0xe5916000, /* ldr r6, [r1] */
1512 0xe0257006, /* eor r7, r5, r6 */
1513 0xe0147007, /* ands r7, r4, r7 */
1514 0x0a000001, /* beq 8140 <sp_32_cont> ; b if DQ7 == Data7 */
1515 0xe3a05000, /* mov r5, #0 ; 0x0 - return 0x00, error */
1516 0x1a000004, /* bne 8154 <sp_32_done> */
1518 /* 00008140 <sp_32_cont>: */
1519 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1520 0x03a05080, /* moveq r5, #128 ; 0x80 */
1521 0x0a000001, /* beq 8154 <sp_32_done> */
1522 0xe2811004, /* add r1, r1, #4 ; 0x4 */
1523 0xeaffffe8, /* b 8100 <sp_32_code> */
1525 /* 00008154 <sp_32_done>: */
1526 0xeafffffe /* b 8154 <sp_32_done> */
1529 /* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
1530 static const uint32_t armv4_5_word_16_code[] = {
1531 /* 00008158 <sp_16_code>: */
1532 0xe0d050b2, /* ldrh r5, [r0], #2 */
1533 0xe1c890b0, /* strh r9, [r8] */
1534 0xe1cab0b0, /* strh r11, [r10] */
1535 0xe1c830b0, /* strh r3, [r8] */
1536 0xe1c150b0, /* strh r5, [r1] */
1537 0xe1a00000, /* nop (mov r0,r0) */
1539 /* 00008168 <sp_16_busy>: */
1540 0xe1d160b0, /* ldrh r6, [r1] */
1541 0xe0257006, /* eor r7, r5, r6 */
1542 0xe0147007, /* ands r7, r4, r7 */
1543 0x0a000007, /* beq 8198 <sp_16_cont> */
1544 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1545 0x0afffff9, /* beq 8168 <sp_16_busy> */
1546 0xe1d160b0, /* ldrh r6, [r1] */
1547 0xe0257006, /* eor r7, r5, r6 */
1548 0xe0147007, /* ands r7, r4, r7 */
1549 0x0a000001, /* beq 8198 <sp_16_cont> */
1550 0xe3a05000, /* mov r5, #0 ; 0x0 */
1551 0x1a000004, /* bne 81ac <sp_16_done> */
1553 /* 00008198 <sp_16_cont>: */
1554 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1555 0x03a05080, /* moveq r5, #128 ; 0x80 */
1556 0x0a000001, /* beq 81ac <sp_16_done> */
1557 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1558 0xeaffffe8, /* b 8158 <sp_16_code> */
1560 /* 000081ac <sp_16_done>: */
1561 0xeafffffe /* b 81ac <sp_16_done> */
1564 /* see contib/loaders/flash/armv7m_cfi_span_16.s for src */
1565 static const uint32_t armv7m_word_16_code[] = {
1586 /* see contib/loaders/flash/armv4_5_cfi_span_16_dq7.s for src */
1587 static const uint32_t armv4_5_word_16_code_dq7only[] = {
1589 0xe0d050b2, /* ldrh r5, [r0], #2 */
1590 0xe1c890b0, /* strh r9, [r8] */
1591 0xe1cab0b0, /* strh r11, [r10] */
1592 0xe1c830b0, /* strh r3, [r8] */
1593 0xe1c150b0, /* strh r5, [r1] */
1594 0xe1a00000, /* nop (mov r0,r0) */
1597 0xe1d160b0, /* ldrh r6, [r1] */
1598 0xe0257006, /* eor r7, r5, r6 */
1599 0xe2177080, /* ands r7, #0x80 */
1600 0x1afffffb, /* bne 8168 <sp_16_busy> */
1602 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1603 0x03a05080, /* moveq r5, #128 ; 0x80 */
1604 0x0a000001, /* beq 81ac <sp_16_done> */
1605 0xe2811002, /* add r1, r1, #2 ; 0x2 */
1606 0xeafffff0, /* b 8158 <sp_16_code> */
1608 /* 000081ac <sp_16_done>: */
1609 0xeafffffe /* b 81ac <sp_16_done> */
1612 /* see contib/loaders/flash/armv4_5_cfi_span_8.s for src */
1613 static const uint32_t armv4_5_word_8_code[] = {
1614 /* 000081b0 <sp_16_code_end>: */
1615 0xe4d05001, /* ldrb r5, [r0], #1 */
1616 0xe5c89000, /* strb r9, [r8] */
1617 0xe5cab000, /* strb r11, [r10] */
1618 0xe5c83000, /* strb r3, [r8] */
1619 0xe5c15000, /* strb r5, [r1] */
1620 0xe1a00000, /* nop (mov r0,r0) */
1622 /* 000081c0 <sp_8_busy>: */
1623 0xe5d16000, /* ldrb r6, [r1] */
1624 0xe0257006, /* eor r7, r5, r6 */
1625 0xe0147007, /* ands r7, r4, r7 */
1626 0x0a000007, /* beq 81f0 <sp_8_cont> */
1627 0xe0166124, /* ands r6, r6, r4, lsr #2 */
1628 0x0afffff9, /* beq 81c0 <sp_8_busy> */
1629 0xe5d16000, /* ldrb r6, [r1] */
1630 0xe0257006, /* eor r7, r5, r6 */
1631 0xe0147007, /* ands r7, r4, r7 */
1632 0x0a000001, /* beq 81f0 <sp_8_cont> */
1633 0xe3a05000, /* mov r5, #0 ; 0x0 */
1634 0x1a000004, /* bne 8204 <sp_8_done> */
1636 /* 000081f0 <sp_8_cont>: */
1637 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
1638 0x03a05080, /* moveq r5, #128 ; 0x80 */
1639 0x0a000001, /* beq 8204 <sp_8_done> */
1640 0xe2811001, /* add r1, r1, #1 ; 0x1 */
1641 0xeaffffe8, /* b 81b0 <sp_16_code_end> */
1643 /* 00008204 <sp_8_done>: */
1644 0xeafffffe /* b 8204 <sp_8_done> */
1647 if(strcmp("cortex_m3", target_type_name(target)) == 0) /* Cortex-M3 target */
1649 armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC;
1650 armv4_5_info.core_mode = ARMV7M_MODE_HANDLER;
1651 armv4_5_info.core_state = ARM_STATE_ARM;
1653 else /* right now is only armv4_5 target */
1655 armv4_5_info.common_magic = ARM_COMMON_MAGIC;
1656 armv4_5_info.core_mode = ARM_MODE_SVC;
1657 armv4_5_info.core_state = ARM_STATE_ARM;
1660 int target_code_size;
1661 const uint32_t *target_code_src;
1663 switch (bank->bus_width)
1666 if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) /* armv4_5 target */
1668 target_code_src = armv4_5_word_8_code;
1669 target_code_size = sizeof(armv4_5_word_8_code);
1673 /* Check for DQ5 support */
1674 if( cfi_info->status_poll_mask & (1 << 5) )
1676 if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) /* armv4_5 target */
1678 target_code_src = armv4_5_word_16_code;
1679 target_code_size = sizeof(armv4_5_word_16_code);
1681 else if (armv4_5_info.common_magic == ARMV7M_COMMON_MAGIC) /* cortex-m3 target */
1683 target_code_src = armv7m_word_16_code;
1684 target_code_size = sizeof(armv7m_word_16_code);
1689 /* No DQ5 support. Use DQ7 DATA# polling only. */
1690 if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target
1692 target_code_src = armv4_5_word_16_code_dq7only;
1693 target_code_size = sizeof(armv4_5_word_16_code_dq7only);
1698 if(armv4_5_info.common_magic == ARM_COMMON_MAGIC) // armv4_5 target
1700 target_code_src = armv4_5_word_32_code;
1701 target_code_size = sizeof(armv4_5_word_32_code);
1705 LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
1706 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1709 /* flash write code */
1710 if (!cfi_info->write_algorithm)
1712 uint8_t *target_code;
1714 /* convert bus-width dependent algorithm code to correct endiannes */
1715 target_code = malloc(target_code_size);
1716 if (target_code == NULL)
1718 LOG_ERROR("Out of memory");
1721 cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
1723 /* allocate working area */
1724 retval = target_alloc_working_area(target, target_code_size,
1725 &cfi_info->write_algorithm);
1726 if (retval != ERROR_OK)
1732 /* write algorithm code to working area */
1733 if ((retval = target_write_buffer(target, cfi_info->write_algorithm->address,
1734 target_code_size, target_code)) != ERROR_OK)
1742 /* the following code still assumes target code is fixed 24*4 bytes */
1744 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK)
1747 if (buffer_size <= 256)
1749 /* if we already allocated the writing code, but failed to get a
1750 * buffer, free the algorithm */
1751 if (cfi_info->write_algorithm)
1752 target_free_working_area(target, cfi_info->write_algorithm);
1754 LOG_WARNING("not enough working area available, can't do block memory writes");
1755 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
1759 init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
1760 init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
1761 init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
1762 init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
1763 init_reg_param(®_params[4], "r4", 32, PARAM_OUT);
1764 init_reg_param(®_params[5], "r5", 32, PARAM_IN);
1765 init_reg_param(®_params[6], "r8", 32, PARAM_OUT);
1766 init_reg_param(®_params[7], "r9", 32, PARAM_OUT);
1767 init_reg_param(®_params[8], "r10", 32, PARAM_OUT);
1768 init_reg_param(®_params[9], "r11", 32, PARAM_OUT);
1772 uint32_t thisrun_count = (count > buffer_size) ? buffer_size : count;
1774 retval = target_write_buffer(target, source->address, thisrun_count, buffer);
1775 if (retval != ERROR_OK)
1780 buf_set_u32(reg_params[0].value, 0, 32, source->address);
1781 buf_set_u32(reg_params[1].value, 0, 32, address);
1782 buf_set_u32(reg_params[2].value, 0, 32, thisrun_count / bank->bus_width);
1783 buf_set_u32(reg_params[3].value, 0, 32, cfi_command_val(bank, 0xA0));
1784 buf_set_u32(reg_params[4].value, 0, 32, cfi_command_val(bank, 0x80));
1785 buf_set_u32(reg_params[6].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock1));
1786 buf_set_u32(reg_params[7].value, 0, 32, 0xaaaaaaaa);
1787 buf_set_u32(reg_params[8].value, 0, 32, flash_address(bank, 0, pri_ext->_unlock2));
1788 buf_set_u32(reg_params[9].value, 0, 32, 0x55555555);
1790 retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
1791 cfi_info->write_algorithm->address,
1792 cfi_info->write_algorithm->address + ((target_code_size) - 4),
1793 10000, &armv4_5_info);
1794 if (retval != ERROR_OK)
1799 status = buf_get_u32(reg_params[5].value, 0, 32);
1802 LOG_ERROR("flash write block failed status: 0x%" PRIx32 , status);
1803 retval = ERROR_FLASH_OPERATION_FAILED;
1807 buffer += thisrun_count;
1808 address += thisrun_count;
1809 count -= thisrun_count;
1812 target_free_all_working_areas(target);
1814 destroy_reg_param(®_params[0]);
1815 destroy_reg_param(®_params[1]);
1816 destroy_reg_param(®_params[2]);
1817 destroy_reg_param(®_params[3]);
1818 destroy_reg_param(®_params[4]);
1819 destroy_reg_param(®_params[5]);
1820 destroy_reg_param(®_params[6]);
1821 destroy_reg_param(®_params[7]);
1822 destroy_reg_param(®_params[8]);
1823 destroy_reg_param(®_params[9]);
1828 static int cfi_intel_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1831 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1832 struct target *target = bank->target;
1834 cfi_intel_clear_status_register(bank);
1835 if ((retval = cfi_send_command(bank, 0x40, address)) != ERROR_OK)
1840 if ((retval = target_write_memory(target, address, bank->bus_width, 1, word)) != ERROR_OK)
1846 retval = cfi_intel_wait_status_busy(bank, cfi_info->word_write_timeout, &status);
1849 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1854 LOG_ERROR("couldn't write word at base 0x%" PRIx32 ", address 0x%" PRIx32,
1855 bank->base, address);
1856 return ERROR_FLASH_OPERATION_FAILED;
1862 static int cfi_intel_write_words(struct flash_bank *bank, uint8_t *word,
1863 uint32_t wordcount, uint32_t address)
1866 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1867 struct target *target = bank->target;
1869 /* Calculate buffer size and boundary mask */
1870 /* buffersize is (buffer size per chip) * (number of chips) */
1871 /* bufferwsize is buffersize in words */
1872 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
1873 uint32_t buffermask = buffersize-1;
1874 uint32_t bufferwsize = buffersize / bank->bus_width;
1876 /* Check for valid range */
1877 if (address & buffermask)
1879 LOG_ERROR("Write address at base 0x%" PRIx32 ", address 0x%" PRIx32
1880 " not aligned to 2^%d boundary",
1881 bank->base, address, cfi_info->max_buf_write_size);
1882 return ERROR_FLASH_OPERATION_FAILED;
1885 /* Check for valid size */
1886 if (wordcount > bufferwsize)
1888 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %" PRId32,
1889 wordcount, buffersize);
1890 return ERROR_FLASH_OPERATION_FAILED;
1893 /* Write to flash buffer */
1894 cfi_intel_clear_status_register(bank);
1896 /* Initiate buffer operation _*/
1897 if ((retval = cfi_send_command(bank, 0xe8, address)) != ERROR_OK)
1902 retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
1903 if (retval != ERROR_OK)
1907 if ((retval = cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0))) != ERROR_OK)
1912 LOG_ERROR("couldn't start buffer write operation at base 0x%" PRIx32 ", address 0x%" PRIx32,
1913 bank->base, address);
1914 return ERROR_FLASH_OPERATION_FAILED;
1917 /* Write buffer wordcount-1 and data words */
1918 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
1923 if ((retval = target_write_memory(target,
1924 address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
1929 /* Commit write operation */
1930 if ((retval = cfi_send_command(bank, 0xd0, address)) != ERROR_OK)
1935 retval = cfi_intel_wait_status_busy(bank, cfi_info->buf_write_timeout, &status);
1936 if (retval != ERROR_OK)
1941 if ((retval = cfi_send_command(bank, 0xff,
1942 flash_address(bank, 0, 0x0))) != ERROR_OK)
1947 LOG_ERROR("Buffer write at base 0x%" PRIx32
1948 ", address 0x%" PRIx32 " failed.", bank->base, address);
1949 return ERROR_FLASH_OPERATION_FAILED;
1955 static int cfi_spansion_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
1958 struct cfi_flash_bank *cfi_info = bank->driver_priv;
1959 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
1960 struct target *target = bank->target;
1962 if ((retval = cfi_send_command(bank, 0xaa,
1963 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1968 if ((retval = cfi_send_command(bank, 0x55,
1969 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
1974 if ((retval = cfi_send_command(bank, 0xa0,
1975 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
1980 if ((retval = target_write_memory(target,
1981 address, bank->bus_width, 1, word)) != ERROR_OK)
1986 if (cfi_spansion_wait_status_busy(bank, cfi_info->word_write_timeout) != ERROR_OK)
1988 if ((retval = cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0))) != ERROR_OK)
1993 LOG_ERROR("couldn't write word at base 0x%" PRIx32
1994 ", address 0x%" PRIx32 , bank->base, address);
1995 return ERROR_FLASH_OPERATION_FAILED;
2001 static int cfi_spansion_write_words(struct flash_bank *bank, uint8_t *word,
2002 uint32_t wordcount, uint32_t address)
2005 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2006 struct target *target = bank->target;
2007 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2009 /* Calculate buffer size and boundary mask */
2010 /* buffersize is (buffer size per chip) * (number of chips) */
2011 /* bufferwsize is buffersize in words */
2012 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2013 uint32_t buffermask = buffersize-1;
2014 uint32_t bufferwsize = buffersize / bank->bus_width;
2016 /* Check for valid range */
2017 if (address & buffermask)
2019 LOG_ERROR("Write address at base 0x%" PRIx32
2020 ", address 0x%" PRIx32 " not aligned to 2^%d boundary",
2021 bank->base, address, cfi_info->max_buf_write_size);
2022 return ERROR_FLASH_OPERATION_FAILED;
2025 /* Check for valid size */
2026 if (wordcount > bufferwsize)
2028 LOG_ERROR("Number of data words %" PRId32 " exceeds available buffersize %"
2029 PRId32, wordcount, buffersize);
2030 return ERROR_FLASH_OPERATION_FAILED;
2034 if ((retval = cfi_send_command(bank, 0xaa,
2035 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2040 if ((retval = cfi_send_command(bank, 0x55,
2041 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2046 /* Buffer load command */
2047 if ((retval = cfi_send_command(bank, 0x25, address)) != ERROR_OK)
2052 /* Write buffer wordcount-1 and data words */
2053 if ((retval = cfi_send_command(bank, bufferwsize-1, address)) != ERROR_OK)
2058 if ((retval = target_write_memory(target,
2059 address, bank->bus_width, bufferwsize, word)) != ERROR_OK)
2064 /* Commit write operation */
2065 if ((retval = cfi_send_command(bank, 0x29, address)) != ERROR_OK)
2070 if (cfi_spansion_wait_status_busy(bank, cfi_info->buf_write_timeout) != ERROR_OK)
2072 if ((retval = cfi_send_command(bank, 0xf0,
2073 flash_address(bank, 0, 0x0))) != ERROR_OK)
2078 LOG_ERROR("couldn't write block at base 0x%" PRIx32
2079 ", address 0x%" PRIx32 ", size 0x%" PRIx32, bank->base, address, bufferwsize);
2080 return ERROR_FLASH_OPERATION_FAILED;
2086 static int cfi_write_word(struct flash_bank *bank, uint8_t *word, uint32_t address)
2088 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2090 switch (cfi_info->pri_id)
2094 return cfi_intel_write_word(bank, word, address);
2097 return cfi_spansion_write_word(bank, word, address);
2100 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2104 return ERROR_FLASH_OPERATION_FAILED;
2107 static int cfi_write_words(struct flash_bank *bank, uint8_t *word,
2108 uint32_t wordcount, uint32_t address)
2110 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2112 if (cfi_info->buf_write_timeout_typ == 0)
2114 /* buffer writes are not supported */
2115 LOG_DEBUG("Buffer Writes Not Supported");
2116 return ERROR_FLASH_OPER_UNSUPPORTED;
2119 switch (cfi_info->pri_id)
2123 return cfi_intel_write_words(bank, word, wordcount, address);
2126 return cfi_spansion_write_words(bank, word, wordcount, address);
2129 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2133 return ERROR_FLASH_OPERATION_FAILED;
2136 static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2138 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2139 struct target *target = bank->target;
2140 uint32_t address = bank->base + offset;
2142 int align; /* number of unaligned bytes */
2143 uint8_t current_word[CFI_MAX_BUS_WIDTH];
2147 LOG_DEBUG("reading buffer of %i byte at 0x%8.8x",
2148 (int)count, (unsigned)offset);
2150 if (bank->target->state != TARGET_HALTED)
2152 LOG_ERROR("Target not halted");
2153 return ERROR_TARGET_NOT_HALTED;
2156 if (offset + count > bank->size)
2157 return ERROR_FLASH_DST_OUT_OF_BANK;
2159 if (cfi_info->qry[0] != 'Q')
2160 return ERROR_FLASH_BANK_NOT_PROBED;
2162 /* start at the first byte of the first word (bus_width size) */
2163 read_p = address & ~(bank->bus_width - 1);
2164 if ((align = address - read_p) != 0)
2166 LOG_INFO("Fixup %d unaligned read head bytes", align);
2168 /* read a complete word from flash */
2169 if ((retval = target_read_memory(target, read_p,
2170 bank->bus_width, 1, current_word)) != ERROR_OK)
2173 /* take only bytes we need */
2174 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2175 *buffer++ = current_word[i];
2177 read_p += bank->bus_width;
2180 align = count / bank->bus_width;
2183 if ((retval = target_read_memory(target, read_p,
2184 bank->bus_width, align, buffer)) != ERROR_OK)
2187 read_p += align * bank->bus_width;
2188 buffer += align * bank->bus_width;
2189 count -= align * bank->bus_width;
2194 LOG_INFO("Fixup %d unaligned read tail bytes", count);
2196 /* read a complete word from flash */
2197 if ((retval = target_read_memory(target, read_p,
2198 bank->bus_width, 1, current_word)) != ERROR_OK)
2201 /* take only bytes we need */
2202 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2203 *buffer++ = current_word[i];
2209 static int cfi_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
2211 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2212 struct target *target = bank->target;
2213 uint32_t address = bank->base + offset; /* address of first byte to be programmed */
2215 int align; /* number of unaligned bytes */
2216 int blk_count; /* number of bus_width bytes for block copy */
2217 uint8_t current_word[CFI_MAX_BUS_WIDTH * 4]; /* word (bus_width size) currently being programmed */
2221 if (bank->target->state != TARGET_HALTED)
2223 LOG_ERROR("Target not halted");
2224 return ERROR_TARGET_NOT_HALTED;
2227 if (offset + count > bank->size)
2228 return ERROR_FLASH_DST_OUT_OF_BANK;
2230 if (cfi_info->qry[0] != 'Q')
2231 return ERROR_FLASH_BANK_NOT_PROBED;
2233 /* start at the first byte of the first word (bus_width size) */
2234 write_p = address & ~(bank->bus_width - 1);
2235 if ((align = address - write_p) != 0)
2237 LOG_INFO("Fixup %d unaligned head bytes", align);
2239 /* read a complete word from flash */
2240 if ((retval = target_read_memory(target, write_p,
2241 bank->bus_width, 1, current_word)) != ERROR_OK)
2244 /* replace only bytes that must be written */
2245 for (i = align; (i < bank->bus_width) && (count > 0); i++, count--)
2246 current_word[i] = *buffer++;
2248 retval = cfi_write_word(bank, current_word, write_p);
2249 if (retval != ERROR_OK)
2251 write_p += bank->bus_width;
2254 /* handle blocks of bus_size aligned bytes */
2255 blk_count = count & ~(bank->bus_width - 1); /* round down, leave tail bytes */
2256 switch (cfi_info->pri_id)
2258 /* try block writes (fails without working area) */
2261 retval = cfi_intel_write_block(bank, buffer, write_p, blk_count);
2264 retval = cfi_spansion_write_block(bank, buffer, write_p, blk_count);
2267 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2268 retval = ERROR_FLASH_OPERATION_FAILED;
2271 if (retval == ERROR_OK)
2273 /* Increment pointers and decrease count on succesful block write */
2274 buffer += blk_count;
2275 write_p += blk_count;
2280 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
2282 /* Calculate buffer size and boundary mask */
2283 /* buffersize is (buffer size per chip) * (number of chips) */
2284 /* bufferwsize is buffersize in words */
2285 uint32_t buffersize = (1UL << cfi_info->max_buf_write_size) * (bank->bus_width / bank->chip_width);
2286 uint32_t buffermask = buffersize-1;
2287 uint32_t bufferwsize = buffersize / bank->bus_width;
2289 /* fall back to memory writes */
2290 while (count >= (uint32_t)bank->bus_width)
2293 if ((write_p & 0xff) == 0)
2295 LOG_INFO("Programming at 0x%08" PRIx32 ", count 0x%08"
2296 PRIx32 " bytes remaining", write_p, count);
2299 if ((bufferwsize > 0) && (count >= buffersize) && !(write_p & buffermask))
2301 retval = cfi_write_words(bank, buffer, bufferwsize, write_p);
2302 if (retval == ERROR_OK)
2304 buffer += buffersize;
2305 write_p += buffersize;
2306 count -= buffersize;
2309 else if (retval != ERROR_FLASH_OPER_UNSUPPORTED)
2312 /* try the slow way? */
2315 for (i = 0; i < bank->bus_width; i++)
2316 current_word[i] = *buffer++;
2318 retval = cfi_write_word(bank, current_word, write_p);
2319 if (retval != ERROR_OK)
2322 write_p += bank->bus_width;
2323 count -= bank->bus_width;
2331 /* return to read array mode, so we can read from flash again for padding */
2332 if ((retval = cfi_reset(bank)) != ERROR_OK)
2337 /* handle unaligned tail bytes */
2340 LOG_INFO("Fixup %" PRId32 " unaligned tail bytes", count);
2342 /* read a complete word from flash */
2343 if ((retval = target_read_memory(target, write_p,
2344 bank->bus_width, 1, current_word)) != ERROR_OK)
2347 /* replace only bytes that must be written */
2348 for (i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
2349 current_word[i] = *buffer++;
2351 retval = cfi_write_word(bank, current_word, write_p);
2352 if (retval != ERROR_OK)
2356 /* return to read array mode */
2357 return cfi_reset(bank);
2360 static void cfi_fixup_reversed_erase_regions(struct flash_bank *bank, void *param)
2363 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2364 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2366 pri_ext->_reversed_geometry = 1;
2369 static void cfi_fixup_0002_erase_regions(struct flash_bank *bank, void *param)
2372 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2373 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2376 if ((pri_ext->_reversed_geometry) || (pri_ext->TopBottom == 3))
2378 LOG_DEBUG("swapping reversed erase region information on cmdset 0002 device");
2380 for (i = 0; i < cfi_info->num_erase_regions / 2; i++)
2382 int j = (cfi_info->num_erase_regions - 1) - i;
2385 swap = cfi_info->erase_region_info[i];
2386 cfi_info->erase_region_info[i] = cfi_info->erase_region_info[j];
2387 cfi_info->erase_region_info[j] = swap;
2392 static void cfi_fixup_0002_unlock_addresses(struct flash_bank *bank, void *param)
2394 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2395 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2396 struct cfi_unlock_addresses *unlock_addresses = param;
2398 pri_ext->_unlock1 = unlock_addresses->unlock1;
2399 pri_ext->_unlock2 = unlock_addresses->unlock2;
2403 static int cfi_query_string(struct flash_bank *bank, int address)
2405 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2408 if ((retval = cfi_send_command(bank, 0x98, flash_address(bank, 0, address))) != ERROR_OK)
2413 retval = cfi_query_u8(bank, 0, 0x10, &cfi_info->qry[0]);
2414 if (retval != ERROR_OK)
2416 retval = cfi_query_u8(bank, 0, 0x11, &cfi_info->qry[1]);
2417 if (retval != ERROR_OK)
2419 retval = cfi_query_u8(bank, 0, 0x12, &cfi_info->qry[2]);
2420 if (retval != ERROR_OK)
2423 LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x",
2424 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
2426 if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
2428 if ((retval = cfi_reset(bank)) != ERROR_OK)
2432 LOG_ERROR("Could not probe bank: no QRY");
2433 return ERROR_FLASH_BANK_INVALID;
2439 static int cfi_probe(struct flash_bank *bank)
2441 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2442 struct target *target = bank->target;
2443 int num_sectors = 0;
2446 uint32_t unlock1 = 0x555;
2447 uint32_t unlock2 = 0x2aa;
2449 uint8_t value_buf0[CFI_MAX_BUS_WIDTH], value_buf1[CFI_MAX_BUS_WIDTH];
2451 if (bank->target->state != TARGET_HALTED)
2453 LOG_ERROR("Target not halted");
2454 return ERROR_TARGET_NOT_HALTED;
2457 cfi_info->probed = 0;
2460 free(bank->sectors);
2461 bank->sectors = NULL;
2463 if(cfi_info->erase_region_info)
2465 free(cfi_info->erase_region_info);
2466 cfi_info->erase_region_info = NULL;
2469 /* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
2470 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
2472 if (cfi_info->jedec_probe)
2478 /* switch to read identifier codes mode ("AUTOSELECT") */
2479 if ((retval = cfi_send_command(bank, 0xaa, flash_address(bank, 0, unlock1))) != ERROR_OK)
2483 if ((retval = cfi_send_command(bank, 0x55, flash_address(bank, 0, unlock2))) != ERROR_OK)
2487 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, unlock1))) != ERROR_OK)
2492 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x00),
2493 bank->bus_width, 1, value_buf0)) != ERROR_OK)
2497 if ((retval = target_read_memory(target, flash_address(bank, 0, 0x01),
2498 bank->bus_width, 1, value_buf1)) != ERROR_OK)
2502 switch (bank->chip_width) {
2504 cfi_info->manufacturer = *value_buf0;
2505 cfi_info->device_id = *value_buf1;
2508 cfi_info->manufacturer = target_buffer_get_u16(target, value_buf0);
2509 cfi_info->device_id = target_buffer_get_u16(target, value_buf1);
2512 cfi_info->manufacturer = target_buffer_get_u32(target, value_buf0);
2513 cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
2516 LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory", bank->chip_width);
2517 return ERROR_FLASH_OPERATION_FAILED;
2520 LOG_INFO("Flash Manufacturer/Device: 0x%04x 0x%04x",
2521 cfi_info->manufacturer, cfi_info->device_id);
2522 /* switch back to read array mode */
2523 if ((retval = cfi_reset(bank)) != ERROR_OK)
2528 /* check device/manufacturer ID for known non-CFI flashes. */
2529 cfi_fixup_non_cfi(bank);
2531 /* query only if this is a CFI compatible flash,
2532 * otherwise the relevant info has already been filled in
2534 if (cfi_info->not_cfi == 0)
2536 /* enter CFI query mode
2537 * according to JEDEC Standard No. 68.01,
2538 * a single bus sequence with address = 0x55, data = 0x98 should put
2539 * the device into CFI query mode.
2541 * SST flashes clearly violate this, and we will consider them incompatbile for now
2544 retval = cfi_query_string(bank, 0x55);
2545 if (retval != ERROR_OK)
2548 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
2549 * be harmless enough:
2551 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
2553 LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
2554 retval = cfi_query_string(bank, 0x555);
2556 if (retval != ERROR_OK)
2559 retval = cfi_query_u16(bank, 0, 0x13, &cfi_info->pri_id);
2560 if (retval != ERROR_OK)
2562 retval = cfi_query_u16(bank, 0, 0x15, &cfi_info->pri_addr);
2563 if (retval != ERROR_OK)
2565 retval = cfi_query_u16(bank, 0, 0x17, &cfi_info->alt_id);
2566 if (retval != ERROR_OK)
2568 retval = cfi_query_u16(bank, 0, 0x19, &cfi_info->alt_addr);
2569 if (retval != ERROR_OK)
2572 LOG_DEBUG("qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: 0x%4.4x, alt_id: "
2573 "0x%4.4x, alt_addr: 0x%4.4x", cfi_info->qry[0], cfi_info->qry[1],
2574 cfi_info->qry[2], cfi_info->pri_id, cfi_info->pri_addr,
2575 cfi_info->alt_id, cfi_info->alt_addr);
2577 retval = cfi_query_u8(bank, 0, 0x1b, &cfi_info->vcc_min);
2578 if (retval != ERROR_OK)
2580 retval = cfi_query_u8(bank, 0, 0x1c, &cfi_info->vcc_max);
2581 if (retval != ERROR_OK)
2583 retval = cfi_query_u8(bank, 0, 0x1d, &cfi_info->vpp_min);
2584 if (retval != ERROR_OK)
2586 retval = cfi_query_u8(bank, 0, 0x1e, &cfi_info->vpp_max);
2587 if (retval != ERROR_OK)
2590 retval = cfi_query_u8(bank, 0, 0x1f, &cfi_info->word_write_timeout_typ);
2591 if (retval != ERROR_OK)
2593 retval = cfi_query_u8(bank, 0, 0x20, &cfi_info->buf_write_timeout_typ);
2594 if (retval != ERROR_OK)
2596 retval = cfi_query_u8(bank, 0, 0x21, &cfi_info->block_erase_timeout_typ);
2597 if (retval != ERROR_OK)
2599 retval = cfi_query_u8(bank, 0, 0x22, &cfi_info->chip_erase_timeout_typ);
2600 if (retval != ERROR_OK)
2602 retval = cfi_query_u8(bank, 0, 0x23, &cfi_info->word_write_timeout_max);
2603 if (retval != ERROR_OK)
2605 retval = cfi_query_u8(bank, 0, 0x24, &cfi_info->buf_write_timeout_max);
2606 if (retval != ERROR_OK)
2608 retval = cfi_query_u8(bank, 0, 0x25, &cfi_info->block_erase_timeout_max);
2609 if (retval != ERROR_OK)
2611 retval = cfi_query_u8(bank, 0, 0x26, &cfi_info->chip_erase_timeout_max);
2612 if (retval != ERROR_OK)
2616 retval = cfi_query_u8(bank, 0, 0x27, &data);
2617 if (retval != ERROR_OK)
2619 cfi_info->dev_size = 1 << data;
2621 retval = cfi_query_u16(bank, 0, 0x28, &cfi_info->interface_desc);
2622 if (retval != ERROR_OK)
2624 retval = cfi_query_u16(bank, 0, 0x2a, &cfi_info->max_buf_write_size);
2625 if (retval != ERROR_OK)
2627 retval = cfi_query_u8(bank, 0, 0x2c, &cfi_info->num_erase_regions);
2628 if (retval != ERROR_OK)
2631 LOG_DEBUG("size: 0x%" PRIx32 ", interface desc: %i, max buffer write size: 0x%x",
2632 cfi_info->dev_size, cfi_info->interface_desc, (1 << cfi_info->max_buf_write_size));
2634 if (cfi_info->num_erase_regions)
2636 cfi_info->erase_region_info = malloc(sizeof(*cfi_info->erase_region_info)
2637 * cfi_info->num_erase_regions);
2638 for (i = 0; i < cfi_info->num_erase_regions; i++)
2640 retval = cfi_query_u32(bank, 0, 0x2d + (4 * i), &cfi_info->erase_region_info[i]);
2641 if (retval != ERROR_OK)
2643 LOG_DEBUG("erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "", i,
2644 (cfi_info->erase_region_info[i] & 0xffff) + 1,
2645 (cfi_info->erase_region_info[i] >> 16) * 256);
2650 cfi_info->erase_region_info = NULL;
2653 /* We need to read the primary algorithm extended query table before calculating
2654 * the sector layout to be able to apply fixups
2656 switch (cfi_info->pri_id)
2658 /* Intel command set (standard and extended) */
2661 cfi_read_intel_pri_ext(bank);
2663 /* AMD/Spansion, Atmel, ... command set */
2665 cfi_info->status_poll_mask = CFI_STATUS_POLL_MASK_DQ5_DQ6_DQ7; /* default for all CFI flashs */
2666 cfi_read_0002_pri_ext(bank);
2669 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2673 /* return to read array mode
2674 * we use both reset commands, as some Intel flashes fail to recognize the 0xF0 command
2676 if ((retval = cfi_reset(bank)) != ERROR_OK)
2680 } /* end CFI case */
2682 LOG_DEBUG("Vcc min: %x.%x, Vcc max: %x.%x, Vpp min: %u.%x, Vpp max: %u.%x",
2683 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2684 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2685 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2686 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2688 LOG_DEBUG("typ. word write timeout: %u us, typ. buf write timeout: %u us, "
2689 "typ. block erase timeout: %u ms, typ. chip erase timeout: %u ms",
2690 1 << cfi_info->word_write_timeout_typ, 1 << cfi_info->buf_write_timeout_typ,
2691 1 << cfi_info->block_erase_timeout_typ, 1 << cfi_info->chip_erase_timeout_typ);
2693 LOG_DEBUG("max. word write timeout: %u us, max. buf write timeout: %u us, "
2694 "max. block erase timeout: %u ms, max. chip erase timeout: %u ms",
2695 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2696 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2697 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2698 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2700 /* convert timeouts to real values in ms */
2701 cfi_info->word_write_timeout = DIV_ROUND_UP((1L << cfi_info->word_write_timeout_typ) *
2702 (1L << cfi_info->word_write_timeout_max), 1000);
2703 cfi_info->buf_write_timeout = DIV_ROUND_UP((1L << cfi_info->buf_write_timeout_typ) *
2704 (1L << cfi_info->buf_write_timeout_max), 1000);
2705 cfi_info->block_erase_timeout = (1L << cfi_info->block_erase_timeout_typ) *
2706 (1L << cfi_info->block_erase_timeout_max);
2707 cfi_info->chip_erase_timeout = (1L << cfi_info->chip_erase_timeout_typ) *
2708 (1L << cfi_info->chip_erase_timeout_max);
2710 LOG_DEBUG("calculated word write timeout: %u ms, buf write timeout: %u ms, "
2711 "block erase timeout: %u ms, chip erase timeout: %u ms",
2712 cfi_info->word_write_timeout, cfi_info->buf_write_timeout,
2713 cfi_info->block_erase_timeout, cfi_info->chip_erase_timeout);
2715 /* apply fixups depending on the primary command set */
2716 switch (cfi_info->pri_id)
2718 /* Intel command set (standard and extended) */
2721 cfi_fixup(bank, cfi_0001_fixups);
2723 /* AMD/Spansion, Atmel, ... command set */
2725 cfi_fixup(bank, cfi_0002_fixups);
2728 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2732 if ((cfi_info->dev_size * bank->bus_width / bank->chip_width) != bank->size)
2734 LOG_WARNING("configuration specifies 0x%" PRIx32 " size, but a 0x%" PRIx32
2735 " size flash was found", bank->size, cfi_info->dev_size);
2738 if (cfi_info->num_erase_regions == 0)
2740 /* a device might have only one erase block, spanning the whole device */
2741 bank->num_sectors = 1;
2742 bank->sectors = malloc(sizeof(struct flash_sector));
2744 bank->sectors[sector].offset = 0x0;
2745 bank->sectors[sector].size = bank->size;
2746 bank->sectors[sector].is_erased = -1;
2747 bank->sectors[sector].is_protected = -1;
2751 uint32_t offset = 0;
2753 for (i = 0; i < cfi_info->num_erase_regions; i++)
2755 num_sectors += (cfi_info->erase_region_info[i] & 0xffff) + 1;
2758 bank->num_sectors = num_sectors;
2759 bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
2761 for (i = 0; i < cfi_info->num_erase_regions; i++)
2764 for (j = 0; j < (cfi_info->erase_region_info[i] & 0xffff) + 1; j++)
2766 bank->sectors[sector].offset = offset;
2767 bank->sectors[sector].size = ((cfi_info->erase_region_info[i] >> 16) * 256)
2768 * bank->bus_width / bank->chip_width;
2769 offset += bank->sectors[sector].size;
2770 bank->sectors[sector].is_erased = -1;
2771 bank->sectors[sector].is_protected = -1;
2775 if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width))
2777 LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \
2778 (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset);
2782 cfi_info->probed = 1;
2787 static int cfi_auto_probe(struct flash_bank *bank)
2789 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2790 if (cfi_info->probed)
2792 return cfi_probe(bank);
2795 static int cfi_intel_protect_check(struct flash_bank *bank)
2798 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2799 struct cfi_intel_pri_ext *pri_ext = cfi_info->pri_ext;
2802 /* check if block lock bits are supported on this device */
2803 if (!(pri_ext->blk_status_reg_mask & 0x1))
2804 return ERROR_FLASH_OPERATION_FAILED;
2806 if ((retval = cfi_send_command(bank, 0x90, flash_address(bank, 0, 0x55))) != ERROR_OK)
2811 for (i = 0; i < bank->num_sectors; i++)
2813 uint8_t block_status;
2814 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2815 if (retval != ERROR_OK)
2818 if (block_status & 1)
2819 bank->sectors[i].is_protected = 1;
2821 bank->sectors[i].is_protected = 0;
2824 return cfi_send_command(bank, 0xff, flash_address(bank, 0, 0x0));
2827 static int cfi_spansion_protect_check(struct flash_bank *bank)
2830 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2831 struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
2834 if ((retval = cfi_send_command(bank, 0xaa,
2835 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2840 if ((retval = cfi_send_command(bank, 0x55,
2841 flash_address(bank, 0, pri_ext->_unlock2))) != ERROR_OK)
2846 if ((retval = cfi_send_command(bank, 0x90,
2847 flash_address(bank, 0, pri_ext->_unlock1))) != ERROR_OK)
2852 for (i = 0; i < bank->num_sectors; i++)
2854 uint8_t block_status;
2855 retval = cfi_get_u8(bank, i, 0x2, &block_status);
2856 if (retval != ERROR_OK)
2859 if (block_status & 1)
2860 bank->sectors[i].is_protected = 1;
2862 bank->sectors[i].is_protected = 0;
2865 return cfi_send_command(bank, 0xf0, flash_address(bank, 0, 0x0));
2868 static int cfi_protect_check(struct flash_bank *bank)
2870 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2872 if (bank->target->state != TARGET_HALTED)
2874 LOG_ERROR("Target not halted");
2875 return ERROR_TARGET_NOT_HALTED;
2878 if (cfi_info->qry[0] != 'Q')
2879 return ERROR_FLASH_BANK_NOT_PROBED;
2881 switch (cfi_info->pri_id)
2885 return cfi_intel_protect_check(bank);
2888 return cfi_spansion_protect_check(bank);
2891 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2898 static int get_cfi_info(struct flash_bank *bank, char *buf, int buf_size)
2901 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2903 if (cfi_info->qry[0] == 0xff)
2905 printed = snprintf(buf, buf_size, "\ncfi flash bank not probed yet\n");
2909 if (cfi_info->not_cfi == 0)
2910 printed = snprintf(buf, buf_size, "\nCFI flash: ");
2912 printed = snprintf(buf, buf_size, "\nnon-CFI flash: ");
2914 buf_size -= printed;
2916 printed = snprintf(buf, buf_size, "mfr: 0x%4.4x, id:0x%4.4x\n\n",
2917 cfi_info->manufacturer, cfi_info->device_id);
2919 buf_size -= printed;
2921 printed = snprintf(buf, buf_size, "qry: '%c%c%c', pri_id: 0x%4.4x, pri_addr: "
2922 "0x%4.4x, alt_id: 0x%4.4x, alt_addr: 0x%4.4x\n",
2923 cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2],
2924 cfi_info->pri_id, cfi_info->pri_addr, cfi_info->alt_id, cfi_info->alt_addr);
2926 buf_size -= printed;
2928 printed = snprintf(buf, buf_size, "Vcc min: %x.%x, Vcc max: %x.%x, "
2929 "Vpp min: %u.%x, Vpp max: %u.%x\n",
2930 (cfi_info->vcc_min & 0xf0) >> 4, cfi_info->vcc_min & 0x0f,
2931 (cfi_info->vcc_max & 0xf0) >> 4, cfi_info->vcc_max & 0x0f,
2932 (cfi_info->vpp_min & 0xf0) >> 4, cfi_info->vpp_min & 0x0f,
2933 (cfi_info->vpp_max & 0xf0) >> 4, cfi_info->vpp_max & 0x0f);
2935 buf_size -= printed;
2937 printed = snprintf(buf, buf_size, "typ. word write timeout: %u us, "
2938 "typ. buf write timeout: %u us, "
2939 "typ. block erase timeout: %u ms, "
2940 "typ. chip erase timeout: %u ms\n",
2941 1 << cfi_info->word_write_timeout_typ,
2942 1 << cfi_info->buf_write_timeout_typ,
2943 1 << cfi_info->block_erase_timeout_typ,
2944 1 << cfi_info->chip_erase_timeout_typ);
2946 buf_size -= printed;
2948 printed = snprintf(buf, buf_size, "max. word write timeout: %u us, "
2949 "max. buf write timeout: %u us, max. "
2950 "block erase timeout: %u ms, max. chip erase timeout: %u ms\n",
2951 (1 << cfi_info->word_write_timeout_max) * (1 << cfi_info->word_write_timeout_typ),
2952 (1 << cfi_info->buf_write_timeout_max) * (1 << cfi_info->buf_write_timeout_typ),
2953 (1 << cfi_info->block_erase_timeout_max) * (1 << cfi_info->block_erase_timeout_typ),
2954 (1 << cfi_info->chip_erase_timeout_max) * (1 << cfi_info->chip_erase_timeout_typ));
2956 buf_size -= printed;
2958 printed = snprintf(buf, buf_size, "size: 0x%" PRIx32 ", interface desc: %i, "
2959 "max buffer write size: 0x%x\n",
2961 cfi_info->interface_desc,
2962 1 << cfi_info->max_buf_write_size);
2964 buf_size -= printed;
2966 switch (cfi_info->pri_id)
2970 cfi_intel_info(bank, buf, buf_size);
2973 cfi_spansion_info(bank, buf, buf_size);
2976 LOG_ERROR("cfi primary command set %i unsupported", cfi_info->pri_id);
2983 static void cfi_fixup_0002_write_buffer(struct flash_bank *bank, void *param)
2985 struct cfi_flash_bank *cfi_info = bank->driver_priv;
2987 /* disable write buffer for M29W128G */
2988 cfi_info->buf_write_timeout_typ = 0;
2991 struct flash_driver cfi_flash = {
2993 .flash_bank_command = cfi_flash_bank_command,
2995 .protect = cfi_protect,
2999 .auto_probe = cfi_auto_probe,
3000 /* FIXME: access flash at bus_width size */
3001 .erase_check = default_flash_blank_check,
3002 .protect_check = cfi_protect_check,
3003 .info = get_cfi_info,