1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * Copyright (C) 2013 by Roman Dmitrienko *
14 * Copyright (C) 2014 Nemui Trinomius *
15 * nemuisan_kawausogasuki@live.jp *
17 * This program is free software; you can redistribute it and/or modify *
18 * it under the terms of the GNU General Public License as published by *
19 * the Free Software Foundation; either version 2 of the License, or *
20 * (at your option) any later version. *
22 * This program is distributed in the hope that it will be useful, *
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
25 * GNU General Public License for more details. *
27 * You should have received a copy of the GNU General Public License *
28 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
29 ***************************************************************************/
36 #include <helper/binarybuffer.h>
37 #include <target/algorithm.h>
38 #include <target/armv7m.h>
39 #include <target/cortex_m.h>
41 /* keep family IDs in decimal */
42 #define EFM_FAMILY_ID_GECKO 71
43 #define EFM_FAMILY_ID_GIANT_GECKO 72
44 #define EFM_FAMILY_ID_TINY_GECKO 73
45 #define EFM_FAMILY_ID_LEOPARD_GECKO 74
46 #define EFM_FAMILY_ID_WONDER_GECKO 75
47 #define EFM_FAMILY_ID_ZERO_GECKO 76
48 #define EFM_FAMILY_ID_HAPPY_GECKO 77
49 #define EZR_FAMILY_ID_WONDER_GECKO 120
50 #define EZR_FAMILY_ID_LEOPARD_GECKO 121
51 #define EZR_FAMILY_ID_HAPPY_GECKO 122
52 #define EFR_FAMILY_ID_MIGHTY_GECKO 16
53 #define EFR_FAMILY_ID_BLUE_GECKO 20
55 #define EFM32_FLASH_ERASE_TMO 100
56 #define EFM32_FLASH_WDATAREADY_TMO 100
57 #define EFM32_FLASH_WRITE_TMO 100
59 /* size in bytes, not words; must fit all Gecko devices */
60 #define LOCKBITS_PAGE_SZ 512
62 #define EFM32_MSC_INFO_BASE 0x0fe00000
64 #define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
65 #define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
66 #define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
68 /* PAGE_SIZE is only present in Leopard, Giant and Wonder Gecko MCUs */
69 #define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
70 #define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
71 #define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
72 #define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
73 #define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
74 #define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
76 #define EFM32_MSC_REGBASE 0x400c0000
77 #define EFR32_MSC_REGBASE 0x400e0000
78 #define EFM32_MSC_REG_WRITECTRL 0x008
79 #define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
80 #define EFM32_MSC_REG_WRITECMD 0x00c
81 #define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
82 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
83 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
84 #define EFM32_MSC_REG_ADDRB 0x010
85 #define EFM32_MSC_REG_WDATA 0x018
86 #define EFM32_MSC_REG_STATUS 0x01c
87 #define EFM32_MSC_STATUS_BUSY_MASK 0x1
88 #define EFM32_MSC_STATUS_LOCKED_MASK 0x2
89 #define EFM32_MSC_STATUS_INVADDR_MASK 0x4
90 #define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
91 #define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
92 #define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
93 #define EFM32_MSC_REG_LOCK 0x03c
94 #define EFR32_MSC_REG_LOCK 0x040
95 #define EFM32_MSC_LOCK_LOCKKEY 0x1b71
97 struct efm32x_flash_bank {
99 uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
105 uint16_t flash_sz_kib;
113 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
114 uint32_t offset, uint32_t count);
116 static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
118 return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
121 static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
123 return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
126 static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
128 return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
131 static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
133 return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
136 static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
138 return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
141 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
144 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
145 uint32_t base = efm32x_info->reg_base;
147 return target_read_u32(bank->target, base + offset, value);
150 static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
153 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
154 uint32_t base = efm32x_info->reg_base;
156 return target_write_u32(bank->target, base + offset, value);
159 static int efm32x_read_info(struct flash_bank *bank,
160 struct efm32_info *efm32_info)
164 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
166 memset(efm32_info, 0, sizeof(struct efm32_info));
168 ret = target_read_u32(bank->target, CPUID, &cpuid);
172 if (((cpuid >> 4) & 0xfff) == 0xc23) {
173 /* Cortex-M3 device */
174 } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
175 /* Cortex-M4 device (WONDER GECKO) */
176 } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
177 /* Cortex-M0+ device */
179 LOG_ERROR("Target is not Cortex-Mx Device");
183 ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
187 ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
191 ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
195 ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
199 ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
203 if (EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
204 EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
205 efm32x_info->reg_base = EFR32_MSC_REGBASE;
206 efm32x_info->reg_lock = EFR32_MSC_REG_LOCK;
208 efm32x_info->reg_base = EFM32_MSC_REGBASE;
209 efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
212 if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
213 EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
214 efm32_info->page_size = 512;
215 else if (EFM_FAMILY_ID_ZERO_GECKO == efm32_info->part_family ||
216 EFM_FAMILY_ID_HAPPY_GECKO == efm32_info->part_family ||
217 EZR_FAMILY_ID_HAPPY_GECKO == efm32_info->part_family)
218 efm32_info->page_size = 1024;
219 else if (EFM_FAMILY_ID_GIANT_GECKO == efm32_info->part_family ||
220 EFM_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
221 if (efm32_info->prod_rev >= 18) {
223 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
228 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
230 /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
231 for MCUs with PROD_REV < 18 */
232 if (efm32_info->flash_sz_kib < 512)
233 efm32_info->page_size = 2048;
235 efm32_info->page_size = 4096;
238 if ((2048 != efm32_info->page_size) &&
239 (4096 != efm32_info->page_size)) {
240 LOG_ERROR("Invalid page size %u", efm32_info->page_size);
243 } else if (EFM_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
244 EZR_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
245 EZR_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family ||
246 EFR_FAMILY_ID_BLUE_GECKO == efm32_info->part_family ||
247 EFR_FAMILY_ID_MIGHTY_GECKO == efm32_info->part_family) {
249 ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
254 efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
255 if (2048 != efm32_info->page_size) {
256 LOG_ERROR("Invalid page size %u", efm32_info->page_size);
260 LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
268 * Helper to create a human friendly string describing a part
270 static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
274 switch (info->part_family) {
275 case EZR_FAMILY_ID_WONDER_GECKO:
276 case EZR_FAMILY_ID_LEOPARD_GECKO:
277 case EZR_FAMILY_ID_HAPPY_GECKO:
278 printed = snprintf(buf, buf_size, "EZR32 ");
280 case EFR_FAMILY_ID_MIGHTY_GECKO:
281 case EFR_FAMILY_ID_BLUE_GECKO:
282 printed = snprintf(buf, buf_size, "EFR32 ");
285 printed = snprintf(buf, buf_size, "EFM32 ");
292 return ERROR_BUF_TOO_SMALL;
294 switch (info->part_family) {
295 case EFM_FAMILY_ID_GECKO:
296 printed = snprintf(buf, buf_size, "Gecko");
298 case EFM_FAMILY_ID_GIANT_GECKO:
299 printed = snprintf(buf, buf_size, "Giant Gecko");
301 case EFM_FAMILY_ID_TINY_GECKO:
302 printed = snprintf(buf, buf_size, "Tiny Gecko");
304 case EFM_FAMILY_ID_LEOPARD_GECKO:
305 case EZR_FAMILY_ID_LEOPARD_GECKO:
306 printed = snprintf(buf, buf_size, "Leopard Gecko");
308 case EFM_FAMILY_ID_WONDER_GECKO:
309 case EZR_FAMILY_ID_WONDER_GECKO:
310 printed = snprintf(buf, buf_size, "Wonder Gecko");
312 case EFM_FAMILY_ID_ZERO_GECKO:
313 printed = snprintf(buf, buf_size, "Zero Gecko");
315 case EFM_FAMILY_ID_HAPPY_GECKO:
316 case EZR_FAMILY_ID_HAPPY_GECKO:
317 printed = snprintf(buf, buf_size, "Happy Gecko");
319 case EFR_FAMILY_ID_BLUE_GECKO:
320 printed = snprintf(buf, buf_size, "Blue Gecko");
322 case EFR_FAMILY_ID_MIGHTY_GECKO:
323 printed = snprintf(buf, buf_size, "Mighty Gecko");
331 return ERROR_BUF_TOO_SMALL;
333 printed = snprintf(buf, buf_size, " - Rev: %d", info->prod_rev);
338 return ERROR_BUF_TOO_SMALL;
343 /* flash bank efm32 <base> <size> 0 0 <target#>
345 FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
347 struct efm32x_flash_bank *efm32x_info;
350 return ERROR_COMMAND_SYNTAX_ERROR;
352 efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
354 bank->driver_priv = efm32x_info;
355 efm32x_info->probed = 0;
356 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
361 /* set or reset given bits in a register */
362 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
363 uint32_t bitmask, int set)
366 uint32_t reg_val = 0;
368 ret = efm32x_read_reg_u32(bank, reg, ®_val);
377 return efm32x_write_reg_u32(bank, reg, reg_val);
380 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
382 return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
383 EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
386 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
388 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
389 return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
390 (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
393 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
394 uint32_t wait_mask, int wait_for_set)
400 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
404 LOG_DEBUG("status: 0x%" PRIx32 "", status);
406 if (((status & wait_mask) == 0) && (0 == wait_for_set))
408 else if (((status & wait_mask) != 0) && wait_for_set)
411 if (timeout-- <= 0) {
412 LOG_ERROR("timed out waiting for MSC status");
419 if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
420 LOG_WARNING("page erase was aborted");
425 static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
427 /* this function DOES NOT set WREN; must be set already */
428 /* 1. write address to ADDRB
430 3. check status (INVADDR, LOCKED)
432 5. wait until !STATUS_BUSY
437 LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
439 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
443 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
444 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
448 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
452 LOG_DEBUG("status 0x%" PRIx32, status);
454 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
455 LOG_ERROR("Page is locked");
457 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
458 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
462 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
463 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
467 return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
468 EFM32_MSC_STATUS_BUSY_MASK, 0);
471 static int efm32x_erase(struct flash_bank *bank, int first, int last)
473 struct target *target = bank->target;
477 if (TARGET_HALTED != target->state) {
478 LOG_ERROR("Target not halted");
479 return ERROR_TARGET_NOT_HALTED;
482 efm32x_msc_lock(bank, 0);
483 ret = efm32x_set_wren(bank, 1);
484 if (ERROR_OK != ret) {
485 LOG_ERROR("Failed to enable MSC write");
489 for (i = first; i <= last; i++) {
490 ret = efm32x_erase_page(bank, bank->sectors[i].offset);
492 LOG_ERROR("Failed to erase page %d", i);
495 ret = efm32x_set_wren(bank, 0);
496 efm32x_msc_lock(bank, 1);
501 static int efm32x_read_lock_data(struct flash_bank *bank)
503 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
504 struct target *target = bank->target;
507 uint32_t *ptr = NULL;
510 assert(bank->num_sectors > 0);
512 /* calculate the number of 32-bit words to read (one lock bit per sector) */
513 data_size = (bank->num_sectors + 31) / 32;
515 ptr = efm32x_info->lb_page;
517 for (i = 0; i < data_size; i++, ptr++) {
518 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
519 if (ERROR_OK != ret) {
520 LOG_ERROR("Failed to read PLW %d", i);
525 /* also, read ULW, DLW and MLW */
528 ptr = efm32x_info->lb_page + 126;
529 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
530 if (ERROR_OK != ret) {
531 LOG_ERROR("Failed to read ULW");
536 ptr = efm32x_info->lb_page + 127;
537 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
538 if (ERROR_OK != ret) {
539 LOG_ERROR("Failed to read DLW");
543 /* MLW, word 125, present in GG and LG */
544 ptr = efm32x_info->lb_page + 125;
545 ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
546 if (ERROR_OK != ret) {
547 LOG_ERROR("Failed to read MLW");
554 static int efm32x_write_lock_data(struct flash_bank *bank)
556 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
559 ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
560 if (ERROR_OK != ret) {
561 LOG_ERROR("Failed to erase LB page");
565 return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
569 static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
571 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
572 uint32_t dw = efm32x_info->lb_page[page >> 5];
575 mask = 1 << (page & 0x1f);
577 return (dw & mask) ? 0 : 1;
580 static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
582 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
583 uint32_t *dw = &efm32x_info->lb_page[page >> 5];
586 mask = 1 << (page & 0x1f);
596 static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
598 struct target *target = bank->target;
603 LOG_ERROR("Erase device data to reset page locks");
607 if (target->state != TARGET_HALTED) {
608 LOG_ERROR("Target not halted");
609 return ERROR_TARGET_NOT_HALTED;
612 for (i = first; i <= last; i++) {
613 ret = efm32x_set_page_lock(bank, i, set);
614 if (ERROR_OK != ret) {
615 LOG_ERROR("Failed to set lock on page %d", i);
620 ret = efm32x_write_lock_data(bank);
621 if (ERROR_OK != ret) {
622 LOG_ERROR("Failed to write LB page");
629 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
630 uint32_t offset, uint32_t count)
632 struct target *target = bank->target;
633 uint32_t buffer_size = 16384;
634 struct working_area *write_algorithm;
635 struct working_area *source;
636 uint32_t address = bank->base + offset;
637 struct reg_param reg_params[5];
638 struct armv7m_algorithm armv7m_info;
639 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
642 /* see contrib/loaders/flash/efm32.S for src */
643 static const uint8_t efm32x_flash_write_code[] = {
644 /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
645 /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
646 /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
647 /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
648 /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
650 0x01, 0x26, /* movs r6, #1 */
651 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
654 0x16, 0x68, /* ldr r6, [r2, #0] */
655 0x00, 0x2e, /* cmp r6, #0 */
656 0x22, 0xd0, /* beq exit */
657 0x55, 0x68, /* ldr r5, [r2, #4] */
658 0xb5, 0x42, /* cmp r5, r6 */
659 0xf9, 0xd0, /* beq wait_fifo */
661 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
662 0x01, 0x26, /* movs r6, #1 */
663 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
664 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
665 0x06, 0x27, /* movs r7, #6 */
666 0x3e, 0x42, /* tst r6, r7 */
667 0x16, 0xd1, /* bne error */
669 /* wait_wdataready: */
670 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
671 0x08, 0x27, /* movs r7, #8 */
672 0x3e, 0x42, /* tst r6, r7 */
673 0xfb, 0xd0, /* beq wait_wdataready */
675 0x2e, 0x68, /* ldr r6, [r5] */
676 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
677 0x08, 0x26, /* movs r6, #8 */
678 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
680 0x04, 0x35, /* adds r5, #4 */
681 0x04, 0x34, /* adds r4, #4 */
684 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
685 0x01, 0x27, /* movs r7, #1 */
686 0x3e, 0x42, /* tst r6, r7 */
687 0xfb, 0xd1, /* bne busy */
689 0x9d, 0x42, /* cmp r5, r3 */
690 0x01, 0xd3, /* bcc no_wrap */
691 0x15, 0x46, /* mov r5, r2 */
692 0x08, 0x35, /* adds r5, #8 */
695 0x55, 0x60, /* str r5, [r2, #4] */
696 0x01, 0x39, /* subs r1, r1, #1 */
697 0x00, 0x29, /* cmp r1, #0 */
698 0x02, 0xd0, /* beq exit */
699 0xdb, 0xe7, /* b wait_fifo */
702 0x00, 0x20, /* movs r0, #0 */
703 0x50, 0x60, /* str r0, [r2, #4] */
706 0x30, 0x46, /* mov r0, r6 */
707 0x00, 0xbe, /* bkpt #0 */
711 /* flash write code */
712 if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
713 &write_algorithm) != ERROR_OK) {
714 LOG_WARNING("no working area available, can't do block memory writes");
715 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
718 ret = target_write_buffer(target, write_algorithm->address,
719 sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
724 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
726 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
727 if (buffer_size <= 256) {
728 /* we already allocated the writing code, but failed to get a
729 * buffer, free the algorithm */
730 target_free_working_area(target, write_algorithm);
732 LOG_WARNING("no large enough working area available, can't do block memory writes");
733 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
737 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
738 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
739 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
740 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
741 init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
743 buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
744 buf_set_u32(reg_params[1].value, 0, 32, count);
745 buf_set_u32(reg_params[2].value, 0, 32, source->address);
746 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
747 buf_set_u32(reg_params[4].value, 0, 32, address);
749 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
750 armv7m_info.core_mode = ARM_MODE_THREAD;
752 ret = target_run_flash_async_algorithm(target, buf, count, 4,
755 source->address, source->size,
756 write_algorithm->address, 0,
759 if (ret == ERROR_FLASH_OPERATION_FAILED) {
760 LOG_ERROR("flash write failed at address 0x%"PRIx32,
761 buf_get_u32(reg_params[4].value, 0, 32));
763 if (buf_get_u32(reg_params[0].value, 0, 32) &
764 EFM32_MSC_STATUS_LOCKED_MASK) {
765 LOG_ERROR("flash memory write protected");
768 if (buf_get_u32(reg_params[0].value, 0, 32) &
769 EFM32_MSC_STATUS_INVADDR_MASK) {
770 LOG_ERROR("invalid flash memory write address");
774 target_free_working_area(target, source);
775 target_free_working_area(target, write_algorithm);
777 destroy_reg_param(®_params[0]);
778 destroy_reg_param(®_params[1]);
779 destroy_reg_param(®_params[2]);
780 destroy_reg_param(®_params[3]);
781 destroy_reg_param(®_params[4]);
786 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
789 /* this function DOES NOT set WREN; must be set already */
790 /* 1. write address to ADDRB
792 3. check status (INVADDR, LOCKED)
793 4. wait for WDATAREADY
794 5. write data to WDATA
795 6. write WRITECMD_WRITEONCE to WRITECMD
796 7. wait until !STATUS_BUSY
799 /* FIXME: EFM32G ref states (7.3.2) that writes should be
800 * performed twice per dword */
805 /* if not called, GDB errors will be reported during large writes */
808 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
812 ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
813 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
817 ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
821 LOG_DEBUG("status 0x%" PRIx32, status);
823 if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
824 LOG_ERROR("Page is locked");
826 } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
827 LOG_ERROR("Invalid address 0x%" PRIx32, addr);
831 ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
832 EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
833 if (ERROR_OK != ret) {
834 LOG_ERROR("Wait for WDATAREADY failed");
838 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
839 if (ERROR_OK != ret) {
840 LOG_ERROR("WDATA write failed");
844 ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
845 EFM32_MSC_WRITECMD_WRITEONCE_MASK);
846 if (ERROR_OK != ret) {
847 LOG_ERROR("WRITECMD write failed");
851 ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
852 EFM32_MSC_STATUS_BUSY_MASK, 0);
853 if (ERROR_OK != ret) {
854 LOG_ERROR("Wait for BUSY failed");
861 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
862 uint32_t offset, uint32_t count)
864 struct target *target = bank->target;
865 uint8_t *new_buffer = NULL;
867 if (target->state != TARGET_HALTED) {
868 LOG_ERROR("Target not halted");
869 return ERROR_TARGET_NOT_HALTED;
873 LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
874 "alignment", offset);
875 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
879 uint32_t old_count = count;
880 count = (old_count | 3) + 1;
881 new_buffer = malloc(count);
882 if (new_buffer == NULL) {
883 LOG_ERROR("odd number of bytes to write and no memory "
884 "for padding buffer");
887 LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
888 "and padding with 0xff", old_count, count);
889 memset(new_buffer, 0xff, count);
890 buffer = memcpy(new_buffer, buffer, old_count);
893 uint32_t words_remaining = count / 4;
896 /* unlock flash registers */
897 efm32x_msc_lock(bank, 0);
898 retval = efm32x_set_wren(bank, 1);
899 if (retval != ERROR_OK)
902 /* try using a block write */
903 retval = efm32x_write_block(bank, buffer, offset, words_remaining);
905 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
906 /* if block write failed (no sufficient working area),
907 * we use normal (slow) single word accesses */
908 LOG_WARNING("couldn't use block writes, falling back to single "
911 while (words_remaining > 0) {
913 memcpy(&value, buffer, sizeof(uint32_t));
915 retval = efm32x_write_word(bank, offset, value);
916 if (retval != ERROR_OK)
917 goto reset_pg_and_lock;
926 retval2 = efm32x_set_wren(bank, 0);
927 efm32x_msc_lock(bank, 1);
928 if (retval == ERROR_OK)
938 static int efm32x_probe(struct flash_bank *bank)
940 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
941 struct efm32_info efm32_mcu_info;
944 uint32_t base_address = 0x00000000;
947 efm32x_info->probed = 0;
948 memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
950 ret = efm32x_read_info(bank, &efm32_mcu_info);
954 ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
958 LOG_INFO("detected part: %s", buf);
959 LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
960 LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
962 assert(0 != efm32_mcu_info.page_size);
964 int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
965 efm32_mcu_info.page_size;
967 assert(num_pages > 0);
971 bank->sectors = NULL;
974 bank->base = base_address;
975 bank->size = (num_pages * efm32_mcu_info.page_size);
976 bank->num_sectors = num_pages;
978 ret = efm32x_read_lock_data(bank);
979 if (ERROR_OK != ret) {
980 LOG_ERROR("Failed to read LB data");
984 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
986 for (i = 0; i < num_pages; i++) {
987 bank->sectors[i].offset = i * efm32_mcu_info.page_size;
988 bank->sectors[i].size = efm32_mcu_info.page_size;
989 bank->sectors[i].is_erased = -1;
990 bank->sectors[i].is_protected = 1;
993 efm32x_info->probed = 1;
998 static int efm32x_auto_probe(struct flash_bank *bank)
1000 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1001 if (efm32x_info->probed)
1003 return efm32x_probe(bank);
1006 static int efm32x_protect_check(struct flash_bank *bank)
1008 struct target *target = bank->target;
1012 if (target->state != TARGET_HALTED) {
1013 LOG_ERROR("Target not halted");
1014 return ERROR_TARGET_NOT_HALTED;
1017 ret = efm32x_read_lock_data(bank);
1018 if (ERROR_OK != ret) {
1019 LOG_ERROR("Failed to read LB data");
1023 assert(NULL != bank->sectors);
1025 for (i = 0; i < bank->num_sectors; i++)
1026 bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
1031 static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1033 struct efm32_info info;
1036 ret = efm32x_read_info(bank, &info);
1037 if (ERROR_OK != ret) {
1038 LOG_ERROR("Failed to read EFM32 info");
1042 return efm32x_decode_info(&info, buf, buf_size);
1045 COMMAND_HANDLER(efm32x_handle_debuglock_command)
1047 struct target *target = NULL;
1050 return ERROR_COMMAND_SYNTAX_ERROR;
1052 struct flash_bank *bank;
1053 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1054 if (ERROR_OK != retval)
1057 struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
1059 target = bank->target;
1061 if (target->state != TARGET_HALTED) {
1062 LOG_ERROR("Target not halted");
1063 return ERROR_TARGET_NOT_HALTED;
1067 ptr = efm32x_info->lb_page + 127;
1070 retval = efm32x_write_lock_data(bank);
1071 if (ERROR_OK != retval) {
1072 LOG_ERROR("Failed to write LB page");
1076 command_print(CMD_CTX, "efm32x debug interface locked, reset the device to apply");
1081 static const struct command_registration efm32x_exec_command_handlers[] = {
1083 .name = "debuglock",
1084 .handler = efm32x_handle_debuglock_command,
1085 .mode = COMMAND_EXEC,
1087 .help = "Lock the debug interface of the device.",
1089 COMMAND_REGISTRATION_DONE
1092 static const struct command_registration efm32x_command_handlers[] = {
1095 .mode = COMMAND_ANY,
1096 .help = "efm32 flash command group",
1098 .chain = efm32x_exec_command_handlers,
1100 COMMAND_REGISTRATION_DONE
1103 struct flash_driver efm32_flash = {
1105 .commands = efm32x_command_handlers,
1106 .flash_bank_command = efm32x_flash_bank_command,
1107 .erase = efm32x_erase,
1108 .protect = efm32x_protect,
1109 .write = efm32x_write,
1110 .read = default_flash_read,
1111 .probe = efm32x_probe,
1112 .auto_probe = efm32x_auto_probe,
1113 .erase_check = default_flash_blank_check,
1114 .protect_check = efm32x_protect_check,
1115 .info = get_efm32x_info,