git.sur5r.net Git - openocd/blob - src/flash/nor/spearsmi.c

   1 /***************************************************************************
   2  *   Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com>       *
   3  *                                                                         *
   4  *   This program is free software; you can redistribute it and/or modify  *
   5  *   it under the terms of the GNU General Public License as published by  *
   6  *   the Free Software Foundation; either version 2 of the License, or     *
   7  *   (at your option) any later version.                                   *
   8  *                                                                         *
   9  *   This program is distributed in the hope that it will be useful,       *
  10  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  11  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  12  *   GNU General Public License for more details.                          *
  13  *                                                                         *
  14  *   You should have received a copy of the GNU General Public License     *
  15  *   along with this program; if not, write to the                         *
  16  *   Free Software Foundation, Inc.,                                       *
  17  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  18  ***************************************************************************/
  19
  20 /* SPEAr Serial Memory Interface (SMI) controller is a SPI bus controller
  21  * specifically designed for SPI memories.
  22  * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
  23  * Two working modes are available:
  24  * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
  25  *   on the bus.
  26  * - HW mode: the SPI but is under SMI control. Memory content is directly
  27  *   accessible in CPU memory space. CPU can read, write and execute memory
  28  *   content. */
  29
  30 /* ATTENTION:
  31  * To have flash memory mapped in CPU memory space, the SMI controller
  32  * have to be in "HW mode". This requires following constraints:
  33  * 1) The command "reset init" have to initialize SMI controller and put
  34  *    it in HW mode;
  35  * 2) every command in this file have to return to prompt in HW mode. */
  36
  37 #ifdef HAVE_CONFIG_H
  38 #include "config.h"
  39 #endif
  40
  41 #include "imp.h"
  42 #include <jtag/jtag.h>
  43 #include <helper/time_support.h>
  44
  45 #define JTAG_ID_3XX_6XX  (0x07926041)
  46
  47 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
  48 #define _SMI_READ_REG(a)                \
  49 {                                       \
  50         int __a;                        \
  51         uint32_t __v;                   \
  52                                         \
  53         __a = target_read_u32(target, io_base + (a), &__v); \
  54         if (__a != ERROR_OK)            \
  55             return __a;                 \
  56         __v;                            \
  57 }
  58
  59 #define SMI_WRITE_REG(a,v)              \
  60 {                                       \
  61         int __r;                        \
  62                                         \
  63         __r = target_write_u32(target, io_base + (a), (v)); \
  64         if (__r != ERROR_OK)            \
  65             return __r;                 \
  66 }
  67
  68 #define SMI_POLL_TFF(timeout)           \
  69 {                                       \
  70         int __r;                        \
  71                                         \
  72         __r = poll_tff(target, io_base, timeout); \
  73         if (__r != ERROR_OK)            \
  74             return __r;                 \
  75 }
  76
  77 #define SMI_SET_SW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  78         SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
  79 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
  80         (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
  81 #define SMI_SET_HW_MODE()       SMI_WRITE_REG(SMI_CR1, \
  82         SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
  83 #define SMI_CLEAR_TFF()         SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
  84
  85 #define SMI_BANK_SIZE      (0x01000000)
  86
  87 #define SMI_BASE_3XX_6XX   (0xf8000000)
  88 #define SMI_CFGREG_3XX_6XX (0xfc000000)
  89
  90 /* #define SMI_BASE_13XX      (0xe6000000) */
  91 /* #define SMI_CFGREG_13XX    (0xea000000) */
  92
  93 #define SMI_CR1 (0x00) /* Control register 1 */
  94 #define SMI_CR2 (0x04) /* Control register 2 */
  95 #define SMI_SR  (0x08) /* Status register */
  96 #define SMI_TR  (0x0c) /* TX */
  97 #define SMI_RR  (0x10) /* RX */
  98
  99 /* fields in SMI_CR1 */
 100 #define SMI_SW_MODE       0x10000000 /* set to enable SW Mode */
 101 #define SMI_WB_MODE       0x20000000 /* Write Burst Mode */
 102
 103 /* fields in SMI_CR2 */
 104 #define SMI_TX_LEN_1      0x00000001 /* data length = 1 byte */
 105 #define SMI_TX_LEN_4      0x00000004 /* data length = 4 byte */
 106 #define SMI_RX_LEN_3      0x00000030 /* data length = 3 byte */
 107 #define SMI_SEND          0x00000080 /* Send data */
 108 #define SMI_RSR           0x00000400 /* reads status reg */
 109 #define SMI_WE            0x00000800 /* Write Enable */
 110 #define SMI_SEL_BANK0     0x00000000 /* Select Bank0 */
 111 #define SMI_SEL_BANK1     0x00001000 /* Select Bank1 */
 112 #define SMI_SEL_BANK2     0x00002000 /* Select Bank2 */
 113 #define SMI_SEL_BANK3     0x00003000 /* Select Bank3 */
 114
 115 /* fields in SMI_SR */
 116 #define SMI_WIP_BIT       0x00000001 /* WIP Bit of SPI SR on SMI SR */
 117 #define SMI_WEL_BIT       0x00000002 /* WEL Bit of SPI SR on SMI SR */
 118 #define SMI_TFF           0x00000100 /* Transfer Finished Flag */
 119
 120 /* Commands */
 121 #define SMI_READ_ID       0x0000009F /* Read Flash Identification */
 122
 123 /* Timeout in ms */
 124 #define SMI_CMD_TIMEOUT   (100)
 125 #define SMI_PROBE_TIMEOUT (100)
 126 #define SMI_MAX_TIMEOUT  (3000)
 127
 128 struct spearsmi_flash_bank
 129 {
 130         int probed;
 131         uint32_t io_base;
 132         uint32_t bank_num;
 133         struct flash_device *dev;
 134 };
 135
 136 /* data structure to maintain flash ids from different vendors */
 137 struct flash_device {
 138         char *name;
 139         uint8_t erase_cmd;
 140         uint32_t device_id;
 141         uint32_t pagesize;
 142         unsigned long sectorsize;
 143         unsigned long size_in_bytes;
 144 };
 145
 146 #define FLASH_ID(n, es, id, psize, ssize, size) \
 147 {                               \
 148         .name = n,              \
 149         .erase_cmd = es,        \
 150         .device_id = id,        \
 151         .pagesize = psize,      \
 152         .sectorsize = ssize,    \
 153         .size_in_bytes = size   \
 154 }
 155
 156 /* List below is taken from Linux driver. It is not exhaustive of all the
 157  * possible SPI memories, nor exclusive for SMI. Could be shared with
 158  * other SPI drivers. */
 159 static struct flash_device flash_devices[] = {
 160         /* name, erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */
 161         FLASH_ID("st m25p05",      0xd8, 0x00102020, 0x80,  0x8000,  0x10000),
 162         FLASH_ID("st m25p10",      0xd8, 0x00112020, 0x80,  0x8000,  0x20000),
 163         FLASH_ID("st m25p20",      0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
 164         FLASH_ID("st m25p40",      0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
 165         FLASH_ID("st m25p80",      0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
 166         FLASH_ID("st m25p16",      0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
 167         FLASH_ID("st m25p32",      0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
 168         FLASH_ID("st m25p64",      0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
 169         FLASH_ID("st m25p128",     0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
 170         FLASH_ID("st m45pe10",     0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
 171         FLASH_ID("st m45pe20",     0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
 172         FLASH_ID("st m45pe40",     0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
 173         FLASH_ID("st m45pe80",     0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
 174         FLASH_ID("sp s25fl004",    0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
 175         FLASH_ID("sp s25fl008",    0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
 176         FLASH_ID("sp s25fl016",    0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
 177         FLASH_ID("sp s25fl032",    0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
 178         FLASH_ID("sp s25fl064",    0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
 179         FLASH_ID("atmel 25f512",   0x52, 0x0065001f, 0x80,  0x8000,  0x10000),
 180         FLASH_ID("atmel 25f1024",  0x52, 0x0060001f, 0x100, 0x8000,  0x20000),
 181         FLASH_ID("atmel 25f2048",  0x52, 0x0063001f, 0x100, 0x10000, 0x40000),
 182         FLASH_ID("atmel 25f4096",  0x52, 0x0064001f, 0x100, 0x10000, 0x80000),
 183         FLASH_ID("atmel 25fs040",  0xd7, 0x0004661f, 0x100, 0x10000, 0x80000),
 184         FLASH_ID("mac 25l512",     0xd8, 0x001020c2, 0x010, 0x10000, 0x10000),
 185         FLASH_ID("mac 25l1005",    0xd8, 0x001120c2, 0x010, 0x10000, 0x20000),
 186         FLASH_ID("mac 25l2005",    0xd8, 0x001220c2, 0x010, 0x10000, 0x40000),
 187         FLASH_ID("mac 25l4005",    0xd8, 0x001320c2, 0x010, 0x10000, 0x80000),
 188         FLASH_ID("mac 25l8005",    0xd8, 0x001420c2, 0x010, 0x10000, 0x100000),
 189         FLASH_ID("mac 25l1605",    0xd8, 0x001520c2, 0x100, 0x10000, 0x200000),
 190         FLASH_ID("mac 25l3205",    0xd8, 0x001620c2, 0x100, 0x10000, 0x400000),
 191         FLASH_ID("mac 25l6405",    0xd8, 0x001720c2, 0x100, 0x10000, 0x800000),
 192         FLASH_ID(NULL,             0,    0,          0,     0,       0)
 193 };
 194
 195 FLASH_BANK_COMMAND_HANDLER(spearsmi_flash_bank_command)
 196 {
 197         struct spearsmi_flash_bank *spearsmi_info;
 198
 199         LOG_DEBUG(__FUNCTION__);
 200
 201         if (CMD_ARGC < 6)
 202         {
 203                 LOG_WARNING("incomplete flash_bank spearsmi configuration");
 204                 return ERROR_FLASH_BANK_INVALID;
 205         }
 206
 207         spearsmi_info = malloc(sizeof(struct spearsmi_flash_bank));
 208         if (spearsmi_info == NULL)
 209         {
 210                 LOG_ERROR("not enough memory");
 211                 return ERROR_FAIL;
 212         }
 213
 214         bank->driver_priv = spearsmi_info;
 215         spearsmi_info->probed = 0;
 216
 217         return ERROR_OK;
 218 }
 219
 220 /* Poll transmit finished flag */
 221 /* timeout in ms */
 222 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
 223 {
 224         long long endtime;
 225
 226         if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 227                 return ERROR_OK;
 228
 229         endtime = timeval_ms() + timeout;
 230         do {
 231                 alive_sleep(1);
 232                 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
 233                         return ERROR_OK;
 234         } while (timeval_ms() < endtime);
 235
 236         LOG_ERROR("Timeout while polling TFF");
 237         return ERROR_FLASH_OPERATION_FAILED;
 238 }
 239
 240 /* Read the status register of the external SPI flash chip.
 241  * The operation is triggered by setting SMI_RSR bit.
 242  * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
 243 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
 244 {
 245         struct target *target = bank->target;
 246         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 247         uint32_t io_base = spearsmi_info->io_base;
 248
 249         /* clear transmit finished flag */
 250         SMI_CLEAR_TFF();
 251
 252         /* Read status */
 253         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_RSR);
 254
 255         /* Poll transmit finished flag */
 256         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 257
 258         /* clear transmit finished flag */
 259         SMI_CLEAR_TFF();
 260
 261         *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
 262
 263         /* clean-up SMI_CR2 */
 264         SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
 265
 266         return ERROR_OK;
 267 }
 268
 269 /* check for WIP (write in progress) bit in status register */
 270 /* timeout in ms */
 271 static int wait_till_ready(struct flash_bank *bank, int timeout)
 272 {
 273         uint32_t status;
 274         int retval;
 275         long long endtime;
 276
 277     endtime = timeval_ms() + timeout;
 278     do {
 279         /* read flash status register */
 280         retval = read_status_reg(bank, &status);
 281         if (retval != ERROR_OK)
 282             return retval;
 283
 284                 if ((status & SMI_WIP_BIT) == 0)
 285                         return ERROR_OK;
 286                 alive_sleep(1);
 287     } while (timeval_ms() < endtime);
 288
 289         LOG_ERROR("timeout");
 290         return ERROR_FAIL;
 291 }
 292
 293 /* Send "write enable" command to SPI flash chip.
 294  * The operation is triggered by setting SMI_WE bit, and SMI sends
 295  * the proper SPI command (0x06) */
 296 static int smi_write_enable(struct flash_bank *bank)
 297 {
 298         struct target *target = bank->target;
 299         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 300         uint32_t io_base = spearsmi_info->io_base;
 301         uint32_t status;
 302         int retval;
 303
 304         /* Enter in HW mode */
 305         SMI_SET_HW_MODE(); /* AB: is this correct ?*/
 306
 307         /* clear transmit finished flag */
 308         SMI_CLEAR_TFF();
 309
 310         /* Send write enable command */
 311         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_WE);
 312
 313         /* Poll transmit finished flag */
 314         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 315
 316         /* read flash status register */
 317         retval = read_status_reg(bank, &status);
 318         if (retval != ERROR_OK)
 319                 return retval;
 320
 321         /* Check write enabled */
 322         if ((status & SMI_WEL_BIT) == 0)
 323         {
 324                 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
 325                 return ERROR_FAIL;
 326         }
 327
 328         return ERROR_OK;
 329 }
 330
 331 static uint32_t erase_command(struct spearsmi_flash_bank *spearsmi_info,
 332         uint32_t offset)
 333 {
 334         union {
 335                 uint32_t command;
 336                 uint8_t x[4];
 337         } cmd;
 338
 339         cmd.x[0] = spearsmi_info->dev->erase_cmd;
 340         cmd.x[1] = offset >> 16;
 341         cmd.x[2] = offset >> 8;
 342         cmd.x[3] = offset;
 343
 344         return cmd.command;
 345 }
 346
 347 static int smi_erase_sector(struct flash_bank *bank, int sector)
 348 {
 349         struct target *target = bank->target;
 350         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 351         uint32_t io_base = spearsmi_info->io_base;
 352         uint32_t cmd;
 353         int retval;
 354
 355         retval = smi_write_enable(bank);
 356         if (retval != ERROR_OK)
 357                 return retval;
 358
 359         /* Switch to SW mode to send sector erase command */
 360         SMI_SET_SW_MODE();
 361
 362         /* clear transmit finished flag */
 363         SMI_CLEAR_TFF();
 364
 365         /* send SPI command "block erase" */
 366         cmd = erase_command(spearsmi_info, bank->sectors[sector].offset);
 367         SMI_WRITE_REG(SMI_TR, cmd);
 368         SMI_WRITE_REG(SMI_CR2, spearsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
 369
 370         /* Poll transmit finished flag */
 371         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 372
 373         /* poll WIP for end of self timed Sector Erase cycle */
 374         retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
 375         if (retval != ERROR_OK)
 376                 return retval;
 377
 378         return ERROR_OK;
 379 }
 380
 381 static int spearsmi_erase(struct flash_bank *bank, int first, int last)
 382 {
 383         struct target *target = bank->target;
 384         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 385         uint32_t io_base = spearsmi_info->io_base;
 386         int retval = ERROR_OK;
 387         int sector;
 388
 389         LOG_DEBUG("%s: from sector %d to sector %d", __FUNCTION__, first, last);
 390
 391         if (target->state != TARGET_HALTED)
 392         {
 393                 LOG_ERROR("Target not halted");
 394                 return ERROR_TARGET_NOT_HALTED;
 395         }
 396
 397         if ((first < 0) || (last < first) || (last >= bank->num_sectors))
 398         {
 399                 LOG_ERROR("Flash sector invalid");
 400                 return ERROR_FLASH_SECTOR_INVALID;
 401         }
 402
 403         if (!(spearsmi_info->probed))
 404         {
 405                 LOG_ERROR("Flash bank not probed");
 406                 return ERROR_FLASH_BANK_NOT_PROBED;
 407         }
 408
 409         for (sector = first; sector <= last; sector++)
 410         {
 411                 if (bank->sectors[sector].is_protected)
 412                 {
 413                         LOG_ERROR("Flash sector %d protected", sector);
 414                         return ERROR_FAIL;
 415                 }
 416         }
 417
 418         for (sector = first; sector <= last; sector++)
 419         {
 420                 retval = smi_erase_sector(bank, sector);
 421                 if (retval != ERROR_OK)
 422                         break;
 423                 keep_alive();
 424         }
 425
 426         /* Switch to HW mode before return to prompt */
 427         SMI_SET_HW_MODE();
 428         return retval;
 429 }
 430
 431 static int spearsmi_protect(struct flash_bank *bank, int set,
 432         int first, int last)
 433 {
 434         int sector;
 435
 436         for (sector = first; sector <= last; sector++)
 437                 bank->sectors[sector].is_protected = set;
 438         return ERROR_OK;
 439 }
 440
 441 static int smi_write_buffer(struct flash_bank *bank, uint8_t *buffer,
 442         uint32_t address, uint32_t len)
 443 {
 444         struct target *target = bank->target;
 445         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 446         uint32_t io_base = spearsmi_info->io_base;
 447         int retval;
 448
 449         LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
 450                 __FUNCTION__, address, len);
 451
 452         retval = smi_write_enable(bank);
 453         if (retval != ERROR_OK)
 454                 return retval;
 455
 456         /* HW mode, write burst mode */
 457         SMI_SET_HWWB_MODE();
 458
 459         retval = target_write_buffer(target, address, len, buffer);
 460         if (retval != ERROR_OK)
 461                 return retval;
 462
 463         return ERROR_OK;
 464 }
 465
 466 static int spearsmi_write(struct flash_bank *bank, uint8_t *buffer,
 467         uint32_t offset, uint32_t count)
 468 {
 469         struct target *target = bank->target;
 470         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 471         uint32_t io_base = spearsmi_info->io_base;
 472         uint32_t cur_count, page_size, page_offset;
 473         int sector;
 474         int retval = ERROR_OK;
 475
 476         LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
 477                 __FUNCTION__, offset, count);
 478
 479         if (target->state != TARGET_HALTED)
 480         {
 481                 LOG_ERROR("Target not halted");
 482                 return ERROR_TARGET_NOT_HALTED;
 483         }
 484
 485         if (offset + count > spearsmi_info->dev->size_in_bytes)
 486         {
 487                 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
 488                 count = spearsmi_info->dev->size_in_bytes - offset;
 489         }
 490
 491         /* Check sector protection */
 492         for (sector = 0; sector < bank->num_sectors; sector++)
 493         {
 494                 /* Start offset in or before this sector? */
 495                 /* End offset in or behind this sector? */
 496                 if ( (offset <
 497                                 (bank->sectors[sector].offset + bank->sectors[sector].size))
 498                         && ((offset + count - 1) >= bank->sectors[sector].offset)
 499                         && bank->sectors[sector].is_protected )
 500                 {
 501                         LOG_ERROR("Flash sector %d protected", sector);
 502                         return ERROR_FAIL;
 503                 }
 504         }
 505
 506         page_size = spearsmi_info->dev->pagesize;
 507
 508         /* unaligned buffer head */
 509         if (count > 0 && (offset & 3) != 0)
 510         {
 511                 cur_count = 4 - (offset & 3);
 512                 if (cur_count > count)
 513                         cur_count = count;
 514                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 515                         cur_count);
 516                 if (retval != ERROR_OK)
 517                         goto err;
 518                 offset += cur_count;
 519                 buffer += cur_count;
 520                 count -= cur_count;
 521         }
 522
 523         page_offset = offset % page_size;
 524         /* central part, aligned words */
 525         while (count >= 4)
 526         {
 527                 /* clip block at page boundary */
 528                 if (page_offset + count > page_size)
 529                         cur_count = page_size - page_offset;
 530                 else
 531                         cur_count = count & ~3;
 532
 533                 retval = smi_write_buffer(bank, buffer, bank->base + offset,
 534                         cur_count);
 535                 if (retval != ERROR_OK)
 536                         goto err;
 537
 538                 page_offset = 0;
 539                 buffer += cur_count;
 540                 offset += cur_count;
 541                 count -= cur_count;
 542
 543                 keep_alive();
 544         }
 545
 546         /* buffer tail */
 547         if (count > 0)
 548                 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
 549
 550 err:
 551         /* Switch to HW mode before return to prompt */
 552         SMI_SET_HW_MODE();
 553         return retval;
 554 }
 555
 556 /* Return ID of flash device */
 557 /* On exit, SW mode is kept */
 558 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
 559 {
 560         struct target *target = bank->target;
 561         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 562         uint32_t io_base = spearsmi_info->io_base;
 563         int retval;
 564
 565         if (target->state != TARGET_HALTED)
 566         {
 567                 LOG_ERROR("Target not halted");
 568                 return ERROR_TARGET_NOT_HALTED;
 569         }
 570
 571         /* poll WIP */
 572         retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
 573         if (retval != ERROR_OK)
 574                 return retval;
 575
 576         /* enter in SW mode */
 577         SMI_SET_SW_MODE();
 578
 579         /* clear transmit finished flag */
 580         SMI_CLEAR_TFF();
 581
 582         /* Send SPI command "read ID" */
 583         SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
 584         SMI_WRITE_REG(SMI_CR2,
 585                 spearsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
 586
 587         /* Poll transmit finished flag */
 588         SMI_POLL_TFF(SMI_CMD_TIMEOUT);
 589
 590         /* clear transmit finished flag */
 591         SMI_CLEAR_TFF();
 592
 593         /* read ID from Receive Register */
 594         *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
 595         return ERROR_OK;
 596 }
 597
 598 static int spearsmi_probe(struct flash_bank *bank)
 599 {
 600         struct target *target = bank->target;
 601         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 602         uint32_t io_base;
 603         struct flash_sector *sectors;
 604         uint32_t id = 0; /* silence uninitialized warning */
 605         int retval;
 606
 607         if (spearsmi_info->probed)
 608                 free(bank->sectors);
 609         spearsmi_info->probed = 0;
 610
 611         /* check for SPEAr device */
 612         switch (target->tap->idcode)
 613         {
 614                 case JTAG_ID_3XX_6XX:
 615                         /* SPEAr3xx/6xx */
 616                         spearsmi_info->io_base = SMI_CFGREG_3XX_6XX;
 617                         switch (bank->base)
 618                         {
 619                                 case SMI_BASE_3XX_6XX:
 620                                         spearsmi_info->bank_num = SMI_SEL_BANK0;
 621                                         break;
 622                                 case SMI_BASE_3XX_6XX + SMI_BANK_SIZE:
 623                                         spearsmi_info->bank_num = SMI_SEL_BANK1;
 624                                         break;
 625                                 case SMI_BASE_3XX_6XX + 2*SMI_BANK_SIZE:
 626                                         spearsmi_info->bank_num = SMI_SEL_BANK2;
 627                                         break;
 628                                 case SMI_BASE_3XX_6XX + 3*SMI_BANK_SIZE:
 629                                         spearsmi_info->bank_num = SMI_SEL_BANK3;
 630                                         break;
 631                                 default:
 632                                         LOG_ERROR("Invalid base address 0x%" PRIx32, bank->base);
 633                                         return ERROR_FAIL;
 634                         }
 635                         break;
 636
 637                 default:
 638                         LOG_ERROR("0x%" PRIx32 " is invalid id for SPEAr device",
 639                                 target->tap->idcode);
 640                         return ERROR_FAIL;
 641         }
 642         io_base = spearsmi_info->io_base;
 643
 644         /* read and decode flash ID; returns in SW mode */
 645         retval = read_flash_id(bank, &id);
 646         SMI_SET_HW_MODE();
 647         if (retval != ERROR_OK)
 648                 return retval;
 649
 650         for (struct flash_device *p = flash_devices; p->name ; p++)
 651                 if (p->device_id == id) {
 652                         spearsmi_info->dev = p;
 653                         break;
 654                 }
 655
 656         if (!spearsmi_info->dev)
 657         {
 658                 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
 659                 return ERROR_FAIL;
 660         }
 661
 662         LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
 663                 spearsmi_info->dev->name, spearsmi_info->dev->device_id);
 664
 665         /* Set correct size value */
 666         bank->size = spearsmi_info->dev->size_in_bytes;
 667
 668         /* create and fill sectors array */
 669         bank->num_sectors =
 670                 spearsmi_info->dev->size_in_bytes / spearsmi_info->dev->sectorsize;
 671         sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 672         if (sectors == NULL)
 673         {
 674                 LOG_ERROR("not enough memory");
 675                 return ERROR_FAIL;
 676         }
 677
 678         for (int sector = 0; sector < bank->num_sectors; sector++)
 679         {
 680                 sectors[sector].offset = sector * spearsmi_info->dev->sectorsize;
 681                 sectors[sector].size = spearsmi_info->dev->sectorsize;
 682                 sectors[sector].is_erased = -1;
 683                 sectors[sector].is_protected = 1;
 684         }
 685
 686         bank->sectors = sectors;
 687         spearsmi_info->probed = 1;
 688         return ERROR_OK;
 689 }
 690
 691 static int spearsmi_auto_probe(struct flash_bank *bank)
 692 {
 693         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 694         if (spearsmi_info->probed)
 695                 return ERROR_OK;
 696         return spearsmi_probe(bank);
 697 }
 698
 699 static int spearsmi_protect_check(struct flash_bank *bank)
 700 {
 701         /* Nothing to do. Protection is only handled in SW. */
 702         return ERROR_OK;
 703 }
 704
 705 static int get_spearsmi_info(struct flash_bank *bank, char *buf, int buf_size)
 706 {
 707         struct spearsmi_flash_bank *spearsmi_info = bank->driver_priv;
 708         int printed;
 709
 710         if (!(spearsmi_info->probed))
 711         {
 712                 printed = snprintf(buf, buf_size,
 713                         "\nSPEAr SMI flash bank not probed yet\n");
 714                 return ERROR_OK;
 715         }
 716
 717         printed = snprintf(buf, buf_size, "\nSPEAr SMI flash information:\n"
 718                 "  Device \'%s\' (ID 0x%08x)\n",
 719                 spearsmi_info->dev->name, spearsmi_info->dev->device_id);
 720         buf += printed;
 721         buf_size -= printed;
 722
 723         return ERROR_OK;
 724 }
 725
 726 struct flash_driver spearsmi_flash = {
 727         .name = "spearsmi",
 728         .flash_bank_command = spearsmi_flash_bank_command,
 729         .erase = spearsmi_erase,
 730         .protect = spearsmi_protect,
 731         .write = spearsmi_write,
 732         .read = default_flash_read,
 733         .probe = spearsmi_probe,
 734         .auto_probe = spearsmi_auto_probe,
 735         .erase_check = default_flash_blank_check,
 736         .protect_check = spearsmi_protect_check,
 737         .info = get_spearsmi_info,
 738 };