1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
8 * Copyright (C) 2011 by Andreas Fritiofson *
9 * andreas.fritiofson@gmail.com *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
30 #include <helper/binarybuffer.h>
31 #include <target/algorithm.h>
32 #include <target/armv7m.h>
34 /* stm32x register locations */
36 #define FLASH_REG_BASE_B0 0x40022000
37 #define FLASH_REG_BASE_B1 0x40022040
39 #define STM32_FLASH_ACR 0x00
40 #define STM32_FLASH_KEYR 0x04
41 #define STM32_FLASH_OPTKEYR 0x08
42 #define STM32_FLASH_SR 0x0C
43 #define STM32_FLASH_CR 0x10
44 #define STM32_FLASH_AR 0x14
45 #define STM32_FLASH_OBR 0x1C
46 #define STM32_FLASH_WRPR 0x20
48 /* TODO: Check if code using these really should be hard coded to bank 0.
49 * There are valid cases, on dual flash devices the protection of the
50 * second bank is done on the bank0 reg's. */
51 #define STM32_FLASH_ACR_B0 0x40022000
52 #define STM32_FLASH_KEYR_B0 0x40022004
53 #define STM32_FLASH_OPTKEYR_B0 0x40022008
54 #define STM32_FLASH_SR_B0 0x4002200C
55 #define STM32_FLASH_CR_B0 0x40022010
56 #define STM32_FLASH_AR_B0 0x40022014
57 #define STM32_FLASH_OBR_B0 0x4002201C
58 #define STM32_FLASH_WRPR_B0 0x40022020
60 /* option byte location */
62 #define STM32_OB_RDP 0x1FFFF800
63 #define STM32_OB_USER 0x1FFFF802
64 #define STM32_OB_DATA0 0x1FFFF804
65 #define STM32_OB_DATA1 0x1FFFF806
66 #define STM32_OB_WRP0 0x1FFFF808
67 #define STM32_OB_WRP1 0x1FFFF80A
68 #define STM32_OB_WRP2 0x1FFFF80C
69 #define STM32_OB_WRP3 0x1FFFF80E
71 /* FLASH_CR register bits */
73 #define FLASH_PG (1 << 0)
74 #define FLASH_PER (1 << 1)
75 #define FLASH_MER (1 << 2)
76 #define FLASH_OPTPG (1 << 4)
77 #define FLASH_OPTER (1 << 5)
78 #define FLASH_STRT (1 << 6)
79 #define FLASH_LOCK (1 << 7)
80 #define FLASH_OPTWRE (1 << 9)
82 /* FLASH_SR register bits */
84 #define FLASH_BSY (1 << 0)
85 #define FLASH_PGERR (1 << 2)
86 #define FLASH_WRPRTERR (1 << 4)
87 #define FLASH_EOP (1 << 5)
89 /* STM32_FLASH_OBR bit definitions (reading) */
94 #define OPT_RDRSTSTOP 3
95 #define OPT_RDRSTSTDBY 4
96 #define OPT_BFB2 5 /* dual flash bank only */
98 /* register unlock keys */
100 #define KEY1 0x45670123
101 #define KEY2 0xCDEF89AB
105 #define FLASH_WRITE_TIMEOUT 10
106 #define FLASH_ERASE_TIMEOUT 100
108 struct stm32x_options {
110 uint16_t user_options;
112 uint16_t protection[4];
115 struct stm32x_flash_bank {
116 struct stm32x_options option_bytes;
121 /* used to access dual flash bank stm32xl */
122 uint32_t register_base;
123 uint16_t default_rdp;
124 int user_data_offset;
126 uint32_t user_bank_size;
129 static int stm32x_mass_erase(struct flash_bank *bank);
130 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id);
131 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
132 uint32_t offset, uint32_t count);
134 /* flash bank stm32x <base> <size> 0 0 <target#>
136 FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
138 struct stm32x_flash_bank *stm32x_info;
141 return ERROR_COMMAND_SYNTAX_ERROR;
143 stm32x_info = malloc(sizeof(struct stm32x_flash_bank));
145 bank->driver_priv = stm32x_info;
146 stm32x_info->probed = 0;
147 stm32x_info->has_dual_banks = false;
148 stm32x_info->register_base = FLASH_REG_BASE_B0;
149 stm32x_info->user_bank_size = bank->size;
154 static inline int stm32x_get_flash_reg(struct flash_bank *bank, uint32_t reg)
156 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
157 return reg + stm32x_info->register_base;
160 static inline int stm32x_get_flash_status(struct flash_bank *bank, uint32_t *status)
162 struct target *target = bank->target;
163 return target_read_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), status);
166 static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
168 struct target *target = bank->target;
170 int retval = ERROR_OK;
172 /* wait for busy to clear */
174 retval = stm32x_get_flash_status(bank, &status);
175 if (retval != ERROR_OK)
177 LOG_DEBUG("status: 0x%" PRIx32 "", status);
178 if ((status & FLASH_BSY) == 0)
180 if (timeout-- <= 0) {
181 LOG_ERROR("timed out waiting for flash");
187 if (status & FLASH_WRPRTERR) {
188 LOG_ERROR("stm32x device protected");
192 if (status & FLASH_PGERR) {
193 LOG_ERROR("stm32x device programming failed");
197 /* Clear but report errors */
198 if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
199 /* If this operation fails, we ignore it and report the original
202 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR),
203 FLASH_WRPRTERR | FLASH_PGERR);
208 static int stm32x_check_operation_supported(struct flash_bank *bank)
210 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
212 /* if we have a dual flash bank device then
213 * we need to perform option byte stuff on bank0 only */
214 if (stm32x_info->register_base != FLASH_REG_BASE_B0) {
215 LOG_ERROR("Option Byte Operation's must use bank0");
216 return ERROR_FLASH_OPERATION_FAILED;
222 static int stm32x_read_options(struct flash_bank *bank)
225 struct stm32x_flash_bank *stm32x_info = NULL;
226 struct target *target = bank->target;
228 stm32x_info = bank->driver_priv;
230 /* read current option bytes */
231 int retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optiondata);
232 if (retval != ERROR_OK)
235 stm32x_info->option_bytes.user_options = (optiondata >> stm32x_info->option_offset >> 2) & 0xffff;
236 stm32x_info->option_bytes.user_data = (optiondata >> stm32x_info->user_data_offset) & 0xffff;
237 stm32x_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
239 if (optiondata & (1 << OPT_READOUT))
240 LOG_INFO("Device Security Bit Set");
242 /* each bit refers to a 4bank protection */
243 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &optiondata);
244 if (retval != ERROR_OK)
247 stm32x_info->option_bytes.protection[0] = (uint16_t)optiondata;
248 stm32x_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
249 stm32x_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
250 stm32x_info->option_bytes.protection[3] = (uint16_t)(optiondata >> 24);
255 static int stm32x_erase_options(struct flash_bank *bank)
257 struct stm32x_flash_bank *stm32x_info = NULL;
258 struct target *target = bank->target;
260 stm32x_info = bank->driver_priv;
262 /* read current options */
263 stm32x_read_options(bank);
265 /* unlock flash registers */
266 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
267 if (retval != ERROR_OK)
270 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
271 if (retval != ERROR_OK)
274 /* unlock option flash registers */
275 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
276 if (retval != ERROR_OK)
278 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
279 if (retval != ERROR_OK)
282 /* erase option bytes */
283 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_OPTWRE);
284 if (retval != ERROR_OK)
286 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
287 if (retval != ERROR_OK)
290 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
291 if (retval != ERROR_OK)
294 /* clear readout protection and complementary option bytes
295 * this will also force a device unlock if set */
296 stm32x_info->option_bytes.RDP = stm32x_info->default_rdp;
301 static int stm32x_write_options(struct flash_bank *bank)
303 struct stm32x_flash_bank *stm32x_info = NULL;
304 struct target *target = bank->target;
306 stm32x_info = bank->driver_priv;
308 /* unlock flash registers */
309 int retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY1);
310 if (retval != ERROR_OK)
312 retval = target_write_u32(target, STM32_FLASH_KEYR_B0, KEY2);
313 if (retval != ERROR_OK)
316 /* unlock option flash registers */
317 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY1);
318 if (retval != ERROR_OK)
320 retval = target_write_u32(target, STM32_FLASH_OPTKEYR_B0, KEY2);
321 if (retval != ERROR_OK)
324 /* program option bytes */
325 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_OPTPG | FLASH_OPTWRE);
326 if (retval != ERROR_OK)
329 uint8_t opt_bytes[16];
331 target_buffer_set_u16(target, opt_bytes, stm32x_info->option_bytes.RDP);
332 target_buffer_set_u16(target, opt_bytes + 2, stm32x_info->option_bytes.user_options);
333 target_buffer_set_u16(target, opt_bytes + 4, stm32x_info->option_bytes.user_data & 0xff);
334 target_buffer_set_u16(target, opt_bytes + 6, (stm32x_info->option_bytes.user_data >> 8) & 0xff);
335 target_buffer_set_u16(target, opt_bytes + 8, stm32x_info->option_bytes.protection[0]);
336 target_buffer_set_u16(target, opt_bytes + 10, stm32x_info->option_bytes.protection[1]);
337 target_buffer_set_u16(target, opt_bytes + 12, stm32x_info->option_bytes.protection[2]);
338 target_buffer_set_u16(target, opt_bytes + 14, stm32x_info->option_bytes.protection[3]);
340 uint32_t offset = STM32_OB_RDP - bank->base;
341 retval = stm32x_write_block(bank, opt_bytes, offset, sizeof(opt_bytes) / 2);
342 if (retval != ERROR_OK) {
343 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
344 LOG_ERROR("working area required to erase options bytes");
348 retval = target_write_u32(target, STM32_FLASH_CR_B0, FLASH_LOCK);
349 if (retval != ERROR_OK)
355 static int stm32x_protect_check(struct flash_bank *bank)
357 struct target *target = bank->target;
358 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
365 int retval = stm32x_check_operation_supported(bank);
366 if (ERROR_OK != retval)
369 /* medium density - each bit refers to a 4bank protection
370 * high density - each bit refers to a 2bank protection */
371 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
372 if (retval != ERROR_OK)
375 /* medium density - each protection bit is for 4 * 1K pages
376 * high density - each protection bit is for 2 * 2K pages */
377 num_bits = (bank->num_sectors / stm32x_info->ppage_size);
379 if (stm32x_info->ppage_size == 2) {
380 /* high density flash/connectivity line protection */
384 if (protection & (1 << 31))
387 /* bit 31 controls sector 62 - 255 protection for high density
388 * bit 31 controls sector 62 - 127 protection for connectivity line */
389 for (s = 62; s < bank->num_sectors; s++)
390 bank->sectors[s].is_protected = set;
392 if (bank->num_sectors > 61)
395 for (i = 0; i < num_bits; i++) {
398 if (protection & (1 << i))
401 for (s = 0; s < stm32x_info->ppage_size; s++)
402 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
405 /* low/medium density flash protection */
406 for (i = 0; i < num_bits; i++) {
409 if (protection & (1 << i))
412 for (s = 0; s < stm32x_info->ppage_size; s++)
413 bank->sectors[(i * stm32x_info->ppage_size) + s].is_protected = set;
420 static int stm32x_erase(struct flash_bank *bank, int first, int last)
422 struct target *target = bank->target;
425 if (bank->target->state != TARGET_HALTED) {
426 LOG_ERROR("Target not halted");
427 return ERROR_TARGET_NOT_HALTED;
430 if ((first == 0) && (last == (bank->num_sectors - 1)))
431 return stm32x_mass_erase(bank);
433 /* unlock flash registers */
434 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
435 if (retval != ERROR_OK)
437 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
438 if (retval != ERROR_OK)
441 for (i = first; i <= last; i++) {
442 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER);
443 if (retval != ERROR_OK)
445 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_AR),
446 bank->base + bank->sectors[i].offset);
447 if (retval != ERROR_OK)
449 retval = target_write_u32(target,
450 stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PER | FLASH_STRT);
451 if (retval != ERROR_OK)
454 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
455 if (retval != ERROR_OK)
458 bank->sectors[i].is_erased = 1;
461 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
462 if (retval != ERROR_OK)
468 static int stm32x_protect(struct flash_bank *bank, int set, int first, int last)
470 struct stm32x_flash_bank *stm32x_info = NULL;
471 struct target *target = bank->target;
472 uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
477 stm32x_info = bank->driver_priv;
479 if (target->state != TARGET_HALTED) {
480 LOG_ERROR("Target not halted");
481 return ERROR_TARGET_NOT_HALTED;
484 int retval = stm32x_check_operation_supported(bank);
485 if (ERROR_OK != retval)
488 if ((first % stm32x_info->ppage_size) != 0) {
489 LOG_WARNING("aligned start protect sector to a %d sector boundary",
490 stm32x_info->ppage_size);
491 first = first - (first % stm32x_info->ppage_size);
493 if (((last + 1) % stm32x_info->ppage_size) != 0) {
494 LOG_WARNING("aligned end protect sector to a %d sector boundary",
495 stm32x_info->ppage_size);
497 last = last - (last % stm32x_info->ppage_size);
501 /* medium density - each bit refers to a 4bank protection
502 * high density - each bit refers to a 2bank protection */
503 retval = target_read_u32(target, STM32_FLASH_WRPR_B0, &protection);
504 if (retval != ERROR_OK)
507 prot_reg[0] = (uint16_t)protection;
508 prot_reg[1] = (uint16_t)(protection >> 8);
509 prot_reg[2] = (uint16_t)(protection >> 16);
510 prot_reg[3] = (uint16_t)(protection >> 24);
512 if (stm32x_info->ppage_size == 2) {
513 /* high density flash */
515 /* bit 7 controls sector 62 - 255 protection */
518 prot_reg[3] &= ~(1 << 7);
520 prot_reg[3] |= (1 << 7);
528 for (i = first; i <= last; i++) {
529 reg = (i / stm32x_info->ppage_size) / 8;
530 bit = (i / stm32x_info->ppage_size) - (reg * 8);
533 prot_reg[reg] &= ~(1 << bit);
535 prot_reg[reg] |= (1 << bit);
538 /* medium density flash */
539 for (i = first; i <= last; i++) {
540 reg = (i / stm32x_info->ppage_size) / 8;
541 bit = (i / stm32x_info->ppage_size) - (reg * 8);
544 prot_reg[reg] &= ~(1 << bit);
546 prot_reg[reg] |= (1 << bit);
550 status = stm32x_erase_options(bank);
551 if (status != ERROR_OK)
554 stm32x_info->option_bytes.protection[0] = prot_reg[0];
555 stm32x_info->option_bytes.protection[1] = prot_reg[1];
556 stm32x_info->option_bytes.protection[2] = prot_reg[2];
557 stm32x_info->option_bytes.protection[3] = prot_reg[3];
559 return stm32x_write_options(bank);
562 static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
563 uint32_t offset, uint32_t count)
565 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
566 struct target *target = bank->target;
567 uint32_t buffer_size = 16384;
568 struct working_area *write_algorithm;
569 struct working_area *source;
570 uint32_t address = bank->base + offset;
571 struct reg_param reg_params[5];
572 struct armv7m_algorithm armv7m_info;
573 int retval = ERROR_OK;
575 /* see contrib/loaders/flash/stm32f1x.S for src */
577 static const uint8_t stm32x_flash_write_code[] = {
578 /* #define STM32_FLASH_SR_OFFSET 0x0C */
580 0x16, 0x68, /* ldr r6, [r2, #0] */
581 0x00, 0x2e, /* cmp r6, #0 */
582 0x18, 0xd0, /* beq exit */
583 0x55, 0x68, /* ldr r5, [r2, #4] */
584 0xb5, 0x42, /* cmp r5, r6 */
585 0xf9, 0xd0, /* beq wait_fifo */
586 0x2e, 0x88, /* ldrh r6, [r5, #0] */
587 0x26, 0x80, /* strh r6, [r4, #0] */
588 0x02, 0x35, /* adds r5, #2 */
589 0x02, 0x34, /* adds r4, #2 */
591 0xc6, 0x68, /* ldr r6, [r0, #STM32_FLASH_SR_OFFSET] */
592 0x01, 0x27, /* movs r7, #1 */
593 0x3e, 0x42, /* tst r6, r7 */
594 0xfb, 0xd1, /* bne busy */
595 0x14, 0x27, /* movs r7, #0x14 */
596 0x3e, 0x42, /* tst r6, r7 */
597 0x08, 0xd1, /* bne error */
598 0x9d, 0x42, /* cmp r5, r3 */
599 0x01, 0xd3, /* bcc no_wrap */
600 0x15, 0x46, /* mov r5, r2 */
601 0x08, 0x35, /* adds r5, #8 */
603 0x55, 0x60, /* str r5, [r2, #4] */
604 0x01, 0x39, /* subs r1, r1, #1 */
605 0x00, 0x29, /* cmp r1, #0 */
606 0x02, 0xd0, /* beq exit */
607 0xe5, 0xe7, /* b wait_fifo */
609 0x00, 0x20, /* movs r0, #0 */
610 0x50, 0x60, /* str r0, [r2, #4] */
612 0x30, 0x46, /* mov r0, r6 */
613 0x00, 0xbe, /* bkpt #0 */
616 /* flash write code */
617 if (target_alloc_working_area(target, sizeof(stm32x_flash_write_code),
618 &write_algorithm) != ERROR_OK) {
619 LOG_WARNING("no working area available, can't do block memory writes");
620 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
623 retval = target_write_buffer(target, write_algorithm->address,
624 sizeof(stm32x_flash_write_code), stm32x_flash_write_code);
625 if (retval != ERROR_OK)
629 while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
631 buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
632 if (buffer_size <= 256) {
633 /* we already allocated the writing code, but failed to get a
634 * buffer, free the algorithm */
635 target_free_working_area(target, write_algorithm);
637 LOG_WARNING("no large enough working area available, can't do block memory writes");
638 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
642 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
643 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (halfword-16bit) */
644 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
645 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
646 init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
648 buf_set_u32(reg_params[0].value, 0, 32, stm32x_info->register_base);
649 buf_set_u32(reg_params[1].value, 0, 32, count);
650 buf_set_u32(reg_params[2].value, 0, 32, source->address);
651 buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
652 buf_set_u32(reg_params[4].value, 0, 32, address);
654 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
655 armv7m_info.core_mode = ARM_MODE_THREAD;
657 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
660 source->address, source->size,
661 write_algorithm->address, 0,
664 if (retval == ERROR_FLASH_OPERATION_FAILED) {
665 LOG_ERROR("flash write failed at address 0x%"PRIx32,
666 buf_get_u32(reg_params[4].value, 0, 32));
668 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_PGERR) {
669 LOG_ERROR("flash memory not erased before writing");
670 /* Clear but report errors */
671 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_PGERR);
674 if (buf_get_u32(reg_params[0].value, 0, 32) & FLASH_WRPRTERR) {
675 LOG_ERROR("flash memory write protected");
676 /* Clear but report errors */
677 target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_SR), FLASH_WRPRTERR);
681 target_free_working_area(target, source);
682 target_free_working_area(target, write_algorithm);
684 destroy_reg_param(®_params[0]);
685 destroy_reg_param(®_params[1]);
686 destroy_reg_param(®_params[2]);
687 destroy_reg_param(®_params[3]);
688 destroy_reg_param(®_params[4]);
693 static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
694 uint32_t offset, uint32_t count)
696 struct target *target = bank->target;
697 uint8_t *new_buffer = NULL;
699 if (bank->target->state != TARGET_HALTED) {
700 LOG_ERROR("Target not halted");
701 return ERROR_TARGET_NOT_HALTED;
705 LOG_ERROR("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
706 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
709 /* If there's an odd number of bytes, the data has to be padded. Duplicate
710 * the buffer and use the normal code path with a single block write since
711 * it's probably cheaper than to special case the last odd write using
712 * discrete accesses. */
714 new_buffer = malloc(count + 1);
715 if (new_buffer == NULL) {
716 LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
719 LOG_INFO("odd number of bytes to write, padding with 0xff");
720 buffer = memcpy(new_buffer, buffer, count);
721 new_buffer[count++] = 0xff;
724 uint32_t words_remaining = count / 2;
727 /* unlock flash registers */
728 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
729 if (retval != ERROR_OK)
731 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
732 if (retval != ERROR_OK)
735 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_PG);
736 if (retval != ERROR_OK)
739 /* try using a block write */
740 retval = stm32x_write_block(bank, buffer, offset, words_remaining);
742 if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
743 /* if block write failed (no sufficient working area),
744 * we use normal (slow) single halfword accesses */
745 LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
747 while (words_remaining > 0) {
749 memcpy(&value, buffer, sizeof(uint16_t));
751 retval = target_write_u16(target, bank->base + offset, value);
752 if (retval != ERROR_OK)
753 goto reset_pg_and_lock;
755 retval = stm32x_wait_status_busy(bank, 5);
756 if (retval != ERROR_OK)
757 goto reset_pg_and_lock;
766 retval2 = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
767 if (retval == ERROR_OK)
777 static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
779 /* This check the device CPUID core register to detect
780 * the M0 from the M3 devices. */
782 struct target *target = bank->target;
783 uint32_t cpuid, device_id_register = 0;
785 /* Get the CPUID from the ARM Core
786 * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0432c/DDI0432C_cortex_m0_r0p0_trm.pdf 4.2.1 */
787 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
788 if (retval != ERROR_OK)
791 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
792 /* 0xC20 is M0 devices */
793 device_id_register = 0x40015800;
794 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
795 /* 0xC23 is M3 devices */
796 device_id_register = 0xE0042000;
797 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
798 /* 0xC24 is M4 devices */
799 device_id_register = 0xE0042000;
801 LOG_ERROR("Cannot identify target as a stm32x");
805 /* read stm32 device id register */
806 retval = target_read_u32(target, device_id_register, device_id);
807 if (retval != ERROR_OK)
813 static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
815 struct target *target = bank->target;
816 uint32_t cpuid, flash_size_reg;
818 int retval = target_read_u32(target, 0xE000ED00, &cpuid);
819 if (retval != ERROR_OK)
822 if (((cpuid >> 4) & 0xFFF) == 0xC20) {
823 /* 0xC20 is M0 devices */
824 flash_size_reg = 0x1FFFF7CC;
825 } else if (((cpuid >> 4) & 0xFFF) == 0xC23) {
826 /* 0xC23 is M3 devices */
827 flash_size_reg = 0x1FFFF7E0;
828 } else if (((cpuid >> 4) & 0xFFF) == 0xC24) {
829 /* 0xC24 is M4 devices */
830 flash_size_reg = 0x1FFFF7CC;
832 LOG_ERROR("Cannot identify target as a stm32x");
836 retval = target_read_u16(target, flash_size_reg, flash_size_in_kb);
837 if (retval != ERROR_OK)
843 static int stm32x_probe(struct flash_bank *bank)
845 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
847 uint16_t flash_size_in_kb;
848 uint16_t max_flash_size_in_kb;
851 uint32_t base_address = 0x08000000;
853 stm32x_info->probed = 0;
854 stm32x_info->register_base = FLASH_REG_BASE_B0;
855 stm32x_info->user_data_offset = 10;
856 stm32x_info->option_offset = 0;
858 /* default factory protection level */
859 stm32x_info->default_rdp = 0x5AA5;
861 /* read stm32 device id register */
862 int retval = stm32x_get_device_id(bank, &device_id);
863 if (retval != ERROR_OK)
866 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
868 /* set page size, protection granularity and max flash size depending on family */
869 switch (device_id & 0xfff) {
870 case 0x410: /* medium density */
872 stm32x_info->ppage_size = 4;
873 max_flash_size_in_kb = 128;
875 case 0x412: /* low density */
877 stm32x_info->ppage_size = 4;
878 max_flash_size_in_kb = 32;
880 case 0x414: /* high density */
882 stm32x_info->ppage_size = 2;
883 max_flash_size_in_kb = 512;
885 case 0x418: /* connectivity line density */
887 stm32x_info->ppage_size = 2;
888 max_flash_size_in_kb = 256;
890 case 0x420: /* value line density */
892 stm32x_info->ppage_size = 4;
893 max_flash_size_in_kb = 128;
895 case 0x422: /* stm32f302/3xb/c */
897 stm32x_info->ppage_size = 2;
898 max_flash_size_in_kb = 256;
899 stm32x_info->user_data_offset = 16;
900 stm32x_info->option_offset = 6;
901 stm32x_info->default_rdp = 0x55AA;
903 case 0x446: /* stm32f303xD/E */
905 stm32x_info->ppage_size = 2;
906 max_flash_size_in_kb = 512;
907 stm32x_info->user_data_offset = 16;
908 stm32x_info->option_offset = 6;
909 stm32x_info->default_rdp = 0x55AA;
911 case 0x428: /* value line High density */
913 stm32x_info->ppage_size = 4;
914 max_flash_size_in_kb = 128;
916 case 0x430: /* xl line density (dual flash banks) */
918 stm32x_info->ppage_size = 2;
919 max_flash_size_in_kb = 1024;
920 stm32x_info->has_dual_banks = true;
922 case 0x432: /* stm32f37x */
924 stm32x_info->ppage_size = 2;
925 max_flash_size_in_kb = 256;
926 stm32x_info->user_data_offset = 16;
927 stm32x_info->option_offset = 6;
928 stm32x_info->default_rdp = 0x55AA;
930 case 0x438: /* stm32f33x */
931 case 0x439: /* stm32f302x6/8 */
933 stm32x_info->ppage_size = 2;
934 max_flash_size_in_kb = 64;
935 stm32x_info->user_data_offset = 16;
936 stm32x_info->option_offset = 6;
937 stm32x_info->default_rdp = 0x55AA;
939 case 0x440: /* stm32f05x */
940 case 0x444: /* stm32f03x */
941 case 0x445: /* stm32f04x */
943 stm32x_info->ppage_size = 4;
944 max_flash_size_in_kb = 64;
945 stm32x_info->user_data_offset = 16;
946 stm32x_info->option_offset = 6;
947 stm32x_info->default_rdp = 0x55AA;
949 case 0x448: /* stm32f07x */
950 case 0x442: /* stm32f09x */
952 stm32x_info->ppage_size = 4;
953 max_flash_size_in_kb = 256;
954 stm32x_info->user_data_offset = 16;
955 stm32x_info->option_offset = 6;
956 stm32x_info->default_rdp = 0x55AA;
959 LOG_WARNING("Cannot identify target as a STM32 family.");
963 /* get flash size from target. */
964 retval = stm32x_get_flash_size(bank, &flash_size_in_kb);
966 /* failed reading flash size or flash size invalid (early silicon),
967 * default to max target family */
968 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
969 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
970 max_flash_size_in_kb);
971 flash_size_in_kb = max_flash_size_in_kb;
974 if (stm32x_info->has_dual_banks) {
975 /* split reported size into matching bank */
976 if (bank->base != 0x08080000) {
977 /* bank 0 will be fixed 512k */
978 flash_size_in_kb = 512;
980 flash_size_in_kb -= 512;
981 /* bank1 also uses a register offset */
982 stm32x_info->register_base = FLASH_REG_BASE_B1;
983 base_address = 0x08080000;
987 /* if the user sets the size manually then ignore the probed value
988 * this allows us to work around devices that have a invalid flash size register value */
989 if (stm32x_info->user_bank_size) {
990 LOG_INFO("ignoring flash probed value, using configured bank size");
991 flash_size_in_kb = stm32x_info->user_bank_size / 1024;
994 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
996 /* did we assign flash size? */
997 assert(flash_size_in_kb != 0xffff);
999 /* calculate numbers of pages */
1000 int num_pages = flash_size_in_kb * 1024 / page_size;
1002 /* check that calculation result makes sense */
1003 assert(num_pages > 0);
1005 if (bank->sectors) {
1006 free(bank->sectors);
1007 bank->sectors = NULL;
1010 bank->base = base_address;
1011 bank->size = (num_pages * page_size);
1012 bank->num_sectors = num_pages;
1013 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
1015 for (i = 0; i < num_pages; i++) {
1016 bank->sectors[i].offset = i * page_size;
1017 bank->sectors[i].size = page_size;
1018 bank->sectors[i].is_erased = -1;
1019 bank->sectors[i].is_protected = 1;
1022 stm32x_info->probed = 1;
1027 static int stm32x_auto_probe(struct flash_bank *bank)
1029 struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
1030 if (stm32x_info->probed)
1032 return stm32x_probe(bank);
1036 COMMAND_HANDLER(stm32x_handle_part_id_command)
1042 static const char *get_stm32f0_revision(uint16_t rev_id)
1044 const char *rev_str = NULL;
1057 static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
1059 uint32_t dbgmcu_idcode;
1061 /* read stm32 device id register */
1062 int retval = stm32x_get_device_id(bank, &dbgmcu_idcode);
1063 if (retval != ERROR_OK)
1066 uint16_t device_id = dbgmcu_idcode & 0xfff;
1067 uint16_t rev_id = dbgmcu_idcode >> 16;
1068 const char *device_str;
1069 const char *rev_str = NULL;
1071 switch (device_id) {
1073 device_str = "STM32F10x (Medium Density)";
1095 device_str = "STM32F10x (Low Density)";
1105 device_str = "STM32F10x (High Density)";
1123 device_str = "STM32F10x (Connectivity)";
1137 device_str = "STM32F100 (Low/Medium Density)";
1151 device_str = "STM32F302xB/C";
1173 device_str = "STM32F100 (High Density)";
1187 device_str = "STM32F10x (XL Density)";
1197 device_str = "STM32F37x";
1211 device_str = "STM32F33x";
1221 device_str = "STM32F302x6/8";
1235 device_str = "STM32F03x";
1236 rev_str = get_stm32f0_revision(rev_id);
1240 device_str = "STM32F05x";
1241 rev_str = get_stm32f0_revision(rev_id);
1245 device_str = "STM32F04x";
1246 rev_str = get_stm32f0_revision(rev_id);
1250 device_str = "STM32F303xD/E";
1259 device_str = "STM32F07x";
1260 rev_str = get_stm32f0_revision(rev_id);
1264 device_str = "STM32F09x";
1265 rev_str = get_stm32f0_revision(rev_id);
1269 snprintf(buf, buf_size, "Cannot identify target as a STM32F0/1/3\n");
1273 if (rev_str != NULL)
1274 snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
1276 snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
1281 COMMAND_HANDLER(stm32x_handle_lock_command)
1283 struct target *target = NULL;
1284 struct stm32x_flash_bank *stm32x_info = NULL;
1287 return ERROR_COMMAND_SYNTAX_ERROR;
1289 struct flash_bank *bank;
1290 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1291 if (ERROR_OK != retval)
1294 stm32x_info = bank->driver_priv;
1296 target = bank->target;
1298 if (target->state != TARGET_HALTED) {
1299 LOG_ERROR("Target not halted");
1300 return ERROR_TARGET_NOT_HALTED;
1303 retval = stm32x_check_operation_supported(bank);
1304 if (ERROR_OK != retval)
1307 if (stm32x_erase_options(bank) != ERROR_OK) {
1308 command_print(CMD_CTX, "stm32x failed to erase options");
1312 /* set readout protection */
1313 stm32x_info->option_bytes.RDP = 0;
1315 if (stm32x_write_options(bank) != ERROR_OK) {
1316 command_print(CMD_CTX, "stm32x failed to lock device");
1320 command_print(CMD_CTX, "stm32x locked");
1325 COMMAND_HANDLER(stm32x_handle_unlock_command)
1327 struct target *target = NULL;
1330 return ERROR_COMMAND_SYNTAX_ERROR;
1332 struct flash_bank *bank;
1333 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1334 if (ERROR_OK != retval)
1337 target = bank->target;
1339 if (target->state != TARGET_HALTED) {
1340 LOG_ERROR("Target not halted");
1341 return ERROR_TARGET_NOT_HALTED;
1344 retval = stm32x_check_operation_supported(bank);
1345 if (ERROR_OK != retval)
1348 if (stm32x_erase_options(bank) != ERROR_OK) {
1349 command_print(CMD_CTX, "stm32x failed to unlock device");
1353 if (stm32x_write_options(bank) != ERROR_OK) {
1354 command_print(CMD_CTX, "stm32x failed to lock device");
1358 command_print(CMD_CTX, "stm32x unlocked.\n"
1359 "INFO: a reset or power cycle is required "
1360 "for the new settings to take effect.");
1365 COMMAND_HANDLER(stm32x_handle_options_read_command)
1367 uint32_t optionbyte;
1368 struct target *target = NULL;
1369 struct stm32x_flash_bank *stm32x_info = NULL;
1372 return ERROR_COMMAND_SYNTAX_ERROR;
1374 struct flash_bank *bank;
1375 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1376 if (ERROR_OK != retval)
1379 stm32x_info = bank->driver_priv;
1381 target = bank->target;
1383 if (target->state != TARGET_HALTED) {
1384 LOG_ERROR("Target not halted");
1385 return ERROR_TARGET_NOT_HALTED;
1388 retval = stm32x_check_operation_supported(bank);
1389 if (ERROR_OK != retval)
1392 retval = target_read_u32(target, STM32_FLASH_OBR_B0, &optionbyte);
1393 if (retval != ERROR_OK)
1395 command_print(CMD_CTX, "Option Byte: 0x%" PRIx32 "", optionbyte);
1397 int user_data = optionbyte;
1399 if (optionbyte >> OPT_ERROR & 1)
1400 command_print(CMD_CTX, "Option Byte Complement Error");
1402 if (optionbyte >> OPT_READOUT & 1)
1403 command_print(CMD_CTX, "Readout Protection On");
1405 command_print(CMD_CTX, "Readout Protection Off");
1407 /* user option bytes are offset depending on variant */
1408 optionbyte >>= stm32x_info->option_offset;
1410 if (optionbyte >> OPT_RDWDGSW & 1)
1411 command_print(CMD_CTX, "Software Watchdog");
1413 command_print(CMD_CTX, "Hardware Watchdog");
1415 if (optionbyte >> OPT_RDRSTSTOP & 1)
1416 command_print(CMD_CTX, "Stop: No reset generated");
1418 command_print(CMD_CTX, "Stop: Reset generated");
1420 if (optionbyte >> OPT_RDRSTSTDBY & 1)
1421 command_print(CMD_CTX, "Standby: No reset generated");
1423 command_print(CMD_CTX, "Standby: Reset generated");
1425 if (stm32x_info->has_dual_banks) {
1426 if (optionbyte >> OPT_BFB2 & 1)
1427 command_print(CMD_CTX, "Boot: Bank 0");
1429 command_print(CMD_CTX, "Boot: Bank 1");
1432 command_print(CMD_CTX, "User Option0: 0x%02" PRIx8,
1433 (uint8_t)((user_data >> stm32x_info->user_data_offset) & 0xff));
1434 command_print(CMD_CTX, "User Option1: 0x%02" PRIx8,
1435 (uint8_t)((user_data >> (stm32x_info->user_data_offset + 8)) & 0xff));
1440 COMMAND_HANDLER(stm32x_handle_options_write_command)
1442 struct target *target = NULL;
1443 struct stm32x_flash_bank *stm32x_info = NULL;
1444 uint16_t optionbyte;
1447 return ERROR_COMMAND_SYNTAX_ERROR;
1449 struct flash_bank *bank;
1450 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1451 if (ERROR_OK != retval)
1454 stm32x_info = bank->driver_priv;
1456 target = bank->target;
1458 if (target->state != TARGET_HALTED) {
1459 LOG_ERROR("Target not halted");
1460 return ERROR_TARGET_NOT_HALTED;
1463 retval = stm32x_check_operation_supported(bank);
1464 if (ERROR_OK != retval)
1467 retval = stm32x_read_options(bank);
1468 if (ERROR_OK != retval)
1471 /* start with current options */
1472 optionbyte = stm32x_info->option_bytes.user_options;
1474 /* skip over flash bank */
1479 if (strcmp("SWWDG", CMD_ARGV[0]) == 0)
1480 optionbyte |= (1 << 0);
1481 else if (strcmp("HWWDG", CMD_ARGV[0]) == 0)
1482 optionbyte &= ~(1 << 0);
1483 else if (strcmp("NORSTSTOP", CMD_ARGV[0]) == 0)
1484 optionbyte |= (1 << 1);
1485 else if (strcmp("RSTSTOP", CMD_ARGV[0]) == 0)
1486 optionbyte &= ~(1 << 1);
1487 else if (strcmp("NORSTSTNDBY", CMD_ARGV[0]) == 0)
1488 optionbyte |= (1 << 2);
1489 else if (strcmp("RSTSTNDBY", CMD_ARGV[0]) == 0)
1490 optionbyte &= ~(1 << 2);
1491 else if (stm32x_info->has_dual_banks) {
1492 if (strcmp("BOOT0", CMD_ARGV[0]) == 0)
1493 optionbyte |= (1 << 3);
1494 else if (strcmp("BOOT1", CMD_ARGV[0]) == 0)
1495 optionbyte &= ~(1 << 3);
1497 return ERROR_COMMAND_SYNTAX_ERROR;
1499 return ERROR_COMMAND_SYNTAX_ERROR;
1504 if (stm32x_erase_options(bank) != ERROR_OK) {
1505 command_print(CMD_CTX, "stm32x failed to erase options");
1509 stm32x_info->option_bytes.user_options = optionbyte;
1511 if (stm32x_write_options(bank) != ERROR_OK) {
1512 command_print(CMD_CTX, "stm32x failed to write options");
1516 command_print(CMD_CTX, "stm32x write options complete.\n"
1517 "INFO: a reset or power cycle is required "
1518 "for the new settings to take effect.");
1523 static int stm32x_mass_erase(struct flash_bank *bank)
1525 struct target *target = bank->target;
1527 if (target->state != TARGET_HALTED) {
1528 LOG_ERROR("Target not halted");
1529 return ERROR_TARGET_NOT_HALTED;
1532 /* unlock option flash registers */
1533 int retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY1);
1534 if (retval != ERROR_OK)
1536 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_KEYR), KEY2);
1537 if (retval != ERROR_OK)
1540 /* mass erase flash memory */
1541 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_MER);
1542 if (retval != ERROR_OK)
1544 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
1545 FLASH_MER | FLASH_STRT);
1546 if (retval != ERROR_OK)
1549 retval = stm32x_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
1550 if (retval != ERROR_OK)
1553 retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
1554 if (retval != ERROR_OK)
1560 COMMAND_HANDLER(stm32x_handle_mass_erase_command)
1565 return ERROR_COMMAND_SYNTAX_ERROR;
1567 struct flash_bank *bank;
1568 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
1569 if (ERROR_OK != retval)
1572 retval = stm32x_mass_erase(bank);
1573 if (retval == ERROR_OK) {
1574 /* set all sectors as erased */
1575 for (i = 0; i < bank->num_sectors; i++)
1576 bank->sectors[i].is_erased = 1;
1578 command_print(CMD_CTX, "stm32x mass erase complete");
1580 command_print(CMD_CTX, "stm32x mass erase failed");
1585 static const struct command_registration stm32x_exec_command_handlers[] = {
1588 .handler = stm32x_handle_lock_command,
1589 .mode = COMMAND_EXEC,
1591 .help = "Lock entire flash device.",
1595 .handler = stm32x_handle_unlock_command,
1596 .mode = COMMAND_EXEC,
1598 .help = "Unlock entire protected flash device.",
1601 .name = "mass_erase",
1602 .handler = stm32x_handle_mass_erase_command,
1603 .mode = COMMAND_EXEC,
1605 .help = "Erase entire flash device.",
1608 .name = "options_read",
1609 .handler = stm32x_handle_options_read_command,
1610 .mode = COMMAND_EXEC,
1612 .help = "Read and display device option byte.",
1615 .name = "options_write",
1616 .handler = stm32x_handle_options_write_command,
1617 .mode = COMMAND_EXEC,
1618 .usage = "bank_id ('SWWDG'|'HWWDG') "
1619 "('RSTSTNDBY'|'NORSTSTNDBY') "
1620 "('RSTSTOP'|'NORSTSTOP')",
1621 .help = "Replace bits in device option byte.",
1623 COMMAND_REGISTRATION_DONE
1626 static const struct command_registration stm32x_command_handlers[] = {
1629 .mode = COMMAND_ANY,
1630 .help = "stm32f1x flash command group",
1632 .chain = stm32x_exec_command_handlers,
1634 COMMAND_REGISTRATION_DONE
1637 struct flash_driver stm32f1x_flash = {
1639 .commands = stm32x_command_handlers,
1640 .flash_bank_command = stm32x_flash_bank_command,
1641 .erase = stm32x_erase,
1642 .protect = stm32x_protect,
1643 .write = stm32x_write,
1644 .read = default_flash_read,
1645 .probe = stm32x_probe,
1646 .auto_probe = stm32x_auto_probe,
1647 .erase_check = default_flash_blank_check,
1648 .protect_check = stm32x_protect_check,
1649 .info = get_stm32x_info,
1650 .free_driver_priv = default_flash_free_driver_priv,