1 /***************************************************************************
2 * Copyright (C) 2015 by Uwe Bonnes *
3 * bon@elektron.ikp.physik.tu-darmstadt.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
24 #include <helper/binarybuffer.h>
25 #include <target/algorithm.h>
26 #include <target/armv7m.h>
28 /* STM32L4xxx series for reference.
30 * RM0351 (STM32L4x5/STM32L4x6)
31 * http://www.st.com/resource/en/reference_manual/dm00083560.pdf
33 * RM0394 (STM32L43x/44x/45x/46x)
34 * http://www.st.com/resource/en/reference_manual/dm00151940.pdf
36 * STM32L476RG Datasheet (for erase timing)
37 * http://www.st.com/resource/en/datasheet/stm32l476rg.pdf
39 * The RM0351 devices have normally two banks, but on 512 and 256 kiB devices
40 * an option byte is available to map all sectors to the first bank.
41 * Both STM32 banks are treated as one OpenOCD bank, as other STM32 devices
44 * RM0394 devices have a single bank only.
48 /* Erase time can be as high as 25ms, 10x this and assume it's toast... */
50 #define FLASH_ERASE_TIMEOUT 250
52 #define STM32_FLASH_BASE 0x40022000
53 #define STM32_FLASH_ACR 0x40022000
54 #define STM32_FLASH_KEYR 0x40022008
55 #define STM32_FLASH_OPTKEYR 0x4002200c
56 #define STM32_FLASH_SR 0x40022010
57 #define STM32_FLASH_CR 0x40022014
58 #define STM32_FLASH_OPTR 0x40022020
59 #define STM32_FLASH_WRP1AR 0x4002202c
60 #define STM32_FLASH_WRP1BR 0x40022030
61 #define STM32_FLASH_WRP2AR 0x4002204c
62 #define STM32_FLASH_WRP2BR 0x40022050
64 /* FLASH_CR register bits */
66 #define FLASH_PG (1 << 0)
67 #define FLASH_PER (1 << 1)
68 #define FLASH_MER1 (1 << 2)
69 #define FLASH_PAGE_SHIFT 3
70 #define FLASH_CR_BKER (1 << 11)
71 #define FLASH_MER2 (1 << 15)
72 #define FLASH_STRT (1 << 16)
73 #define FLASH_OPTSTRT (1 << 17)
74 #define FLASH_EOPIE (1 << 24)
75 #define FLASH_ERRIE (1 << 25)
76 #define FLASH_OBLLAUNCH (1 << 27)
77 #define FLASH_OPTLOCK (1 << 30)
78 #define FLASH_LOCK (1 << 31)
80 /* FLASH_SR register bits */
82 #define FLASH_BSY (1 << 16)
83 /* Fast programming not used => related errors not used*/
84 #define FLASH_PGSERR (1 << 7) /* Programming sequence error */
85 #define FLASH_SIZERR (1 << 6) /* Size error */
86 #define FLASH_PGAERR (1 << 5) /* Programming alignment error */
87 #define FLASH_WRPERR (1 << 4) /* Write protection error */
88 #define FLASH_PROGERR (1 << 3) /* Programming error */
89 #define FLASH_OPERR (1 << 1) /* Operation error */
90 #define FLASH_EOP (1 << 0) /* End of operation */
92 #define FLASH_ERROR (FLASH_PGSERR | FLASH_PGSERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_OPERR)
94 /* STM32_FLASH_OBR bit definitions (reading) */
96 #define OPT_DUALBANK 21 /* dual flash bank only */
98 /* register unlock keys */
100 #define KEY1 0x45670123
101 #define KEY2 0xCDEF89AB
103 /* option register unlock key */
104 #define OPTKEY1 0x08192A3B
105 #define OPTKEY2 0x4C5D6E7F
107 #define RDP_LEVEL_0 0xAA
108 #define RDP_LEVEL_1 0xBB
109 #define RDP_LEVEL_2 0xCC
112 /* other registers */
113 #define DBGMCU_IDCODE 0xE0042000
114 #define FLASH_SIZE_REG 0x1FFF75E0
116 struct stm32l4_flash_bank {
117 uint16_t bank2_start;
121 /* flash bank stm32l4x <base> <size> 0 0 <target#>
123 FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
125 struct stm32l4_flash_bank *stm32l4_info;
128 return ERROR_COMMAND_SYNTAX_ERROR;
130 stm32l4_info = malloc(sizeof(struct stm32l4_flash_bank));
132 return ERROR_FAIL; /* Checkme: What better error to use?*/
133 bank->driver_priv = stm32l4_info;
135 stm32l4_info->probed = 0;
140 static inline int stm32l4_get_flash_reg(struct flash_bank *bank, uint32_t reg)
145 static inline int stm32l4_get_flash_status(struct flash_bank *bank, uint32_t *status)
147 struct target *target = bank->target;
148 return target_read_u32(
149 target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR), status);
152 static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
154 struct target *target = bank->target;
156 int retval = ERROR_OK;
158 /* wait for busy to clear */
160 retval = stm32l4_get_flash_status(bank, &status);
161 if (retval != ERROR_OK)
163 LOG_DEBUG("status: 0x%" PRIx32 "", status);
164 if ((status & FLASH_BSY) == 0)
166 if (timeout-- <= 0) {
167 LOG_ERROR("timed out waiting for flash");
174 if (status & FLASH_WRPERR) {
175 LOG_ERROR("stm32x device protected");
179 /* Clear but report errors */
180 if (status & FLASH_ERROR) {
181 if (retval == ERROR_OK)
183 /* If this operation fails, we ignore it and report the original
186 target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_SR),
187 status & FLASH_ERROR);
192 static int stm32l4_unlock_reg(struct target *target)
196 /* first check if not already unlocked
197 * otherwise writing on STM32_FLASH_KEYR will fail
199 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
200 if (retval != ERROR_OK)
203 if ((ctrl & FLASH_LOCK) == 0)
206 /* unlock flash registers */
207 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY1);
208 if (retval != ERROR_OK)
211 retval = target_write_u32(target, STM32_FLASH_KEYR, KEY2);
212 if (retval != ERROR_OK)
215 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
216 if (retval != ERROR_OK)
219 if (ctrl & FLASH_LOCK) {
220 LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
221 return ERROR_TARGET_FAILURE;
227 static int stm32l4_unlock_option_reg(struct target *target)
231 int retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
232 if (retval != ERROR_OK)
235 if ((ctrl & FLASH_OPTLOCK) == 0)
238 /* unlock option registers */
239 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY1);
240 if (retval != ERROR_OK)
243 retval = target_write_u32(target, STM32_FLASH_OPTKEYR, OPTKEY2);
244 if (retval != ERROR_OK)
247 retval = target_read_u32(target, STM32_FLASH_CR, &ctrl);
248 if (retval != ERROR_OK)
251 if (ctrl & FLASH_OPTLOCK) {
252 LOG_ERROR("options not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
253 return ERROR_TARGET_FAILURE;
259 static int stm32l4_read_option(struct flash_bank *bank, uint32_t address, uint32_t* value)
261 struct target *target = bank->target;
262 return target_read_u32(target, address, value);
265 static int stm32l4_write_option(struct flash_bank *bank, uint32_t address, uint32_t value, uint32_t mask)
267 struct target *target = bank->target;
270 int retval = target_read_u32(target, address, &optiondata);
271 if (retval != ERROR_OK)
274 retval = stm32l4_unlock_reg(target);
275 if (retval != ERROR_OK)
278 retval = stm32l4_unlock_option_reg(target);
279 if (retval != ERROR_OK)
282 optiondata = (optiondata & ~mask) | (value & mask);
284 retval = target_write_u32(target, address, optiondata);
285 if (retval != ERROR_OK)
288 retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OPTSTRT);
289 if (retval != ERROR_OK)
292 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
293 if (retval != ERROR_OK)
299 static int stm32l4_protect_check(struct flash_bank *bank)
301 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
302 uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
303 stm32l4_read_option(bank, STM32_FLASH_WRP1AR, &wrp1ar);
304 stm32l4_read_option(bank, STM32_FLASH_WRP1BR, &wrp1br);
305 stm32l4_read_option(bank, STM32_FLASH_WRP2AR, &wrp2ar);
306 stm32l4_read_option(bank, STM32_FLASH_WRP2BR, &wrp2br);
308 const uint8_t wrp1a_start = wrp1ar & 0xFF;
309 const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
310 const uint8_t wrp1b_start = wrp1br & 0xFF;
311 const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
312 const uint8_t wrp2a_start = wrp2ar & 0xFF;
313 const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
314 const uint8_t wrp2b_start = wrp2br & 0xFF;
315 const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
317 for (int i = 0; i < bank->num_sectors; i++) {
318 if (i < stm32l4_info->bank2_start) {
319 if (((i >= wrp1a_start) &&
321 ((i >= wrp1b_start) &&
323 bank->sectors[i].is_protected = 1;
325 bank->sectors[i].is_protected = 0;
328 snb = i - stm32l4_info->bank2_start + 256;
329 if (((snb >= wrp2a_start) &&
330 (snb <= wrp2a_end)) ||
331 ((snb >= wrp2b_start) &&
333 bank->sectors[i].is_protected = 1;
335 bank->sectors[i].is_protected = 0;
341 static int stm32l4_erase(struct flash_bank *bank, int first, int last)
343 struct target *target = bank->target;
346 assert(first < bank->num_sectors);
347 assert(last < bank->num_sectors);
349 if (bank->target->state != TARGET_HALTED) {
350 LOG_ERROR("Target not halted");
351 return ERROR_TARGET_NOT_HALTED;
355 retval = stm32l4_unlock_reg(target);
356 if (retval != ERROR_OK)
361 To erase a sector, follow the procedure below:
362 1. Check that no Flash memory operation is ongoing by
363 checking the BSY bit in the FLASH_SR register
364 2. Set the PER bit and select the page and bank
365 you wish to erase in the FLASH_CR register
366 3. Set the STRT bit in the FLASH_CR register
367 4. Wait for the BSY bit to be cleared
369 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
371 for (i = first; i <= last; i++) {
372 uint32_t erase_flags;
373 erase_flags = FLASH_PER | FLASH_STRT;
375 if (i >= stm32l4_info->bank2_start) {
377 snb = (i - stm32l4_info->bank2_start) + 256;
378 erase_flags |= snb << FLASH_PAGE_SHIFT | FLASH_CR_BKER;
380 erase_flags |= i << FLASH_PAGE_SHIFT;
381 retval = target_write_u32(target,
382 stm32l4_get_flash_reg(bank, STM32_FLASH_CR), erase_flags);
383 if (retval != ERROR_OK)
386 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
387 if (retval != ERROR_OK)
390 bank->sectors[i].is_erased = 1;
393 retval = target_write_u32(
394 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
395 if (retval != ERROR_OK)
401 static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last)
403 struct target *target = bank->target;
404 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
406 if (target->state != TARGET_HALTED) {
407 LOG_ERROR("Target not halted");
408 return ERROR_TARGET_NOT_HALTED;
413 uint32_t reg_value = 0xFF; /* Default to bank un-protected */
414 if (last >= stm32l4_info->bank2_start) {
416 uint8_t begin = first > stm32l4_info->bank2_start ? first : 0x00;
417 reg_value = ((last & 0xFF) << 16) | begin;
420 ret = stm32l4_write_option(bank, STM32_FLASH_WRP2AR, reg_value, 0xffffffff);
423 reg_value = 0xFF; /* Default to bank un-protected */
424 if (first < stm32l4_info->bank2_start) {
426 uint8_t end = last >= stm32l4_info->bank2_start ? 0xFF : last;
427 reg_value = (end << 16) | (first & 0xFF);
430 ret = stm32l4_write_option(bank, STM32_FLASH_WRP1AR, reg_value, 0xffffffff);
436 /* Count is in halfwords */
437 static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
438 uint32_t offset, uint32_t count)
440 struct target *target = bank->target;
441 uint32_t buffer_size = 16384;
442 struct working_area *write_algorithm;
443 struct working_area *source;
444 uint32_t address = bank->base + offset;
445 struct reg_param reg_params[5];
446 struct armv7m_algorithm armv7m_info;
447 int retval = ERROR_OK;
449 static const uint8_t stm32l4_flash_write_code[] = {
450 #include "../../../contrib/loaders/flash/stm32/stm32l4x.inc"
453 if (target_alloc_working_area(target, sizeof(stm32l4_flash_write_code),
454 &write_algorithm) != ERROR_OK) {
455 LOG_WARNING("no working area available, can't do block memory writes");
456 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
459 retval = target_write_buffer(target, write_algorithm->address,
460 sizeof(stm32l4_flash_write_code),
461 stm32l4_flash_write_code);
462 if (retval != ERROR_OK) {
463 target_free_working_area(target, write_algorithm);
468 while (target_alloc_working_area_try(target, buffer_size, &source) !=
471 if (buffer_size <= 256) {
472 /* we already allocated the writing code, but failed to get a
473 * buffer, free the algorithm */
474 target_free_working_area(target, write_algorithm);
476 LOG_WARNING("no large enough working area available, can't do block memory writes");
477 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
481 armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
482 armv7m_info.core_mode = ARM_MODE_THREAD;
484 init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
485 init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
486 init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
487 init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
488 init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash base */
490 buf_set_u32(reg_params[0].value, 0, 32, source->address);
491 buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
492 buf_set_u32(reg_params[2].value, 0, 32, address);
493 buf_set_u32(reg_params[3].value, 0, 32, count / 4);
494 buf_set_u32(reg_params[4].value, 0, 32, STM32_FLASH_BASE);
496 retval = target_run_flash_async_algorithm(target, buffer, count, 2,
499 source->address, source->size,
500 write_algorithm->address, 0,
503 if (retval == ERROR_FLASH_OPERATION_FAILED) {
504 LOG_ERROR("error executing stm32l4 flash write algorithm");
506 uint32_t error = buf_get_u32(reg_params[0].value, 0, 32) & FLASH_ERROR;
508 if (error & FLASH_WRPERR)
509 LOG_ERROR("flash memory write protected");
512 LOG_ERROR("flash write failed = %08" PRIx32, error);
513 /* Clear but report errors */
514 target_write_u32(target, STM32_FLASH_SR, error);
519 target_free_working_area(target, source);
520 target_free_working_area(target, write_algorithm);
522 destroy_reg_param(®_params[0]);
523 destroy_reg_param(®_params[1]);
524 destroy_reg_param(®_params[2]);
525 destroy_reg_param(®_params[3]);
526 destroy_reg_param(®_params[4]);
531 static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
532 uint32_t offset, uint32_t count)
534 struct target *target = bank->target;
537 if (bank->target->state != TARGET_HALTED) {
538 LOG_ERROR("Target not halted");
539 return ERROR_TARGET_NOT_HALTED;
543 LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment",
545 return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
549 LOG_WARNING("Padding %d bytes to keep 8-byte write size",
551 count = (count + 7) & ~7;
552 /* This pads the write chunk with random bytes by overrunning the
553 * write buffer. Padding with the erased pattern 0xff is purely
554 * cosmetical, as 8-byte flash words are ECC secured and the first
555 * write will program the ECC bits. A second write would need
556 * to reprogramm these ECC bits.
557 * But this can only be done after erase!
561 retval = stm32l4_unlock_reg(target);
562 if (retval != ERROR_OK)
565 /* Only full double words (8-byte) can be programmed*/
566 retval = stm32l4_write_block(bank, buffer, offset, count / 2);
567 if (retval != ERROR_OK) {
568 LOG_WARNING("block write failed");
572 LOG_WARNING("block write succeeded");
573 return target_write_u32(target, STM32_FLASH_CR, FLASH_LOCK);
576 static int stm32l4_probe(struct flash_bank *bank)
578 struct target *target = bank->target;
579 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
581 uint16_t flash_size_in_kb = 0xffff;
582 uint16_t max_flash_size_in_kb;
585 uint32_t base_address = 0x08000000;
587 stm32l4_info->probed = 0;
589 /* read stm32 device id register */
590 int retval = target_read_u32(target, DBGMCU_IDCODE, &device_id);
591 if (retval != ERROR_OK)
593 LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
595 /* set max flash size depending on family */
596 switch (device_id & 0xfff) {
599 max_flash_size_in_kb = 1024;
602 max_flash_size_in_kb = 512;
605 max_flash_size_in_kb = 256;
608 LOG_WARNING("Cannot identify target as a STM32L4 family.");
612 /* get flash size from target. */
613 retval = target_read_u16(target, FLASH_SIZE_REG, &flash_size_in_kb);
615 /* failed reading flash size or flash size invalid (early silicon),
616 * default to max target family */
617 if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
618 LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
619 max_flash_size_in_kb);
620 flash_size_in_kb = max_flash_size_in_kb;
623 LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
625 /* did we assign flash size? */
626 assert(flash_size_in_kb != 0xffff);
628 /* get options to for DUAL BANK. */
629 retval = target_read_u32(target, STM32_FLASH_OPTR, &options);
631 if (retval != ERROR_OK)
634 /* only devices with < 1024 kiB may be set to single bank dual banks */
635 if ((flash_size_in_kb == 1024) || !(options & OPT_DUALBANK))
636 stm32l4_info->bank2_start = 256;
638 stm32l4_info->bank2_start = flash_size_in_kb << 9;
640 /* did we assign flash size? */
641 assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
643 /* calculate numbers of pages */
644 int num_pages = flash_size_in_kb / 2;
646 /* check that calculation result makes sense */
647 assert(num_pages > 0);
651 bank->sectors = NULL;
654 bank->base = base_address;
655 bank->size = num_pages * (1 << 11);
656 bank->num_sectors = num_pages;
657 bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
659 return ERROR_FAIL; /* Checkme: What better error to use?*/
661 for (i = 0; i < num_pages; i++) {
662 bank->sectors[i].offset = i << 11;
663 bank->sectors[i].size = 1 << 11;
664 bank->sectors[i].is_erased = -1;
665 bank->sectors[i].is_protected = 1;
668 stm32l4_info->probed = 1;
673 static int stm32l4_auto_probe(struct flash_bank *bank)
675 struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
676 if (stm32l4_info->probed)
678 return stm32l4_probe(bank);
681 static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
683 struct target *target = bank->target;
684 uint32_t dbgmcu_idcode;
686 /* read stm32 device id register */
687 int retval = target_read_u32(target, DBGMCU_IDCODE, &dbgmcu_idcode);
688 if (retval != ERROR_OK)
691 uint16_t device_id = dbgmcu_idcode & 0xfff;
692 uint8_t rev_id = dbgmcu_idcode >> 28;
693 uint8_t rev_minor = 0;
696 for (i = 16; i < 28; i++) {
697 if (dbgmcu_idcode & (1 << i))
703 const char *device_str;
707 device_str = "STM32L496/4A6";
711 device_str = "STM32L475/476/486";
715 device_str = "STM32L45x/46x";
719 device_str = "STM32L43x/44x";
723 snprintf(buf, buf_size, "Cannot identify target as a STM32L4\n");
727 snprintf(buf, buf_size, "%s - Rev: %1d.%02d",
728 device_str, rev_id, rev_minor);
733 static int stm32l4_mass_erase(struct flash_bank *bank, uint32_t action)
736 struct target *target = bank->target;
738 if (target->state != TARGET_HALTED) {
739 LOG_ERROR("Target not halted");
740 return ERROR_TARGET_NOT_HALTED;
743 retval = stm32l4_unlock_reg(target);
744 if (retval != ERROR_OK)
747 /* mass erase flash memory */
748 retval = target_write_u32(
749 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), action);
750 if (retval != ERROR_OK)
752 retval = target_write_u32(
753 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR),
754 action | FLASH_STRT);
755 if (retval != ERROR_OK)
758 retval = stm32l4_wait_status_busy(bank, FLASH_ERASE_TIMEOUT);
759 if (retval != ERROR_OK)
762 retval = target_write_u32(
763 target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_LOCK);
764 if (retval != ERROR_OK)
770 COMMAND_HANDLER(stm32l4_handle_mass_erase_command)
776 command_print(CMD_CTX, "stm32l4x mass_erase <STM32L4 bank>");
777 return ERROR_COMMAND_SYNTAX_ERROR;
780 struct flash_bank *bank;
781 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
782 if (ERROR_OK != retval)
785 action = FLASH_MER1 | FLASH_MER2;
786 retval = stm32l4_mass_erase(bank, action);
787 if (retval == ERROR_OK) {
788 /* set all sectors as erased */
789 for (i = 0; i < bank->num_sectors; i++)
790 bank->sectors[i].is_erased = 1;
792 command_print(CMD_CTX, "stm32l4x mass erase complete");
794 command_print(CMD_CTX, "stm32l4x mass erase failed");
800 COMMAND_HANDLER(stm32l4_handle_option_read_command)
803 command_print(CMD_CTX, "stm32l4x option_read <STM32L4 bank> <option_reg offset>");
804 return ERROR_COMMAND_SYNTAX_ERROR;
807 struct flash_bank *bank;
808 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
809 if (ERROR_OK != retval)
812 uint32_t reg_addr = STM32_FLASH_BASE;
815 reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
817 retval = stm32l4_read_option(bank, reg_addr, &value);
818 if (ERROR_OK != retval)
821 command_print(CMD_CTX, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
826 COMMAND_HANDLER(stm32l4_handle_option_write_command)
829 command_print(CMD_CTX, "stm32l4x option_write <STM32L4 bank> <option_reg offset> <value> [mask]");
830 return ERROR_COMMAND_SYNTAX_ERROR;
833 struct flash_bank *bank;
834 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
835 if (ERROR_OK != retval)
838 uint32_t reg_addr = STM32_FLASH_BASE;
840 uint32_t mask = 0xFFFFFFFF;
842 reg_addr += strtoul(CMD_ARGV[1], NULL, 16);
843 value = strtoul(CMD_ARGV[2], NULL, 16);
845 mask = strtoul(CMD_ARGV[3], NULL, 16);
847 command_print(CMD_CTX, "%s Option written.\n"
848 "INFO: a reset or power cycle is required "
849 "for the new settings to take effect.", bank->driver->name);
851 retval = stm32l4_write_option(bank, reg_addr, value, mask);
855 COMMAND_HANDLER(stm32l4_handle_option_load_command)
858 return ERROR_COMMAND_SYNTAX_ERROR;
860 struct flash_bank *bank;
861 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
862 if (ERROR_OK != retval)
865 struct target *target = bank->target;
867 retval = stm32l4_unlock_reg(target);
868 if (ERROR_OK != retval)
871 retval = stm32l4_unlock_option_reg(target);
872 if (ERROR_OK != retval)
875 /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
876 retval = target_write_u32(target, stm32l4_get_flash_reg(bank, STM32_FLASH_CR), FLASH_OBLLAUNCH);
878 command_print(CMD_CTX, "stm32l4x option load (POR) completed.");
882 COMMAND_HANDLER(stm32l4_handle_lock_command)
884 struct target *target = NULL;
887 return ERROR_COMMAND_SYNTAX_ERROR;
889 struct flash_bank *bank;
890 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
891 if (ERROR_OK != retval)
894 target = bank->target;
896 if (target->state != TARGET_HALTED) {
897 LOG_ERROR("Target not halted");
898 return ERROR_TARGET_NOT_HALTED;
901 /* set readout protection level 1 by erasing the RDP option byte */
902 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, 0, 0x000000FF) != ERROR_OK) {
903 command_print(CMD_CTX, "%s failed to lock device", bank->driver->name);
910 COMMAND_HANDLER(stm32l4_handle_unlock_command)
912 struct target *target = NULL;
915 return ERROR_COMMAND_SYNTAX_ERROR;
917 struct flash_bank *bank;
918 int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
919 if (ERROR_OK != retval)
922 target = bank->target;
924 if (target->state != TARGET_HALTED) {
925 LOG_ERROR("Target not halted");
926 return ERROR_TARGET_NOT_HALTED;
929 if (stm32l4_write_option(bank, STM32_FLASH_OPTR, RDP_LEVEL_0, 0x000000FF) != ERROR_OK) {
930 command_print(CMD_CTX, "%s failed to unlock device", bank->driver->name);
937 static const struct command_registration stm32l4_exec_command_handlers[] = {
940 .handler = stm32l4_handle_lock_command,
941 .mode = COMMAND_EXEC,
943 .help = "Lock entire flash device.",
947 .handler = stm32l4_handle_unlock_command,
948 .mode = COMMAND_EXEC,
950 .help = "Unlock entire protected flash device.",
953 .name = "mass_erase",
954 .handler = stm32l4_handle_mass_erase_command,
955 .mode = COMMAND_EXEC,
957 .help = "Erase entire flash device.",
960 .name = "option_read",
961 .handler = stm32l4_handle_option_read_command,
962 .mode = COMMAND_EXEC,
963 .usage = "bank_id reg_offset",
964 .help = "Read & Display device option bytes.",
967 .name = "option_write",
968 .handler = stm32l4_handle_option_write_command,
969 .mode = COMMAND_EXEC,
970 .usage = "bank_id reg_offset value mask",
971 .help = "Write device option bit fields with provided value.",
974 .name = "option_load",
975 .handler = stm32l4_handle_option_load_command,
976 .mode = COMMAND_EXEC,
978 .help = "Force re-load of device options (will cause device reset).",
980 COMMAND_REGISTRATION_DONE
983 static const struct command_registration stm32l4_command_handlers[] = {
987 .help = "stm32l4x flash command group",
989 .chain = stm32l4_exec_command_handlers,
991 COMMAND_REGISTRATION_DONE
994 struct flash_driver stm32l4x_flash = {
996 .commands = stm32l4_command_handlers,
997 .flash_bank_command = stm32l4_flash_bank_command,
998 .erase = stm32l4_erase,
999 .protect = stm32l4_protect,
1000 .write = stm32l4_write,
1001 .read = default_flash_read,
1002 .probe = stm32l4_probe,
1003 .auto_probe = stm32l4_auto_probe,
1004 .erase_check = default_flash_blank_check,
1005 .protect_check = stm32l4_protect_check,
1006 .info = get_stm32l4_info,
1007 .free_driver_priv = default_flash_free_driver_priv,