1 /***************************************************************************
2 * Copyright (C) 2010 by Antonio Borneo <borneo.antonio@gmail.com> *
4 * This program is free software; you can redistribute it and/or modify *
5 * it under the terms of the GNU General Public License as published by *
6 * the Free Software Foundation; either version 2 of the License, or *
7 * (at your option) any later version. *
9 * This program is distributed in the hope that it will be useful, *
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
12 * GNU General Public License for more details. *
14 * You should have received a copy of the GNU General Public License *
15 * along with this program; if not, write to the *
16 * Free Software Foundation, Inc., *
17 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
18 ***************************************************************************/
20 /* STM Serial Memory Interface (SMI) controller is a SPI bus controller
21 * specifically designed for SPI memories.
22 * Only SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
23 * Two working modes are available:
24 * - SW mode: the SPI is controlled by SW. Any custom commands can be sent
26 * - HW mode: the SPI but is under SMI control. Memory content is directly
27 * accessible in CPU memory space. CPU can read, write and execute memory
31 * To have flash memory mapped in CPU memory space, the SMI controller
32 * have to be in "HW mode". This requires following constraints:
33 * 1) The command "reset init" have to initialize SMI controller and put
35 * 2) every command in this file have to return to prompt in HW mode. */
42 #include <jtag/jtag.h>
43 #include <helper/time_support.h>
45 #define SMI_READ_REG(a) (_SMI_READ_REG(a))
46 #define _SMI_READ_REG(a) \
51 __a = target_read_u32(target, io_base + (a), &__v); \
52 if (__a != ERROR_OK) \
57 #define SMI_WRITE_REG(a,v) \
61 __r = target_write_u32(target, io_base + (a), (v)); \
62 if (__r != ERROR_OK) \
66 #define SMI_POLL_TFF(timeout) \
70 __r = poll_tff(target, io_base, timeout); \
71 if (__r != ERROR_OK) \
75 #define SMI_SET_SW_MODE() SMI_WRITE_REG(SMI_CR1, \
76 SMI_READ_REG(SMI_CR1) | SMI_SW_MODE)
77 #define SMI_SET_HWWB_MODE() SMI_WRITE_REG(SMI_CR1, \
78 (SMI_READ_REG(SMI_CR1) | SMI_WB_MODE) & ~SMI_SW_MODE)
79 #define SMI_SET_HW_MODE() SMI_WRITE_REG(SMI_CR1, \
80 SMI_READ_REG(SMI_CR1) & ~(SMI_SW_MODE | SMI_WB_MODE))
81 #define SMI_CLEAR_TFF() SMI_WRITE_REG(SMI_SR, ~SMI_TFF)
83 #define SMI_BANK_SIZE (0x01000000)
85 #define SMI_CR1 (0x00) /* Control register 1 */
86 #define SMI_CR2 (0x04) /* Control register 2 */
87 #define SMI_SR (0x08) /* Status register */
88 #define SMI_TR (0x0c) /* TX */
89 #define SMI_RR (0x10) /* RX */
91 /* fields in SMI_CR1 */
92 #define SMI_SW_MODE 0x10000000 /* set to enable SW Mode */
93 #define SMI_WB_MODE 0x20000000 /* Write Burst Mode */
95 /* fields in SMI_CR2 */
96 #define SMI_TX_LEN_1 0x00000001 /* data length = 1 byte */
97 #define SMI_TX_LEN_4 0x00000004 /* data length = 4 byte */
98 #define SMI_RX_LEN_3 0x00000030 /* data length = 3 byte */
99 #define SMI_SEND 0x00000080 /* Send data */
100 #define SMI_RSR 0x00000400 /* reads status reg */
101 #define SMI_WE 0x00000800 /* Write Enable */
102 #define SMI_SEL_BANK0 0x00000000 /* Select Bank0 */
103 #define SMI_SEL_BANK1 0x00001000 /* Select Bank1 */
104 #define SMI_SEL_BANK2 0x00002000 /* Select Bank2 */
105 #define SMI_SEL_BANK3 0x00003000 /* Select Bank3 */
107 /* fields in SMI_SR */
108 #define SMI_WIP_BIT 0x00000001 /* WIP Bit of SPI SR on SMI SR */
109 #define SMI_WEL_BIT 0x00000002 /* WEL Bit of SPI SR on SMI SR */
110 #define SMI_TFF 0x00000100 /* Transfer Finished Flag */
113 #define SMI_READ_ID 0x0000009F /* Read Flash Identification */
116 #define SMI_CMD_TIMEOUT (100)
117 #define SMI_PROBE_TIMEOUT (100)
118 #define SMI_MAX_TIMEOUT (3000)
120 struct stmsmi_flash_bank
125 struct flash_device *dev;
128 /* data structure to maintain flash ids from different vendors */
129 struct flash_device {
134 unsigned long sectorsize;
135 unsigned long size_in_bytes;
138 #define FLASH_ID(n, es, id, psize, ssize, size) \
144 .sectorsize = ssize, \
145 .size_in_bytes = size \
148 /* List below is taken from Linux driver. It is not exhaustive of all the
149 * possible SPI memories, nor exclusive for SMI. Could be shared with
150 * other SPI drivers. */
151 static struct flash_device flash_devices[] = {
152 /* name, erase_cmd, device_id, pagesize, sectorsize, size_in_bytes */
153 FLASH_ID("st m25p05", 0xd8, 0x00102020, 0x80, 0x8000, 0x10000),
154 FLASH_ID("st m25p10", 0xd8, 0x00112020, 0x80, 0x8000, 0x20000),
155 FLASH_ID("st m25p20", 0xd8, 0x00122020, 0x100, 0x10000, 0x40000),
156 FLASH_ID("st m25p40", 0xd8, 0x00132020, 0x100, 0x10000, 0x80000),
157 FLASH_ID("st m25p80", 0xd8, 0x00142020, 0x100, 0x10000, 0x100000),
158 FLASH_ID("st m25p16", 0xd8, 0x00152020, 0x100, 0x10000, 0x200000),
159 FLASH_ID("st m25p32", 0xd8, 0x00162020, 0x100, 0x10000, 0x400000),
160 FLASH_ID("st m25p64", 0xd8, 0x00172020, 0x100, 0x10000, 0x800000),
161 FLASH_ID("st m25p128", 0xd8, 0x00182020, 0x100, 0x40000, 0x1000000),
162 FLASH_ID("st m45pe10", 0xd8, 0x00114020, 0x100, 0x10000, 0x20000),
163 FLASH_ID("st m45pe20", 0xd8, 0x00124020, 0x100, 0x10000, 0x40000),
164 FLASH_ID("st m45pe40", 0xd8, 0x00134020, 0x100, 0x10000, 0x80000),
165 FLASH_ID("st m45pe80", 0xd8, 0x00144020, 0x100, 0x10000, 0x100000),
166 FLASH_ID("sp s25fl004", 0xd8, 0x00120201, 0x100, 0x10000, 0x80000),
167 FLASH_ID("sp s25fl008", 0xd8, 0x00130201, 0x100, 0x10000, 0x100000),
168 FLASH_ID("sp s25fl016", 0xd8, 0x00140201, 0x100, 0x10000, 0x200000),
169 FLASH_ID("sp s25fl032", 0xd8, 0x00150201, 0x100, 0x10000, 0x400000),
170 FLASH_ID("sp s25fl064", 0xd8, 0x00160201, 0x100, 0x10000, 0x800000),
171 FLASH_ID("atmel 25f512", 0x52, 0x0065001f, 0x80, 0x8000, 0x10000),
172 FLASH_ID("atmel 25f1024", 0x52, 0x0060001f, 0x100, 0x8000, 0x20000),
173 FLASH_ID("atmel 25f2048", 0x52, 0x0063001f, 0x100, 0x10000, 0x40000),
174 FLASH_ID("atmel 25f4096", 0x52, 0x0064001f, 0x100, 0x10000, 0x80000),
175 FLASH_ID("atmel 25fs040", 0xd7, 0x0004661f, 0x100, 0x10000, 0x80000),
176 FLASH_ID("mac 25l512", 0xd8, 0x001020c2, 0x010, 0x10000, 0x10000),
177 FLASH_ID("mac 25l1005", 0xd8, 0x001120c2, 0x010, 0x10000, 0x20000),
178 FLASH_ID("mac 25l2005", 0xd8, 0x001220c2, 0x010, 0x10000, 0x40000),
179 FLASH_ID("mac 25l4005", 0xd8, 0x001320c2, 0x010, 0x10000, 0x80000),
180 FLASH_ID("mac 25l8005", 0xd8, 0x001420c2, 0x010, 0x10000, 0x100000),
181 FLASH_ID("mac 25l1605", 0xd8, 0x001520c2, 0x100, 0x10000, 0x200000),
182 FLASH_ID("mac 25l3205", 0xd8, 0x001620c2, 0x100, 0x10000, 0x400000),
183 FLASH_ID("mac 25l6405", 0xd8, 0x001720c2, 0x100, 0x10000, 0x800000),
184 FLASH_ID(NULL, 0, 0, 0, 0, 0)
187 struct stmsmi_target {
194 static struct stmsmi_target target_devices[] = {
195 /* name, tap_idcode, smi_base, io_base */
196 { "SPEAr3xx/6xx", 0x07926041, 0xf8000000, 0xfc000000 },
197 { "STR75x", 0x4f1f0041, 0x80000000, 0x90000000 },
201 FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
203 struct stmsmi_flash_bank *stmsmi_info;
205 LOG_DEBUG("%s", __FUNCTION__);
209 return ERROR_COMMAND_SYNTAX_ERROR;
212 stmsmi_info = malloc(sizeof(struct stmsmi_flash_bank));
213 if (stmsmi_info == NULL)
215 LOG_ERROR("not enough memory");
219 bank->driver_priv = stmsmi_info;
220 stmsmi_info->probed = 0;
225 /* Poll transmit finished flag */
227 static int poll_tff(struct target *target, uint32_t io_base, int timeout)
231 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
234 endtime = timeval_ms() + timeout;
237 if (SMI_READ_REG(SMI_SR) & SMI_TFF)
239 } while (timeval_ms() < endtime);
241 LOG_ERROR("Timeout while polling TFF");
242 return ERROR_FLASH_OPERATION_FAILED;
245 /* Read the status register of the external SPI flash chip.
246 * The operation is triggered by setting SMI_RSR bit.
247 * SMI sends the proper SPI command (0x05) and returns value in SMI_SR */
248 static int read_status_reg(struct flash_bank *bank, uint32_t *status)
250 struct target *target = bank->target;
251 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
252 uint32_t io_base = stmsmi_info->io_base;
254 /* clear transmit finished flag */
258 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_RSR);
260 /* Poll transmit finished flag */
261 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
263 /* clear transmit finished flag */
266 *status = SMI_READ_REG(SMI_SR) & 0x0000ffff;
268 /* clean-up SMI_CR2 */
269 SMI_WRITE_REG(SMI_CR2, 0); /* AB: Required ? */
274 /* check for WIP (write in progress) bit in status register */
276 static int wait_till_ready(struct flash_bank *bank, int timeout)
282 endtime = timeval_ms() + timeout;
284 /* read flash status register */
285 retval = read_status_reg(bank, &status);
286 if (retval != ERROR_OK)
289 if ((status & SMI_WIP_BIT) == 0)
292 } while (timeval_ms() < endtime);
294 LOG_ERROR("timeout");
298 /* Send "write enable" command to SPI flash chip.
299 * The operation is triggered by setting SMI_WE bit, and SMI sends
300 * the proper SPI command (0x06) */
301 static int smi_write_enable(struct flash_bank *bank)
303 struct target *target = bank->target;
304 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
305 uint32_t io_base = stmsmi_info->io_base;
309 /* Enter in HW mode */
310 SMI_SET_HW_MODE(); /* AB: is this correct ?*/
312 /* clear transmit finished flag */
315 /* Send write enable command */
316 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_WE);
318 /* Poll transmit finished flag */
319 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
321 /* read flash status register */
322 retval = read_status_reg(bank, &status);
323 if (retval != ERROR_OK)
326 /* Check write enabled */
327 if ((status & SMI_WEL_BIT) == 0)
329 LOG_ERROR("Cannot enable write to flash. Status=0x%08" PRIx32, status);
336 static uint32_t erase_command(struct stmsmi_flash_bank *stmsmi_info,
344 cmd.x[0] = stmsmi_info->dev->erase_cmd;
345 cmd.x[1] = offset >> 16;
346 cmd.x[2] = offset >> 8;
352 static int smi_erase_sector(struct flash_bank *bank, int sector)
354 struct target *target = bank->target;
355 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
356 uint32_t io_base = stmsmi_info->io_base;
360 retval = smi_write_enable(bank);
361 if (retval != ERROR_OK)
364 /* Switch to SW mode to send sector erase command */
367 /* clear transmit finished flag */
370 /* send SPI command "block erase" */
371 cmd = erase_command(stmsmi_info, bank->sectors[sector].offset);
372 SMI_WRITE_REG(SMI_TR, cmd);
373 SMI_WRITE_REG(SMI_CR2, stmsmi_info->bank_num | SMI_SEND | SMI_TX_LEN_4);
375 /* Poll transmit finished flag */
376 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
378 /* poll WIP for end of self timed Sector Erase cycle */
379 retval = wait_till_ready(bank, SMI_MAX_TIMEOUT);
380 if (retval != ERROR_OK)
386 static int stmsmi_erase(struct flash_bank *bank, int first, int last)
388 struct target *target = bank->target;
389 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
390 uint32_t io_base = stmsmi_info->io_base;
391 int retval = ERROR_OK;
394 LOG_DEBUG("%s: from sector %d to sector %d", __FUNCTION__, first, last);
396 if (target->state != TARGET_HALTED)
398 LOG_ERROR("Target not halted");
399 return ERROR_TARGET_NOT_HALTED;
402 if ((first < 0) || (last < first) || (last >= bank->num_sectors))
404 LOG_ERROR("Flash sector invalid");
405 return ERROR_FLASH_SECTOR_INVALID;
408 if (!(stmsmi_info->probed))
410 LOG_ERROR("Flash bank not probed");
411 return ERROR_FLASH_BANK_NOT_PROBED;
414 for (sector = first; sector <= last; sector++)
416 if (bank->sectors[sector].is_protected)
418 LOG_ERROR("Flash sector %d protected", sector);
423 for (sector = first; sector <= last; sector++)
425 retval = smi_erase_sector(bank, sector);
426 if (retval != ERROR_OK)
431 /* Switch to HW mode before return to prompt */
436 static int stmsmi_protect(struct flash_bank *bank, int set,
441 for (sector = first; sector <= last; sector++)
442 bank->sectors[sector].is_protected = set;
446 static int smi_write_buffer(struct flash_bank *bank, uint8_t *buffer,
447 uint32_t address, uint32_t len)
449 struct target *target = bank->target;
450 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
451 uint32_t io_base = stmsmi_info->io_base;
454 LOG_DEBUG("%s: address=0x%08" PRIx32 " len=0x%08" PRIx32,
455 __FUNCTION__, address, len);
457 retval = smi_write_enable(bank);
458 if (retval != ERROR_OK)
461 /* HW mode, write burst mode */
464 retval = target_write_buffer(target, address, len, buffer);
465 if (retval != ERROR_OK)
471 static int stmsmi_write(struct flash_bank *bank, uint8_t *buffer,
472 uint32_t offset, uint32_t count)
474 struct target *target = bank->target;
475 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
476 uint32_t io_base = stmsmi_info->io_base;
477 uint32_t cur_count, page_size, page_offset;
479 int retval = ERROR_OK;
481 LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
482 __FUNCTION__, offset, count);
484 if (target->state != TARGET_HALTED)
486 LOG_ERROR("Target not halted");
487 return ERROR_TARGET_NOT_HALTED;
490 if (offset + count > stmsmi_info->dev->size_in_bytes)
492 LOG_WARNING("Write pasts end of flash. Extra data discarded.");
493 count = stmsmi_info->dev->size_in_bytes - offset;
496 /* Check sector protection */
497 for (sector = 0; sector < bank->num_sectors; sector++)
499 /* Start offset in or before this sector? */
500 /* End offset in or behind this sector? */
502 (bank->sectors[sector].offset + bank->sectors[sector].size))
503 && ((offset + count - 1) >= bank->sectors[sector].offset)
504 && bank->sectors[sector].is_protected )
506 LOG_ERROR("Flash sector %d protected", sector);
511 page_size = stmsmi_info->dev->pagesize;
513 /* unaligned buffer head */
514 if (count > 0 && (offset & 3) != 0)
516 cur_count = 4 - (offset & 3);
517 if (cur_count > count)
519 retval = smi_write_buffer(bank, buffer, bank->base + offset,
521 if (retval != ERROR_OK)
528 page_offset = offset % page_size;
529 /* central part, aligned words */
532 /* clip block at page boundary */
533 if (page_offset + count > page_size)
534 cur_count = page_size - page_offset;
536 cur_count = count & ~3;
538 retval = smi_write_buffer(bank, buffer, bank->base + offset,
540 if (retval != ERROR_OK)
553 retval = smi_write_buffer(bank, buffer, bank->base + offset, count);
556 /* Switch to HW mode before return to prompt */
561 /* Return ID of flash device */
562 /* On exit, SW mode is kept */
563 static int read_flash_id(struct flash_bank *bank, uint32_t *id)
565 struct target *target = bank->target;
566 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
567 uint32_t io_base = stmsmi_info->io_base;
570 if (target->state != TARGET_HALTED)
572 LOG_ERROR("Target not halted");
573 return ERROR_TARGET_NOT_HALTED;
577 retval = wait_till_ready(bank, SMI_PROBE_TIMEOUT);
578 if (retval != ERROR_OK)
581 /* enter in SW mode */
584 /* clear transmit finished flag */
587 /* Send SPI command "read ID" */
588 SMI_WRITE_REG(SMI_TR, SMI_READ_ID);
589 SMI_WRITE_REG(SMI_CR2,
590 stmsmi_info->bank_num | SMI_SEND | SMI_RX_LEN_3 | SMI_TX_LEN_1);
592 /* Poll transmit finished flag */
593 SMI_POLL_TFF(SMI_CMD_TIMEOUT);
595 /* clear transmit finished flag */
598 /* read ID from Receive Register */
599 *id = SMI_READ_REG(SMI_RR) & 0x00ffffff;
603 static int stmsmi_probe(struct flash_bank *bank)
605 struct target *target = bank->target;
606 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
608 struct flash_sector *sectors;
609 uint32_t id = 0; /* silence uninitialized warning */
610 struct stmsmi_target *target_device;
613 if (stmsmi_info->probed)
615 stmsmi_info->probed = 0;
617 for (target_device=target_devices ; target_device->name ; ++target_device)
618 if (target_device->tap_idcode == target->tap->idcode)
620 if (!target_device->name)
622 LOG_ERROR("Device ID 0x%" PRIx32 " is not known as SMI capable",
623 target->tap->idcode);
627 switch (bank->base - target_device->smi_base)
630 stmsmi_info->bank_num = SMI_SEL_BANK0;
633 stmsmi_info->bank_num = SMI_SEL_BANK1;
635 case 2*SMI_BANK_SIZE:
636 stmsmi_info->bank_num = SMI_SEL_BANK2;
638 case 3*SMI_BANK_SIZE:
639 stmsmi_info->bank_num = SMI_SEL_BANK3;
642 LOG_ERROR("Invalid SMI base address 0x%" PRIx32, bank->base);
645 io_base = target_device->io_base;
646 stmsmi_info->io_base = io_base;
648 LOG_DEBUG("Valid SMI on device %s at address 0x%" PRIx32,
649 target_device->name, bank->base);
651 /* read and decode flash ID; returns in SW mode */
652 retval = read_flash_id(bank, &id);
654 if (retval != ERROR_OK)
657 stmsmi_info->dev = NULL;
658 for (struct flash_device *p = flash_devices; p->name ; p++)
659 if (p->device_id == id) {
660 stmsmi_info->dev = p;
664 if (!stmsmi_info->dev)
666 LOG_ERROR("Unknown flash device (ID 0x%08" PRIx32 ")", id);
670 LOG_INFO("Found flash device \'%s\' (ID 0x%08" PRIx32 ")",
671 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
673 /* Set correct size value */
674 bank->size = stmsmi_info->dev->size_in_bytes;
676 /* create and fill sectors array */
678 stmsmi_info->dev->size_in_bytes / stmsmi_info->dev->sectorsize;
679 sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
682 LOG_ERROR("not enough memory");
686 for (int sector = 0; sector < bank->num_sectors; sector++)
688 sectors[sector].offset = sector * stmsmi_info->dev->sectorsize;
689 sectors[sector].size = stmsmi_info->dev->sectorsize;
690 sectors[sector].is_erased = -1;
691 sectors[sector].is_protected = 1;
694 bank->sectors = sectors;
695 stmsmi_info->probed = 1;
699 static int stmsmi_auto_probe(struct flash_bank *bank)
701 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
702 if (stmsmi_info->probed)
704 return stmsmi_probe(bank);
707 static int stmsmi_protect_check(struct flash_bank *bank)
709 /* Nothing to do. Protection is only handled in SW. */
713 static int get_stmsmi_info(struct flash_bank *bank, char *buf, int buf_size)
715 struct stmsmi_flash_bank *stmsmi_info = bank->driver_priv;
717 if (!(stmsmi_info->probed))
719 snprintf(buf, buf_size,
720 "\nSMI flash bank not probed yet\n");
724 snprintf(buf, buf_size, "\nSMI flash information:\n"
725 " Device \'%s\' (ID 0x%08x)\n",
726 stmsmi_info->dev->name, stmsmi_info->dev->device_id);
731 struct flash_driver stmsmi_flash = {
733 .flash_bank_command = stmsmi_flash_bank_command,
734 .erase = stmsmi_erase,
735 .protect = stmsmi_protect,
736 .write = stmsmi_write,
737 .read = default_flash_read,
738 .probe = stmsmi_probe,
739 .auto_probe = stmsmi_auto_probe,
740 .erase_check = default_flash_blank_check,
741 .protect_check = stmsmi_protect_check,
742 .info = get_stmsmi_info,